3467 lines
94 KiB
Plaintext
3467 lines
94 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<208>;
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.reg .b16 %rs<327>;
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.reg .f32 %f<2058>;
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.reg .b32 %r<487>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<179>;
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mov.u64 %SPL, __local_depot0;
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cvta.local.u64 %SP, %SPL;
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// begin inline asm
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call (%r59), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r60), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+616];
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ld.const.u32 %r4, [params+540];
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shl.b32 %r5, %r4, 1;
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ld.const.u64 %rd43, [params+400];
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cvta.to.global.u64 %rd44, %rd43;
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ld.const.u32 %r65, [params+392];
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mad.lo.s32 %r66, %r65, %r60, %r59;
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mul.wide.u32 %rd45, %r66, 4;
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add.s64 %rd1, %rd44, %rd45;
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ld.global.v2.u8 {%rs7, %rs326}, [%rd1];
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or.b16 %rs9, %rs7, %rs326;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p10, %rs10, 0;
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@%p10 bra $L__BB0_2;
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ld.global.u8 %rs325, [%rd1+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs325, [%rd1+2];
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setp.eq.s16 %p11, %rs325, 0;
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mov.f32 %f1811, 0f00000000;
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mov.u16 %rs326, 0;
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mov.f32 %f1812, %f1811;
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mov.f32 %f1813, %f1811;
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@%p11 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f556, %rs7;
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div.rn.f32 %f557, %f556, 0f437F0000;
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fma.rn.f32 %f558, %f557, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs326, 255;
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cvt.rn.f32.u16 %f559, %rs13;
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div.rn.f32 %f560, %f559, 0f437F0000;
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fma.rn.f32 %f561, %f560, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f562, %rs325;
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div.rn.f32 %f563, %f562, 0f437F0000;
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fma.rn.f32 %f564, %f563, 0f40000000, 0fBF800000;
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mul.f32 %f565, %f561, %f561;
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fma.rn.f32 %f566, %f558, %f558, %f565;
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fma.rn.f32 %f567, %f564, %f564, %f566;
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sqrt.rn.f32 %f568, %f567;
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rcp.rn.f32 %f569, %f568;
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mul.f32 %f1813, %f569, %f564;
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mul.f32 %f1812, %f569, %f561;
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mul.f32 %f1811, %f558, %f569;
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$L__BB0_4:
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ld.const.v2.u32 {%r67, %r68}, [params];
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add.s32 %r6, %r67, %r59;
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add.s32 %r7, %r68, %r60;
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setp.eq.f32 %p12, %f1811, 0f00000000;
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setp.eq.f32 %p13, %f1812, 0f00000000;
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and.pred %p14, %p12, %p13;
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setp.eq.f32 %p15, %f1813, 0f00000000;
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and.pred %p16, %p15, %p14;
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@%p16 bra $L__BB0_173;
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bra.uni $L__BB0_5;
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$L__BB0_173:
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ld.const.u32 %r56, [params+104];
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and.b32 %r442, %r56, 1;
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setp.eq.b32 %p191, %r442, 1;
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mov.pred %p192, 0;
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xor.pred %p193, %p191, %p192;
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not.pred %p194, %p193;
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@%p194 bra $L__BB0_175;
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ld.const.u64 %rd136, [params+144];
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cvta.to.global.u64 %rd137, %rd136;
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ld.const.u32 %r443, [params+136];
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mad.lo.s32 %r444, %r443, %r7, %r6;
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mul.wide.u32 %rd138, %r444, 4;
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add.s64 %rd139, %rd137, %rd138;
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mov.u16 %rs172, 0;
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st.global.v4.u8 [%rd139], {%rs172, %rs172, %rs172, %rs172};
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$L__BB0_175:
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and.b32 %r445, %r56, 8;
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setp.eq.s32 %p195, %r445, 0;
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@%p195 bra $L__BB0_177;
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ld.const.u64 %rd140, [params+192];
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cvta.to.global.u64 %rd141, %rd140;
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ld.const.u32 %r446, [params+184];
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mad.lo.s32 %r447, %r446, %r7, %r6;
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mov.f32 %f1714, 0f00000000;
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cvt.rzi.u32.f32 %r448, %f1714;
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mul.wide.u32 %rd142, %r447, 2;
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add.s64 %rd143, %rd141, %rd142;
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mov.u16 %rs173, 0;
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cvt.u16.u32 %rs174, %r448;
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st.global.v2.u8 [%rd143], {%rs174, %rs173};
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$L__BB0_177:
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and.b32 %r449, %r56, 4;
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setp.eq.s32 %p196, %r449, 0;
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ld.const.u32 %r486, [params+108];
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@%p196 bra $L__BB0_181;
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setp.eq.s32 %p197, %r486, 0;
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ld.const.u64 %rd144, [params+224];
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cvta.to.global.u64 %rd145, %rd144;
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ld.const.u32 %r450, [params+216];
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mad.lo.s32 %r451, %r450, %r7, %r6;
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mul.wide.u32 %rd146, %r451, 8;
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add.s64 %rd33, %rd145, %rd146;
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@%p197 bra $L__BB0_180;
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ld.global.v4.u16 {%rs181, %rs182, %rs183, %rs184}, [%rd33];
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// begin inline asm
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{ cvt.f32.f16 %f1715, %rs181;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1716, %rs182;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1717, %rs183;}
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// end inline asm
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add.f32 %f1718, %f1715, 0f00000000;
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add.f32 %f1719, %f1716, 0f00000000;
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add.f32 %f1720, %f1717, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs180, %f1720;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs179, %f1719;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs178, %f1718;}
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// end inline asm
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mov.u16 %rs185, 0;
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st.global.v4.u16 [%rd33], {%rs178, %rs179, %rs180, %rs185};
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bra.uni $L__BB0_181;
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$L__BB0_5:
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ld.const.u64 %rd46, [params+432];
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cvta.to.global.u64 %rd47, %rd46;
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ld.const.u32 %r72, [params+424];
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mad.lo.s32 %r73, %r72, %r60, %r59;
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mul.wide.u32 %rd48, %r73, 12;
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add.s64 %rd49, %rd47, %rd48;
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ld.global.f32 %f10, [%rd49];
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mul.f32 %f601, %f10, 0f3456BF95;
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ld.global.f32 %f11, [%rd49+4];
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mul.f32 %f602, %f11, 0f3456BF95;
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ld.global.f32 %f12, [%rd49+8];
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mul.f32 %f603, %f12, 0f3456BF95;
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abs.f32 %f604, %f1811;
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div.rn.f32 %f605, %f601, %f604;
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abs.f32 %f606, %f1812;
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div.rn.f32 %f607, %f602, %f606;
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abs.f32 %f608, %f1813;
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div.rn.f32 %f609, %f603, %f608;
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abs.f32 %f610, %f605;
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abs.f32 %f611, %f607;
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abs.f32 %f612, %f609;
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mov.f32 %f613, 0f38D1B717;
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max.f32 %f614, %f610, %f613;
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max.f32 %f615, %f611, %f613;
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max.f32 %f616, %f612, %f613;
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fma.rn.f32 %f13, %f1811, %f614, %f10;
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fma.rn.f32 %f14, %f1812, %f615, %f11;
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fma.rn.f32 %f15, %f1813, %f616, %f12;
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ld.const.u64 %rd50, [params+128];
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cvta.to.global.u64 %rd51, %rd50;
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ld.const.u32 %r74, [params+120];
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mad.lo.s32 %r75, %r74, %r60, %r59;
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mul.wide.u32 %rd52, %r75, 4;
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add.s64 %rd53, %rd51, %rd52;
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ld.global.u32 %r477, [%rd53];
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mov.u32 %r473, 0;
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abs.s32 %r76, %r3;
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setp.lt.s32 %p18, %r76, 1;
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mov.pred %p17, 0;
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mov.f32 %f1848, 0f00000000;
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mov.f32 %f1849, %f1848;
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mov.f32 %f1850, %f1848;
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mov.f32 %f1851, %f1848;
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mov.f32 %f1852, %f1848;
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mov.f32 %f1853, %f1848;
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mov.f32 %f1854, %f1848;
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mov.f32 %f1855, %f1848;
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mov.f32 %f1856, %f1848;
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mov.f32 %f1857, %f1848;
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mov.f32 %f1858, %f1848;
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mov.f32 %f1859, %f1848;
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mov.f32 %f1860, %f1848;
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mov.f32 %f1861, %f1848;
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mov.f32 %f1862, %f1848;
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mov.f32 %f1863, %f1848;
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mov.f32 %f1864, %f1848;
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mov.f32 %f1865, %f1848;
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mov.f32 %f1866, %f1848;
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mov.f32 %f1867, %f1848;
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mov.f32 %f1868, %f1848;
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mov.f32 %f1869, %f1848;
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mov.f32 %f1870, %f1848;
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mov.f32 %f1871, %f1848;
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mov.f32 %f1872, %f1848;
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mov.f32 %f1873, %f1848;
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mov.f32 %f1874, %f1848;
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mov.f32 %f1875, %f1848;
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mov.f32 %f1876, %f1848;
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mov.f32 %f1877, %f1848;
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mov.f32 %f1878, %f1848;
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mov.pred %p207, %p17;
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@%p18 bra $L__BB0_23;
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ld.const.f32 %f16, [params+620];
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ld.const.u64 %rd54, [params+624];
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cvta.to.global.u64 %rd2, %rd54;
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ld.const.u64 %rd55, [params+640];
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cvta.to.global.u64 %rd56, %rd55;
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ld.const.u32 %r78, [params+632];
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and.b32 %r79, %r60, 255;
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and.b32 %r80, %r59, 255;
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mad.lo.s32 %r81, %r78, %r79, %r80;
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mul.wide.u32 %rd57, %r81, 3;
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add.s64 %rd3, %rd56, %rd57;
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ld.const.f32 %f17, [params+660];
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mul.f32 %f18, %f13, 0f3456BF95;
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mul.f32 %f19, %f14, 0f3456BF95;
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mul.f32 %f20, %f15, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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abs.f32 %f775, %f19;
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abs.f32 %f776, %f18;
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max.f32 %f777, %f776, %f775;
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abs.f32 %f778, %f20;
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max.f32 %f779, %f777, %f778;
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$L__BB0_7:
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mul.lo.s32 %r82, %r473, 3;
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mul.wide.s32 %rd58, %r82, 12;
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add.s64 %rd59, %rd2, %rd58;
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ld.global.f32 %f648, [%rd59];
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sub.f32 %f649, %f648, %f10;
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ld.global.f32 %f650, [%rd59+4];
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sub.f32 %f651, %f650, %f11;
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ld.global.f32 %f652, [%rd59+8];
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sub.f32 %f653, %f652, %f12;
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mul.f32 %f654, %f651, %f651;
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fma.rn.f32 %f655, %f649, %f649, %f654;
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fma.rn.f32 %f656, %f653, %f653, %f655;
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sqrt.rn.f32 %f52, %f656;
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rcp.rn.f32 %f657, %f52;
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mul.f32 %f53, %f649, %f657;
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mul.f32 %f54, %f651, %f657;
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mul.f32 %f55, %f653, %f657;
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mul.f32 %f658, %f52, %f52;
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div.rn.f32 %f56, %f16, %f658;
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ld.global.u8 %rs15, [%rd3];
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cvt.rn.f32.u16 %f659, %rs15;
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div.rn.f32 %f660, %f659, 0fC37F0000;
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fma.rn.f32 %f661, %f660, 0f3F333333, 0f3F800000;
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setp.gt.f32 %p20, %f56, %f661;
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setp.ne.s32 %p21, %r4, 0;
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and.pred %p22, %p21, %p20;
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mov.pred %p207, -1;
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@%p22 bra $L__BB0_23;
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mul.f32 %f57, %f52, %f17;
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mov.f32 %f666, 0f40800000;
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abs.f32 %f59, %f57;
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setp.lt.f32 %p23, %f59, 0f00800000;
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mul.f32 %f668, %f59, 0f4B800000;
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selp.f32 %f669, %f668, %f59, %p23;
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selp.f32 %f670, 0fC3170000, 0fC2FE0000, %p23;
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mov.b32 %r83, %f669;
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and.b32 %r84, %r83, 8388607;
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or.b32 %r85, %r84, 1065353216;
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mov.b32 %f671, %r85;
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shr.u32 %r86, %r83, 23;
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cvt.rn.f32.u32 %f672, %r86;
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add.f32 %f673, %f670, %f672;
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setp.gt.f32 %p24, %f671, 0f3FB504F3;
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mul.f32 %f674, %f671, 0f3F000000;
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add.f32 %f675, %f673, 0f3F800000;
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selp.f32 %f676, %f675, %f673, %p24;
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selp.f32 %f677, %f674, %f671, %p24;
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add.f32 %f678, %f677, 0fBF800000;
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add.f32 %f679, %f677, 0f3F800000;
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rcp.approx.ftz.f32 %f680, %f679;
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add.f32 %f681, %f678, %f678;
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mul.f32 %f682, %f681, %f680;
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mul.f32 %f683, %f682, %f682;
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mov.f32 %f684, 0f3C4CAF63;
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mov.f32 %f685, 0f3B18F0FE;
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fma.rn.f32 %f686, %f685, %f683, %f684;
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mov.f32 %f687, 0f3DAAAABD;
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fma.rn.f32 %f688, %f686, %f683, %f687;
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mul.rn.f32 %f689, %f688, %f683;
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mul.rn.f32 %f690, %f689, %f682;
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sub.f32 %f691, %f678, %f682;
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add.f32 %f692, %f691, %f691;
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neg.f32 %f693, %f682;
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fma.rn.f32 %f694, %f693, %f678, %f692;
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mul.rn.f32 %f695, %f680, %f694;
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add.f32 %f696, %f690, %f682;
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sub.f32 %f697, %f682, %f696;
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add.f32 %f698, %f690, %f697;
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add.f32 %f699, %f695, %f698;
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add.f32 %f700, %f696, %f699;
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sub.f32 %f701, %f696, %f700;
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add.f32 %f702, %f699, %f701;
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mov.f32 %f703, 0f3F317200;
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mul.rn.f32 %f704, %f676, %f703;
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mov.f32 %f705, 0f35BFBE8E;
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mul.rn.f32 %f706, %f676, %f705;
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add.f32 %f707, %f704, %f700;
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sub.f32 %f708, %f704, %f707;
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add.f32 %f709, %f700, %f708;
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add.f32 %f710, %f702, %f709;
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add.f32 %f711, %f706, %f710;
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add.f32 %f712, %f707, %f711;
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sub.f32 %f713, %f707, %f712;
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add.f32 %f714, %f711, %f713;
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mul.rn.f32 %f715, %f666, %f712;
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neg.f32 %f716, %f715;
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fma.rn.f32 %f717, %f666, %f712, %f716;
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fma.rn.f32 %f718, %f666, %f714, %f717;
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mov.f32 %f719, 0f00000000;
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fma.rn.f32 %f720, %f719, %f712, %f718;
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add.rn.f32 %f721, %f715, %f720;
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neg.f32 %f722, %f721;
|
|
add.rn.f32 %f723, %f715, %f722;
|
|
add.rn.f32 %f724, %f723, %f720;
|
|
mov.b32 %r87, %f721;
|
|
setp.eq.s32 %p25, %r87, 1118925336;
|
|
add.s32 %r88, %r87, -1;
|
|
mov.b32 %f725, %r88;
|
|
add.f32 %f726, %f724, 0f37000000;
|
|
selp.f32 %f60, %f726, %f724, %p25;
|
|
selp.f32 %f727, %f725, %f721, %p25;
|
|
mov.f32 %f728, 0f3FB8AA3B;
|
|
mul.rn.f32 %f729, %f727, %f728;
|
|
cvt.rzi.f32.f32 %f730, %f729;
|
|
abs.f32 %f731, %f730;
|
|
setp.gt.f32 %p26, %f731, 0f42FC0000;
|
|
mov.b32 %r89, %f730;
|
|
and.b32 %r90, %r89, -2147483648;
|
|
or.b32 %r91, %r90, 1123811328;
|
|
mov.b32 %f732, %r91;
|
|
selp.f32 %f733, %f732, %f730, %p26;
|
|
mov.f32 %f734, 0fBF317218;
|
|
fma.rn.f32 %f735, %f733, %f734, %f727;
|
|
mov.f32 %f736, 0f3102E308;
|
|
fma.rn.f32 %f737, %f733, %f736, %f735;
|
|
mul.f32 %f738, %f737, 0f3FB8AA3B;
|
|
add.f32 %f739, %f733, 0f4B40007F;
|
|
mov.b32 %r92, %f739;
|
|
shl.b32 %r93, %r92, 23;
|
|
mov.b32 %f740, %r93;
|
|
ex2.approx.ftz.f32 %f741, %f738;
|
|
mul.f32 %f61, %f741, %f740;
|
|
setp.eq.f32 %p27, %f61, 0f7F800000;
|
|
mov.f32 %f1845, 0f7F800000;
|
|
@%p27 bra $L__BB0_10;
|
|
|
|
fma.rn.f32 %f1845, %f61, %f60, %f61;
|
|
|
|
$L__BB0_10:
|
|
mov.f32 %f1810, 0f40000000;
|
|
cvt.rzi.f32.f32 %f1809, %f1810;
|
|
add.f32 %f1808, %f1809, %f1809;
|
|
mov.f32 %f1807, 0f40800000;
|
|
sub.f32 %f1806, %f1807, %f1808;
|
|
abs.f32 %f1805, %f1806;
|
|
setp.lt.f32 %p28, %f57, 0f00000000;
|
|
setp.eq.f32 %p29, %f1805, 0f3F800000;
|
|
and.pred %p1, %p28, %p29;
|
|
setp.eq.f32 %p30, %f57, 0f00000000;
|
|
@%p30 bra $L__BB0_14;
|
|
bra.uni $L__BB0_11;
|
|
|
|
$L__BB0_14:
|
|
add.f32 %f746, %f57, %f57;
|
|
selp.f32 %f1847, %f746, 0f00000000, %p29;
|
|
bra.uni $L__BB0_15;
|
|
|
|
$L__BB0_11:
|
|
mov.b32 %r94, %f1845;
|
|
xor.b32 %r95, %r94, -2147483648;
|
|
mov.b32 %f742, %r95;
|
|
selp.f32 %f1847, %f742, %f1845, %p1;
|
|
setp.geu.f32 %p31, %f57, 0f00000000;
|
|
@%p31 bra $L__BB0_15;
|
|
|
|
mov.f32 %f743, 0f40800000;
|
|
cvt.rzi.f32.f32 %f744, %f743;
|
|
setp.eq.f32 %p32, %f744, 0f40800000;
|
|
@%p32 bra $L__BB0_15;
|
|
|
|
mov.f32 %f1847, 0f7FFFFFFF;
|
|
|
|
$L__BB0_15:
|
|
add.f32 %f747, %f59, 0f40800000;
|
|
mov.b32 %r96, %f747;
|
|
setp.lt.s32 %p34, %r96, 2139095040;
|
|
@%p34 bra $L__BB0_20;
|
|
|
|
setp.gtu.f32 %p35, %f59, 0f7F800000;
|
|
@%p35 bra $L__BB0_19;
|
|
bra.uni $L__BB0_17;
|
|
|
|
$L__BB0_19:
|
|
add.f32 %f1847, %f57, 0f40800000;
|
|
bra.uni $L__BB0_20;
|
|
|
|
$L__BB0_17:
|
|
setp.neu.f32 %p36, %f59, 0f7F800000;
|
|
@%p36 bra $L__BB0_20;
|
|
|
|
selp.f32 %f1847, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_20:
|
|
mov.f32 %f748, 0f3F800000;
|
|
sub.f32 %f749, %f748, %f1847;
|
|
setp.eq.f32 %p37, %f57, 0f3F800000;
|
|
selp.f32 %f750, 0f00000000, %f749, %p37;
|
|
cvt.sat.f32.f32 %f751, %f750;
|
|
mul.f32 %f752, %f56, %f751;
|
|
ld.global.f32 %f753, [%rd59+12];
|
|
mul.f32 %f754, %f53, %f753;
|
|
ld.global.f32 %f755, [%rd59+16];
|
|
mul.f32 %f756, %f54, %f755;
|
|
neg.f32 %f757, %f756;
|
|
sub.f32 %f758, %f757, %f754;
|
|
ld.global.f32 %f759, [%rd59+20];
|
|
mul.f32 %f760, %f55, %f759;
|
|
sub.f32 %f761, %f758, %f760;
|
|
cvt.sat.f32.f32 %f762, %f761;
|
|
mul.f32 %f70, %f752, %f762;
|
|
mul.f32 %f763, %f1812, %f54;
|
|
fma.rn.f32 %f764, %f1811, %f53, %f763;
|
|
fma.rn.f32 %f71, %f1813, %f55, %f764;
|
|
setp.leu.f32 %p38, %f70, 0f3727C5AC;
|
|
@%p38 bra $L__BB0_22;
|
|
|
|
cvt.sat.f32.f32 %f774, %f71;
|
|
mov.f32 %f780, 0f38D1B717;
|
|
max.f32 %f771, %f779, %f780;
|
|
sub.f32 %f772, %f52, %f771;
|
|
mov.f32 %f773, 0f00000000;
|
|
mov.u32 %r134, 2;
|
|
mov.u32 %r135, 1;
|
|
mov.u32 %r136, 3;
|
|
mov.u32 %r139, 1065353216;
|
|
mov.u32 %r168, 0;
|
|
// begin inline asm
|
|
call(%r98,%r99,%r100,%r101,%r102,%r103,%r104,%r105,%r106,%r107,%r108,%r109,%r110,%r111,%r112,%r113,%r114,%r115,%r116,%r117,%r118,%r119,%r120,%r121,%r122,%r123,%r124,%r125,%r126,%r127,%r128,%r129),_optix_trace_typed_32,(%r168,%rd4,%f13,%f14,%f15,%f53,%f54,%f55,%f771,%f772,%f773,%r135,%r168,%r135,%r134,%r135,%r136,%r139,%r139,%r139,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168,%r168);
|
|
// end inline asm
|
|
mov.b32 %f781, %r98;
|
|
mov.b32 %f782, %r99;
|
|
mov.b32 %f783, %r100;
|
|
ld.global.f32 %f784, [%rd59+24];
|
|
mul.f32 %f785, %f784, %f781;
|
|
ld.global.f32 %f786, [%rd59+28];
|
|
mul.f32 %f787, %f786, %f782;
|
|
ld.global.f32 %f788, [%rd59+32];
|
|
mul.f32 %f789, %f788, %f783;
|
|
mul.f32 %f790, %f70, 0f3EA2F983;
|
|
mul.f32 %f791, %f790, %f785;
|
|
mul.f32 %f792, %f790, %f787;
|
|
mul.f32 %f793, %f790, %f789;
|
|
fma.rn.f32 %f1875, %f774, %f791, %f1875;
|
|
fma.rn.f32 %f1876, %f774, %f792, %f1876;
|
|
fma.rn.f32 %f1877, %f774, %f793, %f1877;
|
|
add.f32 %f1872, %f1872, %f791;
|
|
add.f32 %f1873, %f1873, %f792;
|
|
add.f32 %f1874, %f1874, %f793;
|
|
fma.rn.f32 %f1869, %f54, %f791, %f1869;
|
|
fma.rn.f32 %f1870, %f54, %f792, %f1870;
|
|
fma.rn.f32 %f1871, %f54, %f793, %f1871;
|
|
fma.rn.f32 %f1866, %f55, %f791, %f1866;
|
|
fma.rn.f32 %f1867, %f55, %f792, %f1867;
|
|
fma.rn.f32 %f1868, %f55, %f793, %f1868;
|
|
fma.rn.f32 %f1863, %f53, %f791, %f1863;
|
|
fma.rn.f32 %f1864, %f53, %f792, %f1864;
|
|
fma.rn.f32 %f1865, %f53, %f793, %f1865;
|
|
mul.f32 %f794, %f53, %f54;
|
|
fma.rn.f32 %f1860, %f794, %f791, %f1860;
|
|
fma.rn.f32 %f1861, %f794, %f792, %f1861;
|
|
fma.rn.f32 %f1862, %f794, %f793, %f1862;
|
|
mul.f32 %f795, %f54, %f55;
|
|
fma.rn.f32 %f1857, %f795, %f791, %f1857;
|
|
fma.rn.f32 %f1858, %f795, %f792, %f1858;
|
|
fma.rn.f32 %f1859, %f795, %f793, %f1859;
|
|
fma.rn.f32 %f796, %f55, %f55, 0fBEAAAAAB;
|
|
fma.rn.f32 %f1854, %f796, %f791, %f1854;
|
|
fma.rn.f32 %f1855, %f796, %f792, %f1855;
|
|
fma.rn.f32 %f1856, %f796, %f793, %f1856;
|
|
mul.f32 %f797, %f53, %f55;
|
|
fma.rn.f32 %f1851, %f797, %f791, %f1851;
|
|
fma.rn.f32 %f1852, %f797, %f792, %f1852;
|
|
fma.rn.f32 %f1853, %f797, %f793, %f1853;
|
|
mul.f32 %f798, %f54, %f54;
|
|
mul.f32 %f799, %f53, %f53;
|
|
sub.f32 %f800, %f799, %f798;
|
|
fma.rn.f32 %f1848, %f800, %f791, %f1848;
|
|
fma.rn.f32 %f1849, %f800, %f792, %f1849;
|
|
fma.rn.f32 %f1850, %f800, %f793, %f1850;
|
|
add.f32 %f1878, %f1878, %f781;
|
|
|
|
$L__BB0_22:
|
|
add.s32 %r473, %r473, 1;
|
|
setp.lt.s32 %p40, %r473, %r76;
|
|
mov.pred %p207, %p17;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_23:
|
|
cvt.rn.f32.s32 %f801, %r473;
|
|
mov.f32 %f802, 0f3F800000;
|
|
max.f32 %f803, %f801, %f802;
|
|
rcp.rn.f32 %f804, %f803;
|
|
mul.f32 %f2033, %f1875, %f804;
|
|
mul.f32 %f2034, %f1876, %f804;
|
|
mul.f32 %f2035, %f1877, %f804;
|
|
div.rn.f32 %f2036, %f1878, %f803;
|
|
mul.f32 %f2030, %f1872, %f804;
|
|
mul.f32 %f2031, %f1873, %f804;
|
|
mul.f32 %f2032, %f1874, %f804;
|
|
mul.f32 %f2027, %f1869, %f804;
|
|
mul.f32 %f2028, %f1870, %f804;
|
|
mul.f32 %f2029, %f1871, %f804;
|
|
mul.f32 %f2024, %f1866, %f804;
|
|
mul.f32 %f2025, %f1867, %f804;
|
|
mul.f32 %f2026, %f1868, %f804;
|
|
mul.f32 %f2021, %f1863, %f804;
|
|
mul.f32 %f2022, %f1864, %f804;
|
|
mul.f32 %f2023, %f1865, %f804;
|
|
mul.f32 %f2018, %f1860, %f804;
|
|
mul.f32 %f2019, %f1861, %f804;
|
|
mul.f32 %f2020, %f1862, %f804;
|
|
mul.f32 %f2015, %f1857, %f804;
|
|
mul.f32 %f2016, %f1858, %f804;
|
|
mul.f32 %f2017, %f1859, %f804;
|
|
mul.f32 %f2012, %f1854, %f804;
|
|
mul.f32 %f2013, %f1855, %f804;
|
|
mul.f32 %f2014, %f1856, %f804;
|
|
mul.f32 %f2009, %f1851, %f804;
|
|
mul.f32 %f2010, %f1852, %f804;
|
|
mul.f32 %f2011, %f1853, %f804;
|
|
mul.f32 %f2006, %f1848, %f804;
|
|
mul.f32 %f2007, %f1849, %f804;
|
|
mul.f32 %f2008, %f1850, %f804;
|
|
not.pred %p41, %p207;
|
|
@%p41 bra $L__BB0_54;
|
|
|
|
setp.lt.s32 %p42, %r4, 1;
|
|
mov.f32 %f834, 0f00000000;
|
|
mov.f32 %f1969, %f834;
|
|
mov.f32 %f1968, %f834;
|
|
mov.f32 %f1967, %f834;
|
|
mov.f32 %f1966, %f834;
|
|
mov.f32 %f1965, %f834;
|
|
mov.f32 %f1964, %f834;
|
|
mov.f32 %f1963, %f834;
|
|
mov.f32 %f1962, %f834;
|
|
mov.f32 %f1961, %f834;
|
|
mov.f32 %f1960, %f834;
|
|
mov.f32 %f1959, %f834;
|
|
mov.f32 %f1958, %f834;
|
|
mov.f32 %f1957, %f834;
|
|
mov.f32 %f1956, %f834;
|
|
mov.f32 %f1955, %f834;
|
|
mov.f32 %f1954, %f834;
|
|
mov.f32 %f1953, %f834;
|
|
mov.f32 %f1952, %f834;
|
|
mov.f32 %f1951, %f834;
|
|
mov.f32 %f1950, %f834;
|
|
mov.f32 %f1949, %f834;
|
|
mov.f32 %f1948, %f834;
|
|
mov.f32 %f1947, %f834;
|
|
mov.f32 %f1946, %f834;
|
|
mov.f32 %f1945, %f834;
|
|
mov.f32 %f1944, %f834;
|
|
mov.f32 %f1943, %f834;
|
|
mov.f32 %f1942, %f834;
|
|
mov.f32 %f1941, %f834;
|
|
mov.f32 %f1940, %f834;
|
|
@%p42 bra $L__BB0_53;
|
|
|
|
cvt.rn.f32.s32 %f865, %r5;
|
|
rcp.rn.f32 %f196, %f865;
|
|
mul.f32 %f197, %f13, 0f3456BF95;
|
|
mul.f32 %f198, %f14, 0f3456BF95;
|
|
mul.f32 %f199, %f15, 0f3456BF95;
|
|
ld.const.u64 %rd5, [params+96];
|
|
add.u64 %rd65, %SP, 0;
|
|
add.u64 %rd6, %SPL, 0;
|
|
mov.u32 %r171, 0;
|
|
add.s64 %rd7, %rd6, 24;
|
|
mov.u64 %rd66, __cudart_i2opi_f;
|
|
abs.f32 %f922, %f198;
|
|
abs.f32 %f923, %f197;
|
|
max.f32 %f924, %f923, %f922;
|
|
abs.f32 %f925, %f199;
|
|
max.f32 %f926, %f924, %f925;
|
|
mov.u32 %r474, %r171;
|
|
|
|
$L__BB0_26:
|
|
cvt.rn.f32.s32 %f230, %r474;
|
|
mov.u32 %r476, %r171;
|
|
|
|
$L__BB0_27:
|
|
mad.lo.s32 %r173, %r477, 1664525, 1013904223;
|
|
and.b32 %r174, %r173, 16777215;
|
|
cvt.rn.f32.u32 %f866, %r174;
|
|
fma.rn.f32 %f867, %f866, 0f33800000, %f230;
|
|
mul.f32 %f868, %f196, %f867;
|
|
mad.lo.s32 %r477, %r173, 1664525, 1013904223;
|
|
and.b32 %r175, %r477, 16777215;
|
|
cvt.rn.f32.u32 %f869, %r175;
|
|
cvt.rn.f32.s32 %f870, %r476;
|
|
fma.rn.f32 %f871, %f869, 0f33800000, %f870;
|
|
mul.f32 %f872, %f196, %f871;
|
|
fma.rn.f32 %f873, %f196, %f867, %f868;
|
|
mov.f32 %f874, 0f3F800000;
|
|
sub.f32 %f261, %f874, %f873;
|
|
mul.f32 %f262, %f261, %f261;
|
|
sub.f32 %f875, %f874, %f262;
|
|
mov.f32 %f876, 0f00000000;
|
|
max.f32 %f877, %f876, %f875;
|
|
sqrt.rn.f32 %f263, %f877;
|
|
mul.f32 %f264, %f872, 0f40C90FDB;
|
|
mul.f32 %f878, %f264, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r484, %f878;
|
|
cvt.rn.f32.s32 %f879, %r484;
|
|
mov.f32 %f880, 0fBFC90FDA;
|
|
fma.rn.f32 %f881, %f879, %f880, %f264;
|
|
mov.f32 %f882, 0fB3A22168;
|
|
fma.rn.f32 %f883, %f879, %f882, %f881;
|
|
mov.f32 %f884, 0fA7C234C5;
|
|
fma.rn.f32 %f1973, %f879, %f884, %f883;
|
|
abs.f32 %f266, %f264;
|
|
setp.ltu.f32 %p43, %f266, 0f47CE4780;
|
|
mov.u32 %r481, %r484;
|
|
mov.f32 %f1970, %f1973;
|
|
@%p43 bra $L__BB0_35;
|
|
|
|
setp.eq.f32 %p44, %f266, 0f7F800000;
|
|
@%p44 bra $L__BB0_34;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_34:
|
|
mov.f32 %f887, 0f00000000;
|
|
mul.rn.f32 %f1970, %f264, %f887;
|
|
mov.u32 %r481, 0;
|
|
bra.uni $L__BB0_35;
|
|
|
|
$L__BB0_29:
|
|
mov.b32 %r18, %f264;
|
|
bfe.u32 %r177, %r18, 23, 8;
|
|
add.s32 %r19, %r177, -128;
|
|
shl.b32 %r178, %r18, 8;
|
|
or.b32 %r20, %r178, -2147483648;
|
|
shr.u32 %r21, %r19, 5;
|
|
mov.u64 %rd176, 0;
|
|
mov.u32 %r478, 0;
|
|
mov.u64 %rd174, %rd6;
|
|
mov.u64 %rd175, %rd66;
|
|
|
|
$L__BB0_30:
|
|
.pragma "nounroll";
|
|
ld.global.nc.u32 %r179, [%rd175];
|
|
mad.wide.u32 %rd69, %r179, %r20, %rd176;
|
|
shr.u64 %rd176, %rd69, 32;
|
|
st.local.u32 [%rd174], %rd69;
|
|
add.s64 %rd175, %rd175, 4;
|
|
add.s64 %rd174, %rd174, 4;
|
|
add.s32 %r478, %r478, 1;
|
|
setp.ne.s32 %p45, %r478, 6;
|
|
@%p45 bra $L__BB0_30;
|
|
|
|
st.local.u32 [%rd7], %rd176;
|
|
mov.u32 %r180, 4;
|
|
sub.s32 %r24, %r180, %r21;
|
|
mov.u32 %r181, 6;
|
|
sub.s32 %r182, %r181, %r21;
|
|
cvta.to.local.u64 %rd71, %rd65;
|
|
mul.wide.s32 %rd72, %r182, 4;
|
|
add.s64 %rd73, %rd71, %rd72;
|
|
ld.local.u32 %r479, [%rd73];
|
|
ld.local.u32 %r480, [%rd73+-4];
|
|
and.b32 %r27, %r19, 31;
|
|
setp.eq.s32 %p46, %r27, 0;
|
|
@%p46 bra $L__BB0_33;
|
|
|
|
mov.u32 %r183, 32;
|
|
sub.s32 %r184, %r183, %r27;
|
|
shr.u32 %r185, %r480, %r184;
|
|
shl.b32 %r186, %r479, %r27;
|
|
add.s32 %r479, %r185, %r186;
|
|
mul.wide.s32 %rd76, %r24, 4;
|
|
add.s64 %rd77, %rd71, %rd76;
|
|
ld.local.u32 %r187, [%rd77];
|
|
shr.u32 %r188, %r187, %r184;
|
|
shl.b32 %r189, %r480, %r27;
|
|
add.s32 %r480, %r188, %r189;
|
|
|
|
$L__BB0_33:
|
|
and.b32 %r190, %r18, -2147483648;
|
|
shr.u32 %r191, %r480, 30;
|
|
shl.b32 %r192, %r479, 2;
|
|
or.b32 %r193, %r191, %r192;
|
|
shr.u32 %r194, %r193, 31;
|
|
shr.u32 %r195, %r479, 30;
|
|
add.s32 %r196, %r194, %r195;
|
|
neg.s32 %r197, %r196;
|
|
setp.eq.s32 %p47, %r190, 0;
|
|
selp.b32 %r481, %r196, %r197, %p47;
|
|
setp.ne.s32 %p48, %r194, 0;
|
|
xor.b32 %r198, %r190, -2147483648;
|
|
selp.b32 %r199, %r198, %r190, %p48;
|
|
selp.b32 %r200, -1, 0, %p48;
|
|
xor.b32 %r201, %r193, %r200;
|
|
shl.b32 %r202, %r480, 2;
|
|
xor.b32 %r203, %r202, %r200;
|
|
cvt.u64.u32 %rd78, %r201;
|
|
cvt.u64.u32 %rd79, %r203;
|
|
bfi.b64 %rd80, %rd78, %rd79, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd80;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f885, %fd2;
|
|
setp.eq.s32 %p49, %r199, 0;
|
|
neg.f32 %f886, %f885;
|
|
selp.f32 %f1970, %f885, %f886, %p49;
|
|
|
|
$L__BB0_35:
|
|
add.s32 %r34, %r481, 1;
|
|
and.b32 %r35, %r34, 1;
|
|
setp.eq.s32 %p50, %r35, 0;
|
|
selp.f32 %f270, %f1970, 0f3F800000, %p50;
|
|
mul.rn.f32 %f271, %f1970, %f1970;
|
|
mov.f32 %f1971, 0fB94D4153;
|
|
@%p50 bra $L__BB0_37;
|
|
|
|
mov.f32 %f889, 0fBAB607ED;
|
|
mov.f32 %f890, 0f37CBAC00;
|
|
fma.rn.f32 %f1971, %f890, %f271, %f889;
|
|
|
|
$L__BB0_37:
|
|
selp.f32 %f891, 0f3C0885E4, 0f3D2AAABB, %p50;
|
|
fma.rn.f32 %f892, %f1971, %f271, %f891;
|
|
selp.f32 %f893, 0fBE2AAAA8, 0fBEFFFFFF, %p50;
|
|
fma.rn.f32 %f894, %f892, %f271, %f893;
|
|
mov.f32 %f895, 0f00000000;
|
|
fma.rn.f32 %f896, %f271, %f270, %f895;
|
|
fma.rn.f32 %f1972, %f894, %f896, %f270;
|
|
and.b32 %r205, %r34, 2;
|
|
setp.eq.s32 %p52, %r205, 0;
|
|
@%p52 bra $L__BB0_39;
|
|
|
|
mov.f32 %f898, 0fBF800000;
|
|
fma.rn.f32 %f1972, %f1972, %f898, %f895;
|
|
|
|
$L__BB0_39:
|
|
@%p43 bra $L__BB0_47;
|
|
|
|
setp.eq.f32 %p54, %f266, 0f7F800000;
|
|
@%p54 bra $L__BB0_46;
|
|
bra.uni $L__BB0_41;
|
|
|
|
$L__BB0_46:
|
|
mov.f32 %f901, 0f00000000;
|
|
mul.rn.f32 %f1973, %f264, %f901;
|
|
mov.u32 %r484, 0;
|
|
bra.uni $L__BB0_47;
|
|
|
|
$L__BB0_41:
|
|
mov.b32 %r36, %f264;
|
|
bfe.u32 %r206, %r36, 23, 8;
|
|
add.s32 %r37, %r206, -128;
|
|
shl.b32 %r207, %r36, 8;
|
|
or.b32 %r38, %r207, -2147483648;
|
|
shr.u32 %r39, %r37, 5;
|
|
mov.u64 %rd177, 0;
|
|
mov.u64 %rd178, %rd177;
|
|
|
|
$L__BB0_42:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd83, %rd177, 2;
|
|
mov.u64 %rd84, __cudart_i2opi_f;
|
|
add.s64 %rd85, %rd84, %rd83;
|
|
ld.global.nc.u32 %r208, [%rd85];
|
|
mad.wide.u32 %rd86, %r208, %r38, %rd178;
|
|
shr.u64 %rd178, %rd86, 32;
|
|
add.s64 %rd87, %rd6, %rd83;
|
|
st.local.u32 [%rd87], %rd86;
|
|
cvt.u32.u64 %r209, %rd177;
|
|
add.s32 %r210, %r209, 1;
|
|
cvt.s64.s32 %rd177, %r210;
|
|
setp.ne.s32 %p55, %r210, 6;
|
|
@%p55 bra $L__BB0_42;
|
|
|
|
st.local.u32 [%rd7], %rd178;
|
|
mov.u32 %r211, 4;
|
|
sub.s32 %r40, %r211, %r39;
|
|
mov.u32 %r212, 6;
|
|
sub.s32 %r213, %r212, %r39;
|
|
cvta.to.local.u64 %rd89, %rd65;
|
|
mul.wide.s32 %rd90, %r213, 4;
|
|
add.s64 %rd91, %rd89, %rd90;
|
|
ld.local.u32 %r482, [%rd91];
|
|
ld.local.u32 %r483, [%rd91+-4];
|
|
and.b32 %r43, %r37, 31;
|
|
setp.eq.s32 %p56, %r43, 0;
|
|
@%p56 bra $L__BB0_45;
|
|
|
|
mov.u32 %r214, 32;
|
|
sub.s32 %r215, %r214, %r43;
|
|
shr.u32 %r216, %r483, %r215;
|
|
shl.b32 %r217, %r482, %r43;
|
|
add.s32 %r482, %r216, %r217;
|
|
mul.wide.s32 %rd94, %r40, 4;
|
|
add.s64 %rd95, %rd89, %rd94;
|
|
ld.local.u32 %r218, [%rd95];
|
|
shr.u32 %r219, %r218, %r215;
|
|
shl.b32 %r220, %r483, %r43;
|
|
add.s32 %r483, %r219, %r220;
|
|
|
|
$L__BB0_45:
|
|
and.b32 %r221, %r36, -2147483648;
|
|
shr.u32 %r222, %r483, 30;
|
|
shl.b32 %r223, %r482, 2;
|
|
or.b32 %r224, %r222, %r223;
|
|
shr.u32 %r225, %r224, 31;
|
|
shr.u32 %r226, %r482, 30;
|
|
add.s32 %r227, %r225, %r226;
|
|
neg.s32 %r228, %r227;
|
|
setp.eq.s32 %p57, %r221, 0;
|
|
selp.b32 %r484, %r227, %r228, %p57;
|
|
setp.ne.s32 %p58, %r225, 0;
|
|
xor.b32 %r229, %r221, -2147483648;
|
|
selp.b32 %r230, %r229, %r221, %p58;
|
|
selp.b32 %r231, -1, 0, %p58;
|
|
xor.b32 %r232, %r224, %r231;
|
|
shl.b32 %r233, %r483, 2;
|
|
xor.b32 %r234, %r233, %r231;
|
|
cvt.u64.u32 %rd96, %r232;
|
|
cvt.u64.u32 %rd97, %r234;
|
|
bfi.b64 %rd98, %rd96, %rd97, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd98;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f899, %fd4;
|
|
setp.eq.s32 %p59, %r230, 0;
|
|
neg.f32 %f900, %f899;
|
|
selp.f32 %f1973, %f899, %f900, %p59;
|
|
|
|
$L__BB0_47:
|
|
mul.f32 %f280, %f263, %f1972;
|
|
and.b32 %r50, %r484, 1;
|
|
setp.eq.s32 %p60, %r50, 0;
|
|
selp.f32 %f281, %f1973, 0f3F800000, %p60;
|
|
mul.rn.f32 %f282, %f1973, %f1973;
|
|
mov.f32 %f1974, 0fB94D4153;
|
|
@%p60 bra $L__BB0_49;
|
|
|
|
mov.f32 %f903, 0fBAB607ED;
|
|
mov.f32 %f904, 0f37CBAC00;
|
|
fma.rn.f32 %f1974, %f904, %f282, %f903;
|
|
|
|
$L__BB0_49:
|
|
selp.f32 %f905, 0f3C0885E4, 0f3D2AAABB, %p60;
|
|
fma.rn.f32 %f906, %f1974, %f282, %f905;
|
|
selp.f32 %f907, 0fBE2AAAA8, 0fBEFFFFFF, %p60;
|
|
fma.rn.f32 %f908, %f906, %f282, %f907;
|
|
mov.f32 %f909, 0f00000000;
|
|
fma.rn.f32 %f910, %f282, %f281, %f909;
|
|
fma.rn.f32 %f1975, %f908, %f910, %f281;
|
|
and.b32 %r236, %r484, 2;
|
|
setp.eq.s32 %p62, %r236, 0;
|
|
@%p62 bra $L__BB0_51;
|
|
|
|
mov.f32 %f912, 0fBF800000;
|
|
fma.rn.f32 %f1975, %f1975, %f912, %f909;
|
|
|
|
$L__BB0_51:
|
|
mov.f32 %f927, 0f38D1B717;
|
|
max.f32 %f919, %f926, %f927;
|
|
mul.f32 %f917, %f263, %f1975;
|
|
mov.f32 %f920, 0f6C4ECB8F;
|
|
mov.u32 %r270, 1;
|
|
mov.u32 %r273, 2;
|
|
mov.u32 %r275, 4;
|
|
mov.u32 %r278, 1065353216;
|
|
mov.u32 %r279, 2139095039;
|
|
mov.u32 %r307, 0;
|
|
// begin inline asm
|
|
call(%r237,%r238,%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260,%r261,%r262,%r263,%r264,%r265,%r266,%r267,%r268),_optix_trace_typed_32,(%r307,%rd5,%f13,%f14,%f15,%f280,%f917,%f261,%f919,%f920,%f909,%r270,%r307,%r307,%r273,%r307,%r275,%r278,%r278,%r278,%r279,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307,%r307);
|
|
// end inline asm
|
|
mov.b32 %f928, %r237;
|
|
mov.b32 %f929, %r238;
|
|
mov.b32 %f930, %r239;
|
|
mov.b32 %f931, %r240;
|
|
max.f32 %f932, %f928, %f909;
|
|
max.f32 %f933, %f929, %f909;
|
|
max.f32 %f934, %f930, %f909;
|
|
setp.ltu.f32 %p63, %f931, 0f00000000;
|
|
selp.f32 %f935, %f934, 0f00000000, %p63;
|
|
selp.f32 %f936, %f933, 0f00000000, %p63;
|
|
selp.f32 %f937, %f932, 0f00000000, %p63;
|
|
add.f32 %f1945, %f1945, %f937;
|
|
add.f32 %f1944, %f1944, %f936;
|
|
add.f32 %f1943, %f1943, %f935;
|
|
fma.rn.f32 %f1948, %f917, %f937, %f1948;
|
|
fma.rn.f32 %f1947, %f917, %f936, %f1947;
|
|
fma.rn.f32 %f1946, %f917, %f935, %f1946;
|
|
fma.rn.f32 %f1951, %f261, %f937, %f1951;
|
|
fma.rn.f32 %f1950, %f261, %f936, %f1950;
|
|
fma.rn.f32 %f1949, %f261, %f935, %f1949;
|
|
fma.rn.f32 %f1954, %f280, %f937, %f1954;
|
|
fma.rn.f32 %f1953, %f280, %f936, %f1953;
|
|
fma.rn.f32 %f1952, %f280, %f935, %f1952;
|
|
mul.f32 %f938, %f280, %f917;
|
|
fma.rn.f32 %f1957, %f938, %f937, %f1957;
|
|
fma.rn.f32 %f1956, %f938, %f936, %f1956;
|
|
fma.rn.f32 %f1955, %f938, %f935, %f1955;
|
|
mul.f32 %f939, %f261, %f917;
|
|
fma.rn.f32 %f1960, %f939, %f937, %f1960;
|
|
fma.rn.f32 %f1959, %f939, %f936, %f1959;
|
|
fma.rn.f32 %f1958, %f939, %f935, %f1958;
|
|
add.f32 %f940, %f262, 0fBEAAAAAB;
|
|
fma.rn.f32 %f1963, %f940, %f937, %f1963;
|
|
fma.rn.f32 %f1962, %f940, %f936, %f1962;
|
|
fma.rn.f32 %f1961, %f940, %f935, %f1961;
|
|
mul.f32 %f941, %f261, %f280;
|
|
fma.rn.f32 %f1966, %f941, %f937, %f1966;
|
|
fma.rn.f32 %f1965, %f941, %f936, %f1965;
|
|
fma.rn.f32 %f1964, %f941, %f935, %f1964;
|
|
mul.f32 %f942, %f917, %f917;
|
|
mul.f32 %f943, %f280, %f280;
|
|
sub.f32 %f944, %f943, %f942;
|
|
fma.rn.f32 %f1969, %f944, %f937, %f1969;
|
|
fma.rn.f32 %f1968, %f944, %f936, %f1968;
|
|
fma.rn.f32 %f1967, %f944, %f935, %f1967;
|
|
mul.f32 %f945, %f1812, %f917;
|
|
fma.rn.f32 %f946, %f1811, %f280, %f945;
|
|
fma.rn.f32 %f947, %f1813, %f261, %f946;
|
|
cvt.sat.f32.f32 %f948, %f947;
|
|
fma.rn.f32 %f1942, %f937, %f948, %f1942;
|
|
fma.rn.f32 %f1941, %f936, %f948, %f1941;
|
|
fma.rn.f32 %f1940, %f935, %f948, %f1940;
|
|
add.s32 %r476, %r476, 1;
|
|
setp.lt.s32 %p64, %r476, %r5;
|
|
@%p64 bra $L__BB0_27;
|
|
|
|
add.s32 %r474, %r474, 1;
|
|
setp.lt.s32 %p65, %r474, %r5;
|
|
@%p65 bra $L__BB0_26;
|
|
|
|
$L__BB0_53:
|
|
mul.lo.s32 %r308, %r5, %r5;
|
|
cvt.rn.f32.s32 %f949, %r308;
|
|
rcp.rn.f32 %f950, %f949;
|
|
mul.f32 %f951, %f950, %f1942;
|
|
mul.f32 %f952, %f950, %f1941;
|
|
mul.f32 %f953, %f950, %f1940;
|
|
div.rn.f32 %f2036, %f834, %f949;
|
|
mul.f32 %f2030, %f950, %f1945;
|
|
mul.f32 %f2031, %f950, %f1944;
|
|
mul.f32 %f2032, %f950, %f1943;
|
|
mul.f32 %f2027, %f950, %f1948;
|
|
mul.f32 %f2028, %f950, %f1947;
|
|
mul.f32 %f2029, %f950, %f1946;
|
|
mul.f32 %f2024, %f950, %f1951;
|
|
mul.f32 %f2025, %f950, %f1950;
|
|
mul.f32 %f2026, %f950, %f1949;
|
|
mul.f32 %f2021, %f950, %f1954;
|
|
mul.f32 %f2022, %f950, %f1953;
|
|
mul.f32 %f2023, %f950, %f1952;
|
|
mul.f32 %f2018, %f950, %f1957;
|
|
mul.f32 %f2019, %f950, %f1956;
|
|
mul.f32 %f2020, %f950, %f1955;
|
|
mul.f32 %f2015, %f950, %f1960;
|
|
mul.f32 %f2016, %f950, %f1959;
|
|
mul.f32 %f2017, %f950, %f1958;
|
|
mul.f32 %f2012, %f950, %f1963;
|
|
mul.f32 %f2013, %f950, %f1962;
|
|
mul.f32 %f2014, %f950, %f1961;
|
|
mul.f32 %f2009, %f950, %f1966;
|
|
mul.f32 %f2010, %f950, %f1965;
|
|
mul.f32 %f2011, %f950, %f1964;
|
|
mul.f32 %f2006, %f950, %f1969;
|
|
mul.f32 %f2007, %f950, %f1968;
|
|
mul.f32 %f2008, %f950, %f1967;
|
|
fma.rn.f32 %f2033, %f950, %f1942, %f951;
|
|
fma.rn.f32 %f2034, %f950, %f1941, %f952;
|
|
fma.rn.f32 %f2035, %f950, %f1940, %f953;
|
|
|
|
$L__BB0_54:
|
|
ld.const.u32 %r471, [params+616];
|
|
setp.lt.s32 %p66, %r471, 0;
|
|
selp.f32 %f410, %f2033, %f2036, %p66;
|
|
ld.const.u32 %r53, [params+104];
|
|
and.b32 %r309, %r53, 8;
|
|
setp.eq.s32 %p67, %r309, 0;
|
|
@%p67 bra $L__BB0_68;
|
|
|
|
ld.const.u64 %rd100, [params+192];
|
|
cvta.to.global.u64 %rd19, %rd100;
|
|
ld.const.u32 %r310, [params+184];
|
|
mad.lo.s32 %r311, %r310, %r7, %r6;
|
|
cvt.u64.u32 %rd20, %r311;
|
|
mov.f32 %f956, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f957, %f956;
|
|
add.f32 %f958, %f957, %f957;
|
|
mov.f32 %f959, 0f3EE8BA2E;
|
|
sub.f32 %f960, %f959, %f958;
|
|
abs.f32 %f411, %f960;
|
|
abs.f32 %f412, %f410;
|
|
setp.lt.f32 %p68, %f412, 0f00800000;
|
|
mul.f32 %f961, %f412, 0f4B800000;
|
|
selp.f32 %f962, %f961, %f412, %p68;
|
|
selp.f32 %f963, 0fC3170000, 0fC2FE0000, %p68;
|
|
mov.b32 %r312, %f962;
|
|
and.b32 %r313, %r312, 8388607;
|
|
or.b32 %r314, %r313, 1065353216;
|
|
mov.b32 %f964, %r314;
|
|
shr.u32 %r315, %r312, 23;
|
|
cvt.rn.f32.u32 %f965, %r315;
|
|
add.f32 %f966, %f963, %f965;
|
|
setp.gt.f32 %p69, %f964, 0f3FB504F3;
|
|
mul.f32 %f967, %f964, 0f3F000000;
|
|
add.f32 %f968, %f966, 0f3F800000;
|
|
selp.f32 %f969, %f968, %f966, %p69;
|
|
selp.f32 %f970, %f967, %f964, %p69;
|
|
add.f32 %f971, %f970, 0fBF800000;
|
|
add.f32 %f972, %f970, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f973, %f972;
|
|
add.f32 %f974, %f971, %f971;
|
|
mul.f32 %f975, %f974, %f973;
|
|
mul.f32 %f976, %f975, %f975;
|
|
mov.f32 %f977, 0f3C4CAF63;
|
|
mov.f32 %f978, 0f3B18F0FE;
|
|
fma.rn.f32 %f979, %f978, %f976, %f977;
|
|
mov.f32 %f980, 0f3DAAAABD;
|
|
fma.rn.f32 %f981, %f979, %f976, %f980;
|
|
mul.rn.f32 %f982, %f981, %f976;
|
|
mul.rn.f32 %f983, %f982, %f975;
|
|
sub.f32 %f984, %f971, %f975;
|
|
add.f32 %f985, %f984, %f984;
|
|
neg.f32 %f986, %f975;
|
|
fma.rn.f32 %f987, %f986, %f971, %f985;
|
|
mul.rn.f32 %f988, %f973, %f987;
|
|
add.f32 %f989, %f983, %f975;
|
|
sub.f32 %f990, %f975, %f989;
|
|
add.f32 %f991, %f983, %f990;
|
|
add.f32 %f992, %f988, %f991;
|
|
add.f32 %f993, %f989, %f992;
|
|
sub.f32 %f994, %f989, %f993;
|
|
add.f32 %f995, %f992, %f994;
|
|
mov.f32 %f996, 0f3F317200;
|
|
mul.rn.f32 %f997, %f969, %f996;
|
|
mov.f32 %f998, 0f35BFBE8E;
|
|
mul.rn.f32 %f999, %f969, %f998;
|
|
add.f32 %f1000, %f997, %f993;
|
|
sub.f32 %f1001, %f997, %f1000;
|
|
add.f32 %f1002, %f993, %f1001;
|
|
add.f32 %f1003, %f995, %f1002;
|
|
add.f32 %f1004, %f999, %f1003;
|
|
add.f32 %f1005, %f1000, %f1004;
|
|
sub.f32 %f1006, %f1000, %f1005;
|
|
add.f32 %f1007, %f1004, %f1006;
|
|
mul.rn.f32 %f1008, %f959, %f1005;
|
|
neg.f32 %f1009, %f1008;
|
|
fma.rn.f32 %f1010, %f959, %f1005, %f1009;
|
|
fma.rn.f32 %f1011, %f959, %f1007, %f1010;
|
|
mov.f32 %f1012, 0f00000000;
|
|
fma.rn.f32 %f1013, %f1012, %f1005, %f1011;
|
|
add.rn.f32 %f1014, %f1008, %f1013;
|
|
neg.f32 %f1015, %f1014;
|
|
add.rn.f32 %f1016, %f1008, %f1015;
|
|
add.rn.f32 %f1017, %f1016, %f1013;
|
|
mov.b32 %r316, %f1014;
|
|
setp.eq.s32 %p70, %r316, 1118925336;
|
|
add.s32 %r317, %r316, -1;
|
|
mov.b32 %f1018, %r317;
|
|
add.f32 %f1019, %f1017, 0f37000000;
|
|
selp.f32 %f413, %f1019, %f1017, %p70;
|
|
selp.f32 %f1020, %f1018, %f1014, %p70;
|
|
mov.f32 %f1021, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1022, %f1020, %f1021;
|
|
cvt.rzi.f32.f32 %f1023, %f1022;
|
|
abs.f32 %f1024, %f1023;
|
|
setp.gt.f32 %p71, %f1024, 0f42FC0000;
|
|
mov.b32 %r318, %f1023;
|
|
and.b32 %r319, %r318, -2147483648;
|
|
or.b32 %r320, %r319, 1123811328;
|
|
mov.b32 %f1025, %r320;
|
|
selp.f32 %f1026, %f1025, %f1023, %p71;
|
|
mov.f32 %f1027, 0fBF317218;
|
|
fma.rn.f32 %f1028, %f1026, %f1027, %f1020;
|
|
mov.f32 %f1029, 0f3102E308;
|
|
fma.rn.f32 %f1030, %f1026, %f1029, %f1028;
|
|
mul.f32 %f1031, %f1030, 0f3FB8AA3B;
|
|
add.f32 %f1032, %f1026, 0f4B40007F;
|
|
mov.b32 %r321, %f1032;
|
|
shl.b32 %r322, %r321, 23;
|
|
mov.b32 %f1033, %r322;
|
|
ex2.approx.ftz.f32 %f1034, %f1031;
|
|
mul.f32 %f414, %f1034, %f1033;
|
|
setp.eq.f32 %p72, %f414, 0f7F800000;
|
|
mov.f32 %f2037, 0f7F800000;
|
|
@%p72 bra $L__BB0_57;
|
|
|
|
fma.rn.f32 %f2037, %f414, %f413, %f414;
|
|
|
|
$L__BB0_57:
|
|
setp.lt.f32 %p73, %f410, 0f00000000;
|
|
setp.eq.f32 %p74, %f411, 0f3F800000;
|
|
and.pred %p3, %p73, %p74;
|
|
setp.eq.f32 %p75, %f410, 0f00000000;
|
|
@%p75 bra $L__BB0_61;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_61:
|
|
add.f32 %f1039, %f410, %f410;
|
|
selp.f32 %f2039, %f1039, 0f00000000, %p74;
|
|
bra.uni $L__BB0_62;
|
|
|
|
$L__BB0_180:
|
|
mov.f32 %f1723, 0f00000000;
|
|
mov.u32 %r486, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs188, %f1723;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs187, %f1723;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs186, %f1723;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs189, 0;
|
|
st.global.v4.u16 [%rd33], {%rs186, %rs187, %rs188, %rs189};
|
|
|
|
$L__BB0_181:
|
|
ld.const.u64 %rd147, [params+256];
|
|
cvta.to.global.u64 %rd148, %rd147;
|
|
ld.const.u32 %r453, [params+248];
|
|
mad.lo.s32 %r454, %r453, %r7, %r6;
|
|
mul.wide.u32 %rd149, %r454, 8;
|
|
add.s64 %rd34, %rd148, %rd149;
|
|
setp.eq.s32 %p198, %r486, 0;
|
|
@%p198 bra $L__BB0_183;
|
|
|
|
ld.global.v4.u16 {%rs196, %rs197, %rs198, %rs199}, [%rd34];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1724, %rs196;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1725, %rs197;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1726, %rs198;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1727, %f1724, 0f00000000;
|
|
add.f32 %f1728, %f1725, 0f00000000;
|
|
add.f32 %f1729, %f1726, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs195, %f1729;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs194, %f1728;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs193, %f1727;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs200, 0;
|
|
st.global.v4.u16 [%rd34], {%rs193, %rs194, %rs195, %rs200};
|
|
bra.uni $L__BB0_184;
|
|
|
|
$L__BB0_183:
|
|
mov.f32 %f1732, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs203, %f1732;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs202, %f1732;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs201, %f1732;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs204, 0;
|
|
st.global.v4.u16 [%rd34], {%rs201, %rs202, %rs203, %rs204};
|
|
|
|
$L__BB0_184:
|
|
ld.const.u64 %rd150, [params+272];
|
|
cvta.to.global.u64 %rd151, %rd150;
|
|
ld.const.u32 %r455, [params+264];
|
|
mad.lo.s32 %r456, %r455, %r7, %r6;
|
|
mul.wide.u32 %rd152, %r456, 8;
|
|
add.s64 %rd35, %rd151, %rd152;
|
|
@%p198 bra $L__BB0_186;
|
|
|
|
ld.global.v4.u16 {%rs211, %rs212, %rs213, %rs214}, [%rd35];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1733, %rs211;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1734, %rs212;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1735, %rs213;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1736, %f1733, 0f00000000;
|
|
add.f32 %f1737, %f1734, 0f00000000;
|
|
add.f32 %f1738, %f1735, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs210, %f1738;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs209, %f1737;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs208, %f1736;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs215, 0;
|
|
st.global.v4.u16 [%rd35], {%rs208, %rs209, %rs210, %rs215};
|
|
bra.uni $L__BB0_187;
|
|
|
|
$L__BB0_186:
|
|
mov.f32 %f1741, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs218, %f1741;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs217, %f1741;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs216, %f1741;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs219, 0;
|
|
st.global.v4.u16 [%rd35], {%rs216, %rs217, %rs218, %rs219};
|
|
|
|
$L__BB0_187:
|
|
ld.const.u64 %rd153, [params+288];
|
|
cvta.to.global.u64 %rd154, %rd153;
|
|
ld.const.u32 %r457, [params+280];
|
|
mad.lo.s32 %r458, %r457, %r7, %r6;
|
|
mul.wide.u32 %rd155, %r458, 8;
|
|
add.s64 %rd36, %rd154, %rd155;
|
|
@%p198 bra $L__BB0_189;
|
|
|
|
ld.global.v4.u16 {%rs226, %rs227, %rs228, %rs229}, [%rd36];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1742, %rs226;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1743, %rs227;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1744, %rs228;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1745, %f1742, 0f00000000;
|
|
add.f32 %f1746, %f1743, 0f00000000;
|
|
add.f32 %f1747, %f1744, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs225, %f1747;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs224, %f1746;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs223, %f1745;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs230, 0;
|
|
st.global.v4.u16 [%rd36], {%rs223, %rs224, %rs225, %rs230};
|
|
bra.uni $L__BB0_190;
|
|
|
|
$L__BB0_189:
|
|
mov.f32 %f1750, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs233, %f1750;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs232, %f1750;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs231, %f1750;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs234, 0;
|
|
st.global.v4.u16 [%rd36], {%rs231, %rs232, %rs233, %rs234};
|
|
|
|
$L__BB0_190:
|
|
ld.const.u64 %rd156, [params+304];
|
|
cvta.to.global.u64 %rd157, %rd156;
|
|
ld.const.u32 %r459, [params+296];
|
|
mad.lo.s32 %r460, %r459, %r7, %r6;
|
|
mul.wide.u32 %rd158, %r460, 8;
|
|
add.s64 %rd37, %rd157, %rd158;
|
|
@%p198 bra $L__BB0_192;
|
|
|
|
ld.global.v4.u16 {%rs241, %rs242, %rs243, %rs244}, [%rd37];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1751, %rs241;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1752, %rs242;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1753, %rs243;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1754, %f1751, 0f00000000;
|
|
add.f32 %f1755, %f1752, 0f00000000;
|
|
add.f32 %f1756, %f1753, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs240, %f1756;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs239, %f1755;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs238, %f1754;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs245, 0;
|
|
st.global.v4.u16 [%rd37], {%rs238, %rs239, %rs240, %rs245};
|
|
bra.uni $L__BB0_193;
|
|
|
|
$L__BB0_192:
|
|
mov.f32 %f1759, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs248, %f1759;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs247, %f1759;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs246, %f1759;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs249, 0;
|
|
st.global.v4.u16 [%rd37], {%rs246, %rs247, %rs248, %rs249};
|
|
|
|
$L__BB0_193:
|
|
ld.const.u64 %rd159, [params+320];
|
|
cvta.to.global.u64 %rd160, %rd159;
|
|
ld.const.u32 %r461, [params+312];
|
|
mad.lo.s32 %r462, %r461, %r7, %r6;
|
|
mul.wide.u32 %rd161, %r462, 8;
|
|
add.s64 %rd38, %rd160, %rd161;
|
|
@%p198 bra $L__BB0_195;
|
|
|
|
ld.global.v4.u16 {%rs256, %rs257, %rs258, %rs259}, [%rd38];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1760, %rs256;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1761, %rs257;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1762, %rs258;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1763, %f1760, 0f00000000;
|
|
add.f32 %f1764, %f1761, 0f00000000;
|
|
add.f32 %f1765, %f1762, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs255, %f1765;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs254, %f1764;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs253, %f1763;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs260, 0;
|
|
st.global.v4.u16 [%rd38], {%rs253, %rs254, %rs255, %rs260};
|
|
bra.uni $L__BB0_196;
|
|
|
|
$L__BB0_195:
|
|
mov.f32 %f1768, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs263, %f1768;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs262, %f1768;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs261, %f1768;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs264, 0;
|
|
st.global.v4.u16 [%rd38], {%rs261, %rs262, %rs263, %rs264};
|
|
|
|
$L__BB0_196:
|
|
ld.const.u64 %rd162, [params+336];
|
|
cvta.to.global.u64 %rd163, %rd162;
|
|
ld.const.u32 %r463, [params+328];
|
|
mad.lo.s32 %r464, %r463, %r7, %r6;
|
|
mul.wide.u32 %rd164, %r464, 8;
|
|
add.s64 %rd39, %rd163, %rd164;
|
|
@%p198 bra $L__BB0_198;
|
|
|
|
ld.global.v4.u16 {%rs271, %rs272, %rs273, %rs274}, [%rd39];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1769, %rs271;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1770, %rs272;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1771, %rs273;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1772, %f1769, 0f00000000;
|
|
add.f32 %f1773, %f1770, 0f00000000;
|
|
add.f32 %f1774, %f1771, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs270, %f1774;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs269, %f1773;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs268, %f1772;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs275, 0;
|
|
st.global.v4.u16 [%rd39], {%rs268, %rs269, %rs270, %rs275};
|
|
bra.uni $L__BB0_199;
|
|
|
|
$L__BB0_198:
|
|
mov.f32 %f1777, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs278, %f1777;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs277, %f1777;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs276, %f1777;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs279, 0;
|
|
st.global.v4.u16 [%rd39], {%rs276, %rs277, %rs278, %rs279};
|
|
|
|
$L__BB0_199:
|
|
ld.const.u64 %rd165, [params+352];
|
|
cvta.to.global.u64 %rd166, %rd165;
|
|
ld.const.u32 %r465, [params+344];
|
|
mad.lo.s32 %r466, %r465, %r7, %r6;
|
|
mul.wide.u32 %rd167, %r466, 8;
|
|
add.s64 %rd40, %rd166, %rd167;
|
|
@%p198 bra $L__BB0_201;
|
|
|
|
ld.global.v4.u16 {%rs286, %rs287, %rs288, %rs289}, [%rd40];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1778, %rs286;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1779, %rs287;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1780, %rs288;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1781, %f1778, 0f00000000;
|
|
add.f32 %f1782, %f1779, 0f00000000;
|
|
add.f32 %f1783, %f1780, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs285, %f1783;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs284, %f1782;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs283, %f1781;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs290, 0;
|
|
st.global.v4.u16 [%rd40], {%rs283, %rs284, %rs285, %rs290};
|
|
bra.uni $L__BB0_202;
|
|
|
|
$L__BB0_201:
|
|
mov.f32 %f1786, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs293, %f1786;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs292, %f1786;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs291, %f1786;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs294, 0;
|
|
st.global.v4.u16 [%rd40], {%rs291, %rs292, %rs293, %rs294};
|
|
|
|
$L__BB0_202:
|
|
ld.const.u64 %rd168, [params+368];
|
|
cvta.to.global.u64 %rd169, %rd168;
|
|
ld.const.u32 %r467, [params+360];
|
|
mad.lo.s32 %r468, %r467, %r7, %r6;
|
|
mul.wide.u32 %rd170, %r468, 8;
|
|
add.s64 %rd41, %rd169, %rd170;
|
|
@%p198 bra $L__BB0_204;
|
|
|
|
ld.global.v4.u16 {%rs301, %rs302, %rs303, %rs304}, [%rd41];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1787, %rs301;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1788, %rs302;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1789, %rs303;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1790, %f1787, 0f00000000;
|
|
add.f32 %f1791, %f1788, 0f00000000;
|
|
add.f32 %f1792, %f1789, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs300, %f1792;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs299, %f1791;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs298, %f1790;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs305, 0;
|
|
st.global.v4.u16 [%rd41], {%rs298, %rs299, %rs300, %rs305};
|
|
bra.uni $L__BB0_205;
|
|
|
|
$L__BB0_204:
|
|
mov.f32 %f1795, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs308, %f1795;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs307, %f1795;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs306, %f1795;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs309, 0;
|
|
st.global.v4.u16 [%rd41], {%rs306, %rs307, %rs308, %rs309};
|
|
|
|
$L__BB0_205:
|
|
ld.const.u64 %rd171, [params+384];
|
|
cvta.to.global.u64 %rd172, %rd171;
|
|
ld.const.u32 %r469, [params+376];
|
|
mad.lo.s32 %r470, %r469, %r7, %r6;
|
|
mul.wide.u32 %rd173, %r470, 8;
|
|
add.s64 %rd42, %rd172, %rd173;
|
|
@%p198 bra $L__BB0_207;
|
|
|
|
ld.global.v4.u16 {%rs316, %rs317, %rs318, %rs319}, [%rd42];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1796, %rs316;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1797, %rs317;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1798, %rs318;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1799, %f1796, 0f00000000;
|
|
add.f32 %f1800, %f1797, 0f00000000;
|
|
add.f32 %f1801, %f1798, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs315, %f1801;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs314, %f1800;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs313, %f1799;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs320, 0;
|
|
st.global.v4.u16 [%rd42], {%rs313, %rs314, %rs315, %rs320};
|
|
bra.uni $L__BB0_208;
|
|
|
|
$L__BB0_207:
|
|
mov.f32 %f1804, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs323, %f1804;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs322, %f1804;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs321, %f1804;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs324, 0;
|
|
st.global.v4.u16 [%rd42], {%rs321, %rs322, %rs323, %rs324};
|
|
bra.uni $L__BB0_208;
|
|
|
|
$L__BB0_58:
|
|
mov.b32 %r323, %f2037;
|
|
xor.b32 %r324, %r323, -2147483648;
|
|
mov.b32 %f1035, %r324;
|
|
selp.f32 %f2039, %f1035, %f2037, %p3;
|
|
setp.geu.f32 %p76, %f410, 0f00000000;
|
|
@%p76 bra $L__BB0_62;
|
|
|
|
mov.f32 %f1036, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f1037, %f1036;
|
|
setp.eq.f32 %p77, %f1037, 0f3EE8BA2E;
|
|
@%p77 bra $L__BB0_62;
|
|
|
|
mov.f32 %f2039, 0f7FFFFFFF;
|
|
|
|
$L__BB0_62:
|
|
add.f32 %f1040, %f412, 0f3EE8BA2E;
|
|
mov.b32 %r325, %f1040;
|
|
setp.lt.s32 %p79, %r325, 2139095040;
|
|
@%p79 bra $L__BB0_67;
|
|
|
|
setp.gtu.f32 %p80, %f412, 0f7F800000;
|
|
@%p80 bra $L__BB0_66;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_66:
|
|
add.f32 %f2039, %f410, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_67;
|
|
|
|
$L__BB0_64:
|
|
setp.neu.f32 %p81, %f412, 0f7F800000;
|
|
@%p81 bra $L__BB0_67;
|
|
|
|
selp.f32 %f2039, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_67:
|
|
mul.f32 %f1041, %f2039, 0f437F0000;
|
|
setp.eq.f32 %p82, %f410, 0f3F800000;
|
|
selp.f32 %f1042, 0f437F0000, %f1041, %p82;
|
|
cvt.rzi.u32.f32 %r326, %f1042;
|
|
shl.b64 %rd101, %rd20, 1;
|
|
add.s64 %rd102, %rd19, %rd101;
|
|
cvt.u16.u32 %rs16, %r326;
|
|
mov.u16 %rs17, 255;
|
|
st.global.v2.u8 [%rd102], {%rs16, %rs17};
|
|
|
|
$L__BB0_68:
|
|
ld.const.v2.f32 {%f1043, %f1044}, [params+648];
|
|
mul.f32 %f425, %f2033, %f1043;
|
|
mul.f32 %f426, %f2034, %f1044;
|
|
ld.const.f32 %f427, [params+656];
|
|
mul.f32 %f428, %f2035, %f427;
|
|
and.b32 %r327, %r53, 1;
|
|
setp.eq.b32 %p83, %r327, 1;
|
|
mov.pred %p84, 0;
|
|
xor.pred %p85, %p83, %p84;
|
|
not.pred %p86, %p85;
|
|
@%p86 bra $L__BB0_142;
|
|
|
|
mov.f32 %f1046, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1047, %f1046;
|
|
add.f32 %f1048, %f1047, %f1047;
|
|
mov.f32 %f1049, 0f3EE66666;
|
|
sub.f32 %f1050, %f1049, %f1048;
|
|
abs.f32 %f429, %f1050;
|
|
abs.f32 %f430, %f425;
|
|
setp.lt.f32 %p87, %f430, 0f00800000;
|
|
mul.f32 %f1051, %f430, 0f4B800000;
|
|
selp.f32 %f1052, %f1051, %f430, %p87;
|
|
selp.f32 %f1053, 0fC3170000, 0fC2FE0000, %p87;
|
|
mov.b32 %r328, %f1052;
|
|
and.b32 %r329, %r328, 8388607;
|
|
or.b32 %r330, %r329, 1065353216;
|
|
mov.b32 %f1054, %r330;
|
|
shr.u32 %r331, %r328, 23;
|
|
cvt.rn.f32.u32 %f1055, %r331;
|
|
add.f32 %f1056, %f1053, %f1055;
|
|
setp.gt.f32 %p88, %f1054, 0f3FB504F3;
|
|
mul.f32 %f1057, %f1054, 0f3F000000;
|
|
add.f32 %f1058, %f1056, 0f3F800000;
|
|
selp.f32 %f1059, %f1058, %f1056, %p88;
|
|
selp.f32 %f1060, %f1057, %f1054, %p88;
|
|
add.f32 %f1061, %f1060, 0fBF800000;
|
|
add.f32 %f1062, %f1060, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1063, %f1062;
|
|
add.f32 %f1064, %f1061, %f1061;
|
|
mul.f32 %f1065, %f1064, %f1063;
|
|
mul.f32 %f1066, %f1065, %f1065;
|
|
mov.f32 %f1067, 0f3C4CAF63;
|
|
mov.f32 %f1068, 0f3B18F0FE;
|
|
fma.rn.f32 %f1069, %f1068, %f1066, %f1067;
|
|
mov.f32 %f1070, 0f3DAAAABD;
|
|
fma.rn.f32 %f1071, %f1069, %f1066, %f1070;
|
|
mul.rn.f32 %f1072, %f1071, %f1066;
|
|
mul.rn.f32 %f1073, %f1072, %f1065;
|
|
sub.f32 %f1074, %f1061, %f1065;
|
|
add.f32 %f1075, %f1074, %f1074;
|
|
neg.f32 %f1076, %f1065;
|
|
fma.rn.f32 %f1077, %f1076, %f1061, %f1075;
|
|
mul.rn.f32 %f1078, %f1063, %f1077;
|
|
add.f32 %f1079, %f1073, %f1065;
|
|
sub.f32 %f1080, %f1065, %f1079;
|
|
add.f32 %f1081, %f1073, %f1080;
|
|
add.f32 %f1082, %f1078, %f1081;
|
|
add.f32 %f1083, %f1079, %f1082;
|
|
sub.f32 %f1084, %f1079, %f1083;
|
|
add.f32 %f1085, %f1082, %f1084;
|
|
mov.f32 %f1086, 0f3F317200;
|
|
mul.rn.f32 %f1087, %f1059, %f1086;
|
|
mov.f32 %f1088, 0f35BFBE8E;
|
|
mul.rn.f32 %f1089, %f1059, %f1088;
|
|
add.f32 %f1090, %f1087, %f1083;
|
|
sub.f32 %f1091, %f1087, %f1090;
|
|
add.f32 %f1092, %f1083, %f1091;
|
|
add.f32 %f1093, %f1085, %f1092;
|
|
add.f32 %f1094, %f1089, %f1093;
|
|
add.f32 %f1095, %f1090, %f1094;
|
|
sub.f32 %f1096, %f1090, %f1095;
|
|
add.f32 %f1097, %f1094, %f1096;
|
|
mul.rn.f32 %f1098, %f1049, %f1095;
|
|
neg.f32 %f1099, %f1098;
|
|
fma.rn.f32 %f1100, %f1049, %f1095, %f1099;
|
|
fma.rn.f32 %f1101, %f1049, %f1097, %f1100;
|
|
mov.f32 %f1102, 0f00000000;
|
|
fma.rn.f32 %f1103, %f1102, %f1095, %f1101;
|
|
add.rn.f32 %f1104, %f1098, %f1103;
|
|
neg.f32 %f1105, %f1104;
|
|
add.rn.f32 %f1106, %f1098, %f1105;
|
|
add.rn.f32 %f1107, %f1106, %f1103;
|
|
mov.b32 %r332, %f1104;
|
|
setp.eq.s32 %p89, %r332, 1118925336;
|
|
add.s32 %r333, %r332, -1;
|
|
mov.b32 %f1108, %r333;
|
|
add.f32 %f1109, %f1107, 0f37000000;
|
|
selp.f32 %f431, %f1109, %f1107, %p89;
|
|
selp.f32 %f1110, %f1108, %f1104, %p89;
|
|
mov.f32 %f1111, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1112, %f1110, %f1111;
|
|
cvt.rzi.f32.f32 %f1113, %f1112;
|
|
abs.f32 %f1114, %f1113;
|
|
setp.gt.f32 %p90, %f1114, 0f42FC0000;
|
|
mov.b32 %r334, %f1113;
|
|
and.b32 %r335, %r334, -2147483648;
|
|
or.b32 %r336, %r335, 1123811328;
|
|
mov.b32 %f1115, %r336;
|
|
selp.f32 %f1116, %f1115, %f1113, %p90;
|
|
mov.f32 %f1117, 0fBF317218;
|
|
fma.rn.f32 %f1118, %f1116, %f1117, %f1110;
|
|
mov.f32 %f1119, 0f3102E308;
|
|
fma.rn.f32 %f1120, %f1116, %f1119, %f1118;
|
|
mul.f32 %f1121, %f1120, 0f3FB8AA3B;
|
|
add.f32 %f1122, %f1116, 0f4B40007F;
|
|
mov.b32 %r337, %f1122;
|
|
shl.b32 %r338, %r337, 23;
|
|
mov.b32 %f1123, %r338;
|
|
ex2.approx.ftz.f32 %f1124, %f1121;
|
|
mul.f32 %f432, %f1124, %f1123;
|
|
setp.eq.f32 %p91, %f432, 0f7F800000;
|
|
mov.f32 %f2040, 0f7F800000;
|
|
@%p91 bra $L__BB0_71;
|
|
|
|
fma.rn.f32 %f2040, %f432, %f431, %f432;
|
|
|
|
$L__BB0_71:
|
|
setp.lt.f32 %p92, %f425, 0f00000000;
|
|
setp.eq.f32 %p93, %f429, 0f3F800000;
|
|
and.pred %p4, %p92, %p93;
|
|
setp.eq.f32 %p94, %f425, 0f00000000;
|
|
@%p94 bra $L__BB0_75;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_75:
|
|
add.f32 %f1129, %f425, %f425;
|
|
selp.f32 %f2042, %f1129, 0f00000000, %p93;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_72:
|
|
mov.b32 %r339, %f2040;
|
|
xor.b32 %r340, %r339, -2147483648;
|
|
mov.b32 %f1125, %r340;
|
|
selp.f32 %f2042, %f1125, %f2040, %p4;
|
|
setp.geu.f32 %p95, %f425, 0f00000000;
|
|
@%p95 bra $L__BB0_76;
|
|
|
|
mov.f32 %f1126, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1127, %f1126;
|
|
setp.eq.f32 %p96, %f1127, 0f3EE66666;
|
|
@%p96 bra $L__BB0_76;
|
|
|
|
mov.f32 %f2042, 0f7FFFFFFF;
|
|
|
|
$L__BB0_76:
|
|
add.f32 %f1130, %f430, 0f3EE66666;
|
|
mov.b32 %r341, %f1130;
|
|
setp.lt.s32 %p98, %r341, 2139095040;
|
|
@%p98 bra $L__BB0_81;
|
|
|
|
setp.gtu.f32 %p99, %f430, 0f7F800000;
|
|
@%p99 bra $L__BB0_80;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f2042, %f425, 0f3EE66666;
|
|
bra.uni $L__BB0_81;
|
|
|
|
$L__BB0_78:
|
|
setp.neu.f32 %p100, %f430, 0f7F800000;
|
|
@%p100 bra $L__BB0_81;
|
|
|
|
selp.f32 %f2042, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_81:
|
|
setp.eq.f32 %p101, %f425, 0f3F800000;
|
|
selp.f32 %f441, 0f3F800000, %f2042, %p101;
|
|
abs.f32 %f442, %f426;
|
|
setp.lt.f32 %p102, %f442, 0f00800000;
|
|
mul.f32 %f1132, %f442, 0f4B800000;
|
|
selp.f32 %f1133, %f1132, %f442, %p102;
|
|
selp.f32 %f1134, 0fC3170000, 0fC2FE0000, %p102;
|
|
mov.b32 %r342, %f1133;
|
|
and.b32 %r343, %r342, 8388607;
|
|
or.b32 %r344, %r343, 1065353216;
|
|
mov.b32 %f1135, %r344;
|
|
shr.u32 %r345, %r342, 23;
|
|
cvt.rn.f32.u32 %f1136, %r345;
|
|
add.f32 %f1137, %f1134, %f1136;
|
|
setp.gt.f32 %p103, %f1135, 0f3FB504F3;
|
|
mul.f32 %f1138, %f1135, 0f3F000000;
|
|
add.f32 %f1139, %f1137, 0f3F800000;
|
|
selp.f32 %f1140, %f1139, %f1137, %p103;
|
|
selp.f32 %f1141, %f1138, %f1135, %p103;
|
|
add.f32 %f1142, %f1141, 0fBF800000;
|
|
add.f32 %f1143, %f1141, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1144, %f1143;
|
|
add.f32 %f1145, %f1142, %f1142;
|
|
mul.f32 %f1146, %f1145, %f1144;
|
|
mul.f32 %f1147, %f1146, %f1146;
|
|
mov.f32 %f1148, 0f3C4CAF63;
|
|
mov.f32 %f1149, 0f3B18F0FE;
|
|
fma.rn.f32 %f1150, %f1149, %f1147, %f1148;
|
|
mov.f32 %f1151, 0f3DAAAABD;
|
|
fma.rn.f32 %f1152, %f1150, %f1147, %f1151;
|
|
mul.rn.f32 %f1153, %f1152, %f1147;
|
|
mul.rn.f32 %f1154, %f1153, %f1146;
|
|
sub.f32 %f1155, %f1142, %f1146;
|
|
add.f32 %f1156, %f1155, %f1155;
|
|
neg.f32 %f1157, %f1146;
|
|
fma.rn.f32 %f1158, %f1157, %f1142, %f1156;
|
|
mul.rn.f32 %f1159, %f1144, %f1158;
|
|
add.f32 %f1160, %f1154, %f1146;
|
|
sub.f32 %f1161, %f1146, %f1160;
|
|
add.f32 %f1162, %f1154, %f1161;
|
|
add.f32 %f1163, %f1159, %f1162;
|
|
add.f32 %f1164, %f1160, %f1163;
|
|
sub.f32 %f1165, %f1160, %f1164;
|
|
add.f32 %f1166, %f1163, %f1165;
|
|
mov.f32 %f1167, 0f3F317200;
|
|
mul.rn.f32 %f1168, %f1140, %f1167;
|
|
mov.f32 %f1169, 0f35BFBE8E;
|
|
mul.rn.f32 %f1170, %f1140, %f1169;
|
|
add.f32 %f1171, %f1168, %f1164;
|
|
sub.f32 %f1172, %f1168, %f1171;
|
|
add.f32 %f1173, %f1164, %f1172;
|
|
add.f32 %f1174, %f1166, %f1173;
|
|
add.f32 %f1175, %f1170, %f1174;
|
|
add.f32 %f1176, %f1171, %f1175;
|
|
sub.f32 %f1177, %f1171, %f1176;
|
|
add.f32 %f1178, %f1175, %f1177;
|
|
mov.f32 %f1179, 0f3EE66666;
|
|
mul.rn.f32 %f1180, %f1179, %f1176;
|
|
neg.f32 %f1181, %f1180;
|
|
fma.rn.f32 %f1182, %f1179, %f1176, %f1181;
|
|
fma.rn.f32 %f1183, %f1179, %f1178, %f1182;
|
|
mov.f32 %f1184, 0f00000000;
|
|
fma.rn.f32 %f1185, %f1184, %f1176, %f1183;
|
|
add.rn.f32 %f1186, %f1180, %f1185;
|
|
neg.f32 %f1187, %f1186;
|
|
add.rn.f32 %f1188, %f1180, %f1187;
|
|
add.rn.f32 %f1189, %f1188, %f1185;
|
|
mov.b32 %r346, %f1186;
|
|
setp.eq.s32 %p104, %r346, 1118925336;
|
|
add.s32 %r347, %r346, -1;
|
|
mov.b32 %f1190, %r347;
|
|
add.f32 %f1191, %f1189, 0f37000000;
|
|
selp.f32 %f443, %f1191, %f1189, %p104;
|
|
selp.f32 %f1192, %f1190, %f1186, %p104;
|
|
mov.f32 %f1193, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1194, %f1192, %f1193;
|
|
cvt.rzi.f32.f32 %f1195, %f1194;
|
|
abs.f32 %f1196, %f1195;
|
|
setp.gt.f32 %p105, %f1196, 0f42FC0000;
|
|
mov.b32 %r348, %f1195;
|
|
and.b32 %r349, %r348, -2147483648;
|
|
or.b32 %r350, %r349, 1123811328;
|
|
mov.b32 %f1197, %r350;
|
|
selp.f32 %f1198, %f1197, %f1195, %p105;
|
|
mov.f32 %f1199, 0fBF317218;
|
|
fma.rn.f32 %f1200, %f1198, %f1199, %f1192;
|
|
mov.f32 %f1201, 0f3102E308;
|
|
fma.rn.f32 %f1202, %f1198, %f1201, %f1200;
|
|
mul.f32 %f1203, %f1202, 0f3FB8AA3B;
|
|
add.f32 %f1204, %f1198, 0f4B40007F;
|
|
mov.b32 %r351, %f1204;
|
|
shl.b32 %r352, %r351, 23;
|
|
mov.b32 %f1205, %r352;
|
|
ex2.approx.ftz.f32 %f1206, %f1203;
|
|
mul.f32 %f444, %f1206, %f1205;
|
|
setp.eq.f32 %p106, %f444, 0f7F800000;
|
|
mov.f32 %f2043, 0f7F800000;
|
|
@%p106 bra $L__BB0_83;
|
|
|
|
fma.rn.f32 %f2043, %f444, %f443, %f444;
|
|
|
|
$L__BB0_83:
|
|
setp.lt.f32 %p107, %f426, 0f00000000;
|
|
and.pred %p5, %p107, %p93;
|
|
setp.eq.f32 %p109, %f426, 0f00000000;
|
|
@%p109 bra $L__BB0_87;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_87:
|
|
add.f32 %f1211, %f426, %f426;
|
|
selp.f32 %f2045, %f1211, 0f00000000, %p93;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_84:
|
|
mov.b32 %r353, %f2043;
|
|
xor.b32 %r354, %r353, -2147483648;
|
|
mov.b32 %f1207, %r354;
|
|
selp.f32 %f2045, %f1207, %f2043, %p5;
|
|
setp.geu.f32 %p110, %f426, 0f00000000;
|
|
@%p110 bra $L__BB0_88;
|
|
|
|
mov.f32 %f1208, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1209, %f1208;
|
|
setp.eq.f32 %p111, %f1209, 0f3EE66666;
|
|
@%p111 bra $L__BB0_88;
|
|
|
|
mov.f32 %f2045, 0f7FFFFFFF;
|
|
|
|
$L__BB0_88:
|
|
add.f32 %f1212, %f442, 0f3EE66666;
|
|
mov.b32 %r355, %f1212;
|
|
setp.lt.s32 %p113, %r355, 2139095040;
|
|
@%p113 bra $L__BB0_93;
|
|
|
|
setp.gtu.f32 %p114, %f442, 0f7F800000;
|
|
@%p114 bra $L__BB0_92;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_92:
|
|
add.f32 %f2045, %f426, 0f3EE66666;
|
|
bra.uni $L__BB0_93;
|
|
|
|
$L__BB0_90:
|
|
setp.neu.f32 %p115, %f442, 0f7F800000;
|
|
@%p115 bra $L__BB0_93;
|
|
|
|
selp.f32 %f2045, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_93:
|
|
setp.eq.f32 %p116, %f426, 0f3F800000;
|
|
selp.f32 %f453, 0f3F800000, %f2045, %p116;
|
|
abs.f32 %f454, %f428;
|
|
setp.lt.f32 %p117, %f454, 0f00800000;
|
|
mul.f32 %f1214, %f454, 0f4B800000;
|
|
selp.f32 %f1215, %f1214, %f454, %p117;
|
|
selp.f32 %f1216, 0fC3170000, 0fC2FE0000, %p117;
|
|
mov.b32 %r356, %f1215;
|
|
and.b32 %r357, %r356, 8388607;
|
|
or.b32 %r358, %r357, 1065353216;
|
|
mov.b32 %f1217, %r358;
|
|
shr.u32 %r359, %r356, 23;
|
|
cvt.rn.f32.u32 %f1218, %r359;
|
|
add.f32 %f1219, %f1216, %f1218;
|
|
setp.gt.f32 %p118, %f1217, 0f3FB504F3;
|
|
mul.f32 %f1220, %f1217, 0f3F000000;
|
|
add.f32 %f1221, %f1219, 0f3F800000;
|
|
selp.f32 %f1222, %f1221, %f1219, %p118;
|
|
selp.f32 %f1223, %f1220, %f1217, %p118;
|
|
add.f32 %f1224, %f1223, 0fBF800000;
|
|
add.f32 %f1225, %f1223, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1226, %f1225;
|
|
add.f32 %f1227, %f1224, %f1224;
|
|
mul.f32 %f1228, %f1227, %f1226;
|
|
mul.f32 %f1229, %f1228, %f1228;
|
|
mov.f32 %f1230, 0f3C4CAF63;
|
|
mov.f32 %f1231, 0f3B18F0FE;
|
|
fma.rn.f32 %f1232, %f1231, %f1229, %f1230;
|
|
mov.f32 %f1233, 0f3DAAAABD;
|
|
fma.rn.f32 %f1234, %f1232, %f1229, %f1233;
|
|
mul.rn.f32 %f1235, %f1234, %f1229;
|
|
mul.rn.f32 %f1236, %f1235, %f1228;
|
|
sub.f32 %f1237, %f1224, %f1228;
|
|
add.f32 %f1238, %f1237, %f1237;
|
|
neg.f32 %f1239, %f1228;
|
|
fma.rn.f32 %f1240, %f1239, %f1224, %f1238;
|
|
mul.rn.f32 %f1241, %f1226, %f1240;
|
|
add.f32 %f1242, %f1236, %f1228;
|
|
sub.f32 %f1243, %f1228, %f1242;
|
|
add.f32 %f1244, %f1236, %f1243;
|
|
add.f32 %f1245, %f1241, %f1244;
|
|
add.f32 %f1246, %f1242, %f1245;
|
|
sub.f32 %f1247, %f1242, %f1246;
|
|
add.f32 %f1248, %f1245, %f1247;
|
|
mov.f32 %f1249, 0f3F317200;
|
|
mul.rn.f32 %f1250, %f1222, %f1249;
|
|
mov.f32 %f1251, 0f35BFBE8E;
|
|
mul.rn.f32 %f1252, %f1222, %f1251;
|
|
add.f32 %f1253, %f1250, %f1246;
|
|
sub.f32 %f1254, %f1250, %f1253;
|
|
add.f32 %f1255, %f1246, %f1254;
|
|
add.f32 %f1256, %f1248, %f1255;
|
|
add.f32 %f1257, %f1252, %f1256;
|
|
add.f32 %f1258, %f1253, %f1257;
|
|
sub.f32 %f1259, %f1253, %f1258;
|
|
add.f32 %f1260, %f1257, %f1259;
|
|
mov.f32 %f1261, 0f3EE66666;
|
|
mul.rn.f32 %f1262, %f1261, %f1258;
|
|
neg.f32 %f1263, %f1262;
|
|
fma.rn.f32 %f1264, %f1261, %f1258, %f1263;
|
|
fma.rn.f32 %f1265, %f1261, %f1260, %f1264;
|
|
mov.f32 %f1266, 0f00000000;
|
|
fma.rn.f32 %f1267, %f1266, %f1258, %f1265;
|
|
add.rn.f32 %f1268, %f1262, %f1267;
|
|
neg.f32 %f1269, %f1268;
|
|
add.rn.f32 %f1270, %f1262, %f1269;
|
|
add.rn.f32 %f1271, %f1270, %f1267;
|
|
mov.b32 %r360, %f1268;
|
|
setp.eq.s32 %p119, %r360, 1118925336;
|
|
add.s32 %r361, %r360, -1;
|
|
mov.b32 %f1272, %r361;
|
|
add.f32 %f1273, %f1271, 0f37000000;
|
|
selp.f32 %f455, %f1273, %f1271, %p119;
|
|
selp.f32 %f1274, %f1272, %f1268, %p119;
|
|
mov.f32 %f1275, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1276, %f1274, %f1275;
|
|
cvt.rzi.f32.f32 %f1277, %f1276;
|
|
abs.f32 %f1278, %f1277;
|
|
setp.gt.f32 %p120, %f1278, 0f42FC0000;
|
|
mov.b32 %r362, %f1277;
|
|
and.b32 %r363, %r362, -2147483648;
|
|
or.b32 %r364, %r363, 1123811328;
|
|
mov.b32 %f1279, %r364;
|
|
selp.f32 %f1280, %f1279, %f1277, %p120;
|
|
mov.f32 %f1281, 0fBF317218;
|
|
fma.rn.f32 %f1282, %f1280, %f1281, %f1274;
|
|
mov.f32 %f1283, 0f3102E308;
|
|
fma.rn.f32 %f1284, %f1280, %f1283, %f1282;
|
|
mul.f32 %f1285, %f1284, 0f3FB8AA3B;
|
|
add.f32 %f1286, %f1280, 0f4B40007F;
|
|
mov.b32 %r365, %f1286;
|
|
shl.b32 %r366, %r365, 23;
|
|
mov.b32 %f1287, %r366;
|
|
ex2.approx.ftz.f32 %f1288, %f1285;
|
|
mul.f32 %f456, %f1288, %f1287;
|
|
setp.eq.f32 %p121, %f456, 0f7F800000;
|
|
mov.f32 %f2046, 0f7F800000;
|
|
@%p121 bra $L__BB0_95;
|
|
|
|
fma.rn.f32 %f2046, %f456, %f455, %f456;
|
|
|
|
$L__BB0_95:
|
|
setp.lt.f32 %p122, %f428, 0f00000000;
|
|
and.pred %p6, %p122, %p93;
|
|
setp.eq.f32 %p124, %f428, 0f00000000;
|
|
@%p124 bra $L__BB0_99;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_99:
|
|
add.f32 %f1293, %f428, %f428;
|
|
selp.f32 %f2048, %f1293, 0f00000000, %p93;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_96:
|
|
mov.b32 %r367, %f2046;
|
|
xor.b32 %r368, %r367, -2147483648;
|
|
mov.b32 %f1289, %r368;
|
|
selp.f32 %f2048, %f1289, %f2046, %p6;
|
|
setp.geu.f32 %p125, %f428, 0f00000000;
|
|
@%p125 bra $L__BB0_100;
|
|
|
|
mov.f32 %f1290, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1291, %f1290;
|
|
setp.eq.f32 %p126, %f1291, 0f3EE66666;
|
|
@%p126 bra $L__BB0_100;
|
|
|
|
mov.f32 %f2048, 0f7FFFFFFF;
|
|
|
|
$L__BB0_100:
|
|
add.f32 %f1294, %f454, 0f3EE66666;
|
|
mov.b32 %r369, %f1294;
|
|
setp.lt.s32 %p128, %r369, 2139095040;
|
|
@%p128 bra $L__BB0_105;
|
|
|
|
setp.gtu.f32 %p129, %f454, 0f7F800000;
|
|
@%p129 bra $L__BB0_104;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f2048, %f428, 0f3EE66666;
|
|
bra.uni $L__BB0_105;
|
|
|
|
$L__BB0_102:
|
|
setp.neu.f32 %p130, %f454, 0f7F800000;
|
|
@%p130 bra $L__BB0_105;
|
|
|
|
selp.f32 %f2048, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_105:
|
|
setp.eq.f32 %p131, %f428, 0f3F800000;
|
|
mov.f32 %f1296, 0f3F800000;
|
|
selp.f32 %f1297, 0f3F800000, %f2048, %p131;
|
|
ld.const.u64 %rd103, [params+144];
|
|
cvta.to.global.u64 %rd21, %rd103;
|
|
ld.const.u32 %r370, [params+136];
|
|
mad.lo.s32 %r371, %r370, %r7, %r6;
|
|
cvt.u64.u32 %rd22, %r371;
|
|
min.f32 %f1298, %f441, %f1296;
|
|
mov.f32 %f1299, 0f00000000;
|
|
max.f32 %f465, %f1299, %f1298;
|
|
min.f32 %f1300, %f453, %f1296;
|
|
max.f32 %f466, %f1299, %f1300;
|
|
min.f32 %f1301, %f1297, %f1296;
|
|
max.f32 %f467, %f1299, %f1301;
|
|
mov.f32 %f1302, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1303, %f1302;
|
|
add.f32 %f1304, %f1303, %f1303;
|
|
mov.f32 %f1305, 0f3ED55555;
|
|
sub.f32 %f1306, %f1305, %f1304;
|
|
abs.f32 %f468, %f1306;
|
|
abs.f32 %f469, %f465;
|
|
setp.lt.f32 %p132, %f469, 0f00800000;
|
|
mul.f32 %f1307, %f469, 0f4B800000;
|
|
selp.f32 %f1308, %f1307, %f469, %p132;
|
|
selp.f32 %f1309, 0fC3170000, 0fC2FE0000, %p132;
|
|
mov.b32 %r372, %f1308;
|
|
and.b32 %r373, %r372, 8388607;
|
|
or.b32 %r374, %r373, 1065353216;
|
|
mov.b32 %f1310, %r374;
|
|
shr.u32 %r375, %r372, 23;
|
|
cvt.rn.f32.u32 %f1311, %r375;
|
|
add.f32 %f1312, %f1309, %f1311;
|
|
setp.gt.f32 %p133, %f1310, 0f3FB504F3;
|
|
mul.f32 %f1313, %f1310, 0f3F000000;
|
|
add.f32 %f1314, %f1312, 0f3F800000;
|
|
selp.f32 %f1315, %f1314, %f1312, %p133;
|
|
selp.f32 %f1316, %f1313, %f1310, %p133;
|
|
add.f32 %f1317, %f1316, 0fBF800000;
|
|
add.f32 %f1318, %f1316, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1319, %f1318;
|
|
add.f32 %f1320, %f1317, %f1317;
|
|
mul.f32 %f1321, %f1320, %f1319;
|
|
mul.f32 %f1322, %f1321, %f1321;
|
|
mov.f32 %f1323, 0f3C4CAF63;
|
|
mov.f32 %f1324, 0f3B18F0FE;
|
|
fma.rn.f32 %f1325, %f1324, %f1322, %f1323;
|
|
mov.f32 %f1326, 0f3DAAAABD;
|
|
fma.rn.f32 %f1327, %f1325, %f1322, %f1326;
|
|
mul.rn.f32 %f1328, %f1327, %f1322;
|
|
mul.rn.f32 %f1329, %f1328, %f1321;
|
|
sub.f32 %f1330, %f1317, %f1321;
|
|
add.f32 %f1331, %f1330, %f1330;
|
|
neg.f32 %f1332, %f1321;
|
|
fma.rn.f32 %f1333, %f1332, %f1317, %f1331;
|
|
mul.rn.f32 %f1334, %f1319, %f1333;
|
|
add.f32 %f1335, %f1329, %f1321;
|
|
sub.f32 %f1336, %f1321, %f1335;
|
|
add.f32 %f1337, %f1329, %f1336;
|
|
add.f32 %f1338, %f1334, %f1337;
|
|
add.f32 %f1339, %f1335, %f1338;
|
|
sub.f32 %f1340, %f1335, %f1339;
|
|
add.f32 %f1341, %f1338, %f1340;
|
|
mov.f32 %f1342, 0f3F317200;
|
|
mul.rn.f32 %f1343, %f1315, %f1342;
|
|
mov.f32 %f1344, 0f35BFBE8E;
|
|
mul.rn.f32 %f1345, %f1315, %f1344;
|
|
add.f32 %f1346, %f1343, %f1339;
|
|
sub.f32 %f1347, %f1343, %f1346;
|
|
add.f32 %f1348, %f1339, %f1347;
|
|
add.f32 %f1349, %f1341, %f1348;
|
|
add.f32 %f1350, %f1345, %f1349;
|
|
add.f32 %f1351, %f1346, %f1350;
|
|
sub.f32 %f1352, %f1346, %f1351;
|
|
add.f32 %f1353, %f1350, %f1352;
|
|
mul.rn.f32 %f1354, %f1305, %f1351;
|
|
neg.f32 %f1355, %f1354;
|
|
fma.rn.f32 %f1356, %f1305, %f1351, %f1355;
|
|
fma.rn.f32 %f1357, %f1305, %f1353, %f1356;
|
|
fma.rn.f32 %f1358, %f1299, %f1351, %f1357;
|
|
add.rn.f32 %f1359, %f1354, %f1358;
|
|
neg.f32 %f1360, %f1359;
|
|
add.rn.f32 %f1361, %f1354, %f1360;
|
|
add.rn.f32 %f1362, %f1361, %f1358;
|
|
mov.b32 %r376, %f1359;
|
|
setp.eq.s32 %p134, %r376, 1118925336;
|
|
add.s32 %r377, %r376, -1;
|
|
mov.b32 %f1363, %r377;
|
|
add.f32 %f1364, %f1362, 0f37000000;
|
|
selp.f32 %f470, %f1364, %f1362, %p134;
|
|
selp.f32 %f1365, %f1363, %f1359, %p134;
|
|
mov.f32 %f1366, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1367, %f1365, %f1366;
|
|
cvt.rzi.f32.f32 %f1368, %f1367;
|
|
abs.f32 %f1369, %f1368;
|
|
setp.gt.f32 %p135, %f1369, 0f42FC0000;
|
|
mov.b32 %r378, %f1368;
|
|
and.b32 %r379, %r378, -2147483648;
|
|
or.b32 %r380, %r379, 1123811328;
|
|
mov.b32 %f1370, %r380;
|
|
selp.f32 %f1371, %f1370, %f1368, %p135;
|
|
mov.f32 %f1372, 0fBF317218;
|
|
fma.rn.f32 %f1373, %f1371, %f1372, %f1365;
|
|
mov.f32 %f1374, 0f3102E308;
|
|
fma.rn.f32 %f1375, %f1371, %f1374, %f1373;
|
|
mul.f32 %f1376, %f1375, 0f3FB8AA3B;
|
|
add.f32 %f1377, %f1371, 0f4B40007F;
|
|
mov.b32 %r381, %f1377;
|
|
shl.b32 %r382, %r381, 23;
|
|
mov.b32 %f1378, %r382;
|
|
ex2.approx.ftz.f32 %f1379, %f1376;
|
|
mul.f32 %f471, %f1379, %f1378;
|
|
setp.eq.f32 %p136, %f471, 0f7F800000;
|
|
mov.f32 %f2049, 0f7F800000;
|
|
@%p136 bra $L__BB0_107;
|
|
|
|
fma.rn.f32 %f2049, %f471, %f470, %f471;
|
|
|
|
$L__BB0_107:
|
|
setp.lt.f32 %p137, %f465, 0f00000000;
|
|
setp.eq.f32 %p138, %f468, 0f3F800000;
|
|
and.pred %p7, %p137, %p138;
|
|
setp.eq.f32 %p139, %f465, 0f00000000;
|
|
@%p139 bra $L__BB0_111;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_111:
|
|
add.f32 %f1384, %f465, %f465;
|
|
selp.f32 %f2051, %f1384, 0f00000000, %p138;
|
|
bra.uni $L__BB0_112;
|
|
|
|
$L__BB0_108:
|
|
mov.b32 %r383, %f2049;
|
|
xor.b32 %r384, %r383, -2147483648;
|
|
mov.b32 %f1380, %r384;
|
|
selp.f32 %f2051, %f1380, %f2049, %p7;
|
|
setp.geu.f32 %p140, %f465, 0f00000000;
|
|
@%p140 bra $L__BB0_112;
|
|
|
|
mov.f32 %f1381, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1382, %f1381;
|
|
setp.eq.f32 %p141, %f1382, 0f3ED55555;
|
|
@%p141 bra $L__BB0_112;
|
|
|
|
mov.f32 %f2051, 0f7FFFFFFF;
|
|
|
|
$L__BB0_112:
|
|
add.f32 %f1385, %f469, 0f3ED55555;
|
|
mov.b32 %r385, %f1385;
|
|
setp.lt.s32 %p143, %r385, 2139095040;
|
|
@%p143 bra $L__BB0_117;
|
|
|
|
setp.gtu.f32 %p144, %f469, 0f7F800000;
|
|
@%p144 bra $L__BB0_116;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_116:
|
|
add.f32 %f2051, %f465, 0f3ED55555;
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_114:
|
|
setp.neu.f32 %p145, %f469, 0f7F800000;
|
|
@%p145 bra $L__BB0_117;
|
|
|
|
selp.f32 %f2051, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_117:
|
|
abs.f32 %f480, %f466;
|
|
setp.lt.f32 %p146, %f480, 0f00800000;
|
|
mul.f32 %f1387, %f480, 0f4B800000;
|
|
selp.f32 %f1388, %f1387, %f480, %p146;
|
|
selp.f32 %f1389, 0fC3170000, 0fC2FE0000, %p146;
|
|
mov.b32 %r386, %f1388;
|
|
and.b32 %r387, %r386, 8388607;
|
|
or.b32 %r388, %r387, 1065353216;
|
|
mov.b32 %f1390, %r388;
|
|
shr.u32 %r389, %r386, 23;
|
|
cvt.rn.f32.u32 %f1391, %r389;
|
|
add.f32 %f1392, %f1389, %f1391;
|
|
setp.gt.f32 %p147, %f1390, 0f3FB504F3;
|
|
mul.f32 %f1393, %f1390, 0f3F000000;
|
|
add.f32 %f1394, %f1392, 0f3F800000;
|
|
selp.f32 %f1395, %f1394, %f1392, %p147;
|
|
selp.f32 %f1396, %f1393, %f1390, %p147;
|
|
add.f32 %f1397, %f1396, 0fBF800000;
|
|
add.f32 %f1398, %f1396, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1399, %f1398;
|
|
add.f32 %f1400, %f1397, %f1397;
|
|
mul.f32 %f1401, %f1400, %f1399;
|
|
mul.f32 %f1402, %f1401, %f1401;
|
|
mov.f32 %f1403, 0f3C4CAF63;
|
|
mov.f32 %f1404, 0f3B18F0FE;
|
|
fma.rn.f32 %f1405, %f1404, %f1402, %f1403;
|
|
mov.f32 %f1406, 0f3DAAAABD;
|
|
fma.rn.f32 %f1407, %f1405, %f1402, %f1406;
|
|
mul.rn.f32 %f1408, %f1407, %f1402;
|
|
mul.rn.f32 %f1409, %f1408, %f1401;
|
|
sub.f32 %f1410, %f1397, %f1401;
|
|
add.f32 %f1411, %f1410, %f1410;
|
|
neg.f32 %f1412, %f1401;
|
|
fma.rn.f32 %f1413, %f1412, %f1397, %f1411;
|
|
mul.rn.f32 %f1414, %f1399, %f1413;
|
|
add.f32 %f1415, %f1409, %f1401;
|
|
sub.f32 %f1416, %f1401, %f1415;
|
|
add.f32 %f1417, %f1409, %f1416;
|
|
add.f32 %f1418, %f1414, %f1417;
|
|
add.f32 %f1419, %f1415, %f1418;
|
|
sub.f32 %f1420, %f1415, %f1419;
|
|
add.f32 %f1421, %f1418, %f1420;
|
|
mov.f32 %f1422, 0f3F317200;
|
|
mul.rn.f32 %f1423, %f1395, %f1422;
|
|
mov.f32 %f1424, 0f35BFBE8E;
|
|
mul.rn.f32 %f1425, %f1395, %f1424;
|
|
add.f32 %f1426, %f1423, %f1419;
|
|
sub.f32 %f1427, %f1423, %f1426;
|
|
add.f32 %f1428, %f1419, %f1427;
|
|
add.f32 %f1429, %f1421, %f1428;
|
|
add.f32 %f1430, %f1425, %f1429;
|
|
add.f32 %f1431, %f1426, %f1430;
|
|
sub.f32 %f1432, %f1426, %f1431;
|
|
add.f32 %f1433, %f1430, %f1432;
|
|
mov.f32 %f1434, 0f3ED55555;
|
|
mul.rn.f32 %f1435, %f1434, %f1431;
|
|
neg.f32 %f1436, %f1435;
|
|
fma.rn.f32 %f1437, %f1434, %f1431, %f1436;
|
|
fma.rn.f32 %f1438, %f1434, %f1433, %f1437;
|
|
mov.f32 %f1439, 0f00000000;
|
|
fma.rn.f32 %f1440, %f1439, %f1431, %f1438;
|
|
add.rn.f32 %f1441, %f1435, %f1440;
|
|
neg.f32 %f1442, %f1441;
|
|
add.rn.f32 %f1443, %f1435, %f1442;
|
|
add.rn.f32 %f1444, %f1443, %f1440;
|
|
mov.b32 %r390, %f1441;
|
|
setp.eq.s32 %p148, %r390, 1118925336;
|
|
add.s32 %r391, %r390, -1;
|
|
mov.b32 %f1445, %r391;
|
|
add.f32 %f1446, %f1444, 0f37000000;
|
|
selp.f32 %f481, %f1446, %f1444, %p148;
|
|
selp.f32 %f1447, %f1445, %f1441, %p148;
|
|
mov.f32 %f1448, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1449, %f1447, %f1448;
|
|
cvt.rzi.f32.f32 %f1450, %f1449;
|
|
abs.f32 %f1451, %f1450;
|
|
setp.gt.f32 %p149, %f1451, 0f42FC0000;
|
|
mov.b32 %r392, %f1450;
|
|
and.b32 %r393, %r392, -2147483648;
|
|
or.b32 %r394, %r393, 1123811328;
|
|
mov.b32 %f1452, %r394;
|
|
selp.f32 %f1453, %f1452, %f1450, %p149;
|
|
mov.f32 %f1454, 0fBF317218;
|
|
fma.rn.f32 %f1455, %f1453, %f1454, %f1447;
|
|
mov.f32 %f1456, 0f3102E308;
|
|
fma.rn.f32 %f1457, %f1453, %f1456, %f1455;
|
|
mul.f32 %f1458, %f1457, 0f3FB8AA3B;
|
|
add.f32 %f1459, %f1453, 0f4B40007F;
|
|
mov.b32 %r395, %f1459;
|
|
shl.b32 %r396, %r395, 23;
|
|
mov.b32 %f1460, %r396;
|
|
ex2.approx.ftz.f32 %f1461, %f1458;
|
|
mul.f32 %f482, %f1461, %f1460;
|
|
setp.eq.f32 %p150, %f482, 0f7F800000;
|
|
mov.f32 %f2052, 0f7F800000;
|
|
@%p150 bra $L__BB0_119;
|
|
|
|
fma.rn.f32 %f2052, %f482, %f481, %f482;
|
|
|
|
$L__BB0_119:
|
|
setp.lt.f32 %p151, %f466, 0f00000000;
|
|
and.pred %p8, %p151, %p138;
|
|
setp.eq.f32 %p153, %f466, 0f00000000;
|
|
@%p153 bra $L__BB0_123;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_123:
|
|
add.f32 %f1466, %f466, %f466;
|
|
selp.f32 %f2054, %f1466, 0f00000000, %p138;
|
|
bra.uni $L__BB0_124;
|
|
|
|
$L__BB0_120:
|
|
mov.b32 %r397, %f2052;
|
|
xor.b32 %r398, %r397, -2147483648;
|
|
mov.b32 %f1462, %r398;
|
|
selp.f32 %f2054, %f1462, %f2052, %p8;
|
|
setp.geu.f32 %p154, %f466, 0f00000000;
|
|
@%p154 bra $L__BB0_124;
|
|
|
|
mov.f32 %f1463, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1464, %f1463;
|
|
setp.eq.f32 %p155, %f1464, 0f3ED55555;
|
|
@%p155 bra $L__BB0_124;
|
|
|
|
mov.f32 %f2054, 0f7FFFFFFF;
|
|
|
|
$L__BB0_124:
|
|
add.f32 %f1467, %f480, 0f3ED55555;
|
|
mov.b32 %r399, %f1467;
|
|
setp.lt.s32 %p157, %r399, 2139095040;
|
|
@%p157 bra $L__BB0_129;
|
|
|
|
setp.gtu.f32 %p158, %f480, 0f7F800000;
|
|
@%p158 bra $L__BB0_128;
|
|
bra.uni $L__BB0_126;
|
|
|
|
$L__BB0_128:
|
|
add.f32 %f2054, %f466, 0f3ED55555;
|
|
bra.uni $L__BB0_129;
|
|
|
|
$L__BB0_126:
|
|
setp.neu.f32 %p159, %f480, 0f7F800000;
|
|
@%p159 bra $L__BB0_129;
|
|
|
|
selp.f32 %f2054, 0fFF800000, 0f7F800000, %p8;
|
|
|
|
$L__BB0_129:
|
|
abs.f32 %f491, %f467;
|
|
setp.lt.f32 %p160, %f491, 0f00800000;
|
|
mul.f32 %f1469, %f491, 0f4B800000;
|
|
selp.f32 %f1470, %f1469, %f491, %p160;
|
|
selp.f32 %f1471, 0fC3170000, 0fC2FE0000, %p160;
|
|
mov.b32 %r400, %f1470;
|
|
and.b32 %r401, %r400, 8388607;
|
|
or.b32 %r402, %r401, 1065353216;
|
|
mov.b32 %f1472, %r402;
|
|
shr.u32 %r403, %r400, 23;
|
|
cvt.rn.f32.u32 %f1473, %r403;
|
|
add.f32 %f1474, %f1471, %f1473;
|
|
setp.gt.f32 %p161, %f1472, 0f3FB504F3;
|
|
mul.f32 %f1475, %f1472, 0f3F000000;
|
|
add.f32 %f1476, %f1474, 0f3F800000;
|
|
selp.f32 %f1477, %f1476, %f1474, %p161;
|
|
selp.f32 %f1478, %f1475, %f1472, %p161;
|
|
add.f32 %f1479, %f1478, 0fBF800000;
|
|
add.f32 %f1480, %f1478, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1481, %f1480;
|
|
add.f32 %f1482, %f1479, %f1479;
|
|
mul.f32 %f1483, %f1482, %f1481;
|
|
mul.f32 %f1484, %f1483, %f1483;
|
|
mov.f32 %f1485, 0f3C4CAF63;
|
|
mov.f32 %f1486, 0f3B18F0FE;
|
|
fma.rn.f32 %f1487, %f1486, %f1484, %f1485;
|
|
mov.f32 %f1488, 0f3DAAAABD;
|
|
fma.rn.f32 %f1489, %f1487, %f1484, %f1488;
|
|
mul.rn.f32 %f1490, %f1489, %f1484;
|
|
mul.rn.f32 %f1491, %f1490, %f1483;
|
|
sub.f32 %f1492, %f1479, %f1483;
|
|
add.f32 %f1493, %f1492, %f1492;
|
|
neg.f32 %f1494, %f1483;
|
|
fma.rn.f32 %f1495, %f1494, %f1479, %f1493;
|
|
mul.rn.f32 %f1496, %f1481, %f1495;
|
|
add.f32 %f1497, %f1491, %f1483;
|
|
sub.f32 %f1498, %f1483, %f1497;
|
|
add.f32 %f1499, %f1491, %f1498;
|
|
add.f32 %f1500, %f1496, %f1499;
|
|
add.f32 %f1501, %f1497, %f1500;
|
|
sub.f32 %f1502, %f1497, %f1501;
|
|
add.f32 %f1503, %f1500, %f1502;
|
|
mov.f32 %f1504, 0f3F317200;
|
|
mul.rn.f32 %f1505, %f1477, %f1504;
|
|
mov.f32 %f1506, 0f35BFBE8E;
|
|
mul.rn.f32 %f1507, %f1477, %f1506;
|
|
add.f32 %f1508, %f1505, %f1501;
|
|
sub.f32 %f1509, %f1505, %f1508;
|
|
add.f32 %f1510, %f1501, %f1509;
|
|
add.f32 %f1511, %f1503, %f1510;
|
|
add.f32 %f1512, %f1507, %f1511;
|
|
add.f32 %f1513, %f1508, %f1512;
|
|
sub.f32 %f1514, %f1508, %f1513;
|
|
add.f32 %f1515, %f1512, %f1514;
|
|
mov.f32 %f1516, 0f3ED55555;
|
|
mul.rn.f32 %f1517, %f1516, %f1513;
|
|
neg.f32 %f1518, %f1517;
|
|
fma.rn.f32 %f1519, %f1516, %f1513, %f1518;
|
|
fma.rn.f32 %f1520, %f1516, %f1515, %f1519;
|
|
mov.f32 %f1521, 0f00000000;
|
|
fma.rn.f32 %f1522, %f1521, %f1513, %f1520;
|
|
add.rn.f32 %f1523, %f1517, %f1522;
|
|
neg.f32 %f1524, %f1523;
|
|
add.rn.f32 %f1525, %f1517, %f1524;
|
|
add.rn.f32 %f1526, %f1525, %f1522;
|
|
mov.b32 %r404, %f1523;
|
|
setp.eq.s32 %p162, %r404, 1118925336;
|
|
add.s32 %r405, %r404, -1;
|
|
mov.b32 %f1527, %r405;
|
|
add.f32 %f1528, %f1526, 0f37000000;
|
|
selp.f32 %f492, %f1528, %f1526, %p162;
|
|
selp.f32 %f1529, %f1527, %f1523, %p162;
|
|
mov.f32 %f1530, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1531, %f1529, %f1530;
|
|
cvt.rzi.f32.f32 %f1532, %f1531;
|
|
abs.f32 %f1533, %f1532;
|
|
setp.gt.f32 %p163, %f1533, 0f42FC0000;
|
|
mov.b32 %r406, %f1532;
|
|
and.b32 %r407, %r406, -2147483648;
|
|
or.b32 %r408, %r407, 1123811328;
|
|
mov.b32 %f1534, %r408;
|
|
selp.f32 %f1535, %f1534, %f1532, %p163;
|
|
mov.f32 %f1536, 0fBF317218;
|
|
fma.rn.f32 %f1537, %f1535, %f1536, %f1529;
|
|
mov.f32 %f1538, 0f3102E308;
|
|
fma.rn.f32 %f1539, %f1535, %f1538, %f1537;
|
|
mul.f32 %f1540, %f1539, 0f3FB8AA3B;
|
|
add.f32 %f1541, %f1535, 0f4B40007F;
|
|
mov.b32 %r409, %f1541;
|
|
shl.b32 %r410, %r409, 23;
|
|
mov.b32 %f1542, %r410;
|
|
ex2.approx.ftz.f32 %f1543, %f1540;
|
|
mul.f32 %f493, %f1543, %f1542;
|
|
setp.eq.f32 %p164, %f493, 0f7F800000;
|
|
mov.f32 %f2055, 0f7F800000;
|
|
@%p164 bra $L__BB0_131;
|
|
|
|
fma.rn.f32 %f2055, %f493, %f492, %f493;
|
|
|
|
$L__BB0_131:
|
|
setp.lt.f32 %p165, %f467, 0f00000000;
|
|
and.pred %p9, %p165, %p138;
|
|
setp.eq.f32 %p167, %f467, 0f00000000;
|
|
@%p167 bra $L__BB0_135;
|
|
bra.uni $L__BB0_132;
|
|
|
|
$L__BB0_135:
|
|
add.f32 %f1548, %f467, %f467;
|
|
selp.f32 %f2057, %f1548, 0f00000000, %p138;
|
|
bra.uni $L__BB0_136;
|
|
|
|
$L__BB0_132:
|
|
mov.b32 %r411, %f2055;
|
|
xor.b32 %r412, %r411, -2147483648;
|
|
mov.b32 %f1544, %r412;
|
|
selp.f32 %f2057, %f1544, %f2055, %p9;
|
|
setp.geu.f32 %p168, %f467, 0f00000000;
|
|
@%p168 bra $L__BB0_136;
|
|
|
|
mov.f32 %f1545, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1546, %f1545;
|
|
setp.eq.f32 %p169, %f1546, 0f3ED55555;
|
|
@%p169 bra $L__BB0_136;
|
|
|
|
mov.f32 %f2057, 0f7FFFFFFF;
|
|
|
|
$L__BB0_136:
|
|
add.f32 %f1549, %f491, 0f3ED55555;
|
|
mov.b32 %r413, %f1549;
|
|
setp.lt.s32 %p171, %r413, 2139095040;
|
|
@%p171 bra $L__BB0_141;
|
|
|
|
setp.gtu.f32 %p172, %f491, 0f7F800000;
|
|
@%p172 bra $L__BB0_140;
|
|
bra.uni $L__BB0_138;
|
|
|
|
$L__BB0_140:
|
|
add.f32 %f2057, %f467, 0f3ED55555;
|
|
bra.uni $L__BB0_141;
|
|
|
|
$L__BB0_138:
|
|
setp.neu.f32 %p173, %f491, 0f7F800000;
|
|
@%p173 bra $L__BB0_141;
|
|
|
|
selp.f32 %f2057, 0fFF800000, 0f7F800000, %p9;
|
|
|
|
$L__BB0_141:
|
|
fma.rn.f32 %f1550, %f2051, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p174, %f465, 0f3F800000;
|
|
mov.f32 %f1551, 0f3F800000;
|
|
selp.f32 %f1552, 0f3F7FFFFF, %f1550, %p174;
|
|
mul.f32 %f1553, %f465, 0f414EB852;
|
|
setp.lt.f32 %p175, %f465, 0f3B4D2E1C;
|
|
selp.f32 %f1554, %f1553, %f1552, %p175;
|
|
fma.rn.f32 %f1555, %f2054, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p176, %f466, 0f3F800000;
|
|
selp.f32 %f1556, 0f3F7FFFFF, %f1555, %p176;
|
|
mul.f32 %f1557, %f466, 0f414EB852;
|
|
setp.lt.f32 %p177, %f466, 0f3B4D2E1C;
|
|
selp.f32 %f1558, %f1557, %f1556, %p177;
|
|
fma.rn.f32 %f1559, %f2057, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p178, %f467, 0f3F800000;
|
|
selp.f32 %f1560, 0f3F7FFFFF, %f1559, %p178;
|
|
mul.f32 %f1561, %f467, 0f414EB852;
|
|
setp.lt.f32 %p179, %f467, 0f3B4D2E1C;
|
|
selp.f32 %f1562, %f1561, %f1560, %p179;
|
|
min.f32 %f1563, %f1554, %f1551;
|
|
mov.f32 %f1564, 0f00000000;
|
|
max.f32 %f1565, %f1564, %f1563;
|
|
mul.f32 %f1566, %f1565, 0f43800000;
|
|
cvt.rzi.u32.f32 %r414, %f1566;
|
|
min.u32 %r415, %r414, 255;
|
|
min.f32 %f1567, %f1558, %f1551;
|
|
max.f32 %f1568, %f1564, %f1567;
|
|
mul.f32 %f1569, %f1568, 0f43800000;
|
|
cvt.rzi.u32.f32 %r416, %f1569;
|
|
min.u32 %r417, %r416, 255;
|
|
min.f32 %f1570, %f1562, %f1551;
|
|
max.f32 %f1571, %f1564, %f1570;
|
|
mul.f32 %f1572, %f1571, 0f43800000;
|
|
cvt.rzi.u32.f32 %r418, %f1572;
|
|
min.u32 %r419, %r418, 255;
|
|
shl.b64 %rd104, %rd22, 2;
|
|
add.s64 %rd105, %rd21, %rd104;
|
|
cvt.u16.u32 %rs18, %r419;
|
|
cvt.u16.u32 %rs19, %r417;
|
|
cvt.u16.u32 %rs20, %r415;
|
|
mov.u16 %rs21, 255;
|
|
st.global.v4.u8 [%rd105], {%rs20, %rs19, %rs18, %rs21};
|
|
|
|
$L__BB0_142:
|
|
and.b32 %r420, %r53, 4;
|
|
setp.eq.s32 %p180, %r420, 0;
|
|
ld.const.u32 %r485, [params+108];
|
|
@%p180 bra $L__BB0_146;
|
|
|
|
setp.eq.s32 %p181, %r485, 0;
|
|
ld.const.u64 %rd106, [params+224];
|
|
cvta.to.global.u64 %rd107, %rd106;
|
|
ld.const.u32 %r421, [params+216];
|
|
mad.lo.s32 %r422, %r421, %r7, %r6;
|
|
mul.wide.u32 %rd108, %r422, 8;
|
|
add.s64 %rd23, %rd107, %rd108;
|
|
@%p181 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs29, %rs30, %rs31, %rs32}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1573, %rs29;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1574, %rs30;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1575, %rs31;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1576, %f425, %f1573;
|
|
add.f32 %f1577, %f426, %f1574;
|
|
add.f32 %f1578, %f428, %f1575;
|
|
mov.f32 %f1579, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f1578;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs26, %f1577;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs25, %f1576;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f1579;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs25, %rs26, %rs27, %rs28};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1583, 0f3F800000;
|
|
mov.u32 %r485, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f1583;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f428;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f426;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f425;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs33, %rs34, %rs35, %rs36};
|
|
|
|
$L__BB0_146:
|
|
selp.f32 %f1584, 0f40800000, 0f3F800000, %p207;
|
|
mul.f32 %f1585, %f1584, %f2030;
|
|
mul.f32 %f1586, %f1584, %f2031;
|
|
mul.f32 %f1587, %f1584, %f2032;
|
|
mul.f32 %f1588, %f1584, %f2027;
|
|
mul.f32 %f1589, %f1584, %f2028;
|
|
mul.f32 %f1590, %f1584, %f2029;
|
|
mul.f32 %f1591, %f1584, %f2024;
|
|
mul.f32 %f1592, %f1584, %f2025;
|
|
mul.f32 %f1593, %f1584, %f2026;
|
|
mul.f32 %f1594, %f1584, %f2021;
|
|
mul.f32 %f1595, %f1584, %f2022;
|
|
mul.f32 %f1596, %f1584, %f2023;
|
|
mul.f32 %f1597, %f1584, %f2018;
|
|
mul.f32 %f1598, %f1584, %f2019;
|
|
mul.f32 %f1599, %f1584, %f2020;
|
|
mul.f32 %f1600, %f1584, %f2015;
|
|
mul.f32 %f1601, %f1584, %f2016;
|
|
mul.f32 %f1602, %f1584, %f2017;
|
|
mul.f32 %f1603, %f1584, %f2012;
|
|
mul.f32 %f1604, %f1584, %f2013;
|
|
mul.f32 %f1605, %f1584, %f2014;
|
|
mul.f32 %f1606, %f1584, %f2009;
|
|
mul.f32 %f1607, %f1584, %f2010;
|
|
mul.f32 %f1608, %f1584, %f2011;
|
|
mul.f32 %f1609, %f1584, %f2006;
|
|
mul.f32 %f1610, %f1584, %f2007;
|
|
mul.f32 %f1611, %f1584, %f2008;
|
|
mul.f32 %f1612, %f1585, %f1043;
|
|
mul.f32 %f1613, %f1586, %f1044;
|
|
mul.f32 %f1614, %f1587, %f427;
|
|
mul.f32 %f502, %f1588, %f1043;
|
|
mul.f32 %f503, %f1589, %f1044;
|
|
mul.f32 %f504, %f1590, %f427;
|
|
mul.f32 %f505, %f1591, %f1043;
|
|
mul.f32 %f506, %f1592, %f1044;
|
|
mul.f32 %f507, %f1593, %f427;
|
|
mul.f32 %f508, %f1594, %f1043;
|
|
mul.f32 %f509, %f1595, %f1044;
|
|
mul.f32 %f510, %f1596, %f427;
|
|
mul.f32 %f511, %f1597, %f1043;
|
|
mul.f32 %f512, %f1598, %f1044;
|
|
mul.f32 %f513, %f1599, %f427;
|
|
mul.f32 %f514, %f1600, %f1043;
|
|
mul.f32 %f515, %f1601, %f1044;
|
|
mul.f32 %f516, %f1602, %f427;
|
|
mul.f32 %f517, %f1603, %f1043;
|
|
mul.f32 %f518, %f1604, %f1044;
|
|
mul.f32 %f519, %f1605, %f427;
|
|
mul.f32 %f520, %f1606, %f1043;
|
|
mul.f32 %f521, %f1607, %f1044;
|
|
mul.f32 %f522, %f1608, %f427;
|
|
mul.f32 %f523, %f1609, %f1043;
|
|
mul.f32 %f524, %f1610, %f1044;
|
|
mul.f32 %f525, %f1611, %f427;
|
|
mul.f32 %f526, %f1612, 0f3F558750;
|
|
mul.f32 %f527, %f1613, 0f3F558750;
|
|
mul.f32 %f528, %f1614, 0f3F558750;
|
|
ld.const.u64 %rd109, [params+256];
|
|
cvta.to.global.u64 %rd110, %rd109;
|
|
ld.const.u32 %r424, [params+248];
|
|
mad.lo.s32 %r425, %r424, %r7, %r6;
|
|
mul.wide.u32 %rd111, %r425, 8;
|
|
add.s64 %rd24, %rd110, %rd111;
|
|
setp.eq.s32 %p182, %r485, 0;
|
|
@%p182 bra $L__BB0_148;
|
|
|
|
ld.global.v4.u16 {%rs44, %rs45, %rs46, %rs47}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1615, %rs44;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1616, %rs45;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1617, %rs46;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1618, %f526, %f1615;
|
|
add.f32 %f1619, %f527, %f1616;
|
|
add.f32 %f1620, %f528, %f1617;
|
|
mov.f32 %f1621, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f1620;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f1619;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f1618;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f1621;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs40, %rs41, %rs42, %rs43};
|
|
bra.uni $L__BB0_149;
|
|
|
|
$L__BB0_148:
|
|
mov.f32 %f1625, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f1625;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f528;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f527;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f526;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs48, %rs49, %rs50, %rs51};
|
|
|
|
$L__BB0_149:
|
|
mul.f32 %f529, %f502, 0f3FB8EBD1;
|
|
mul.f32 %f530, %f503, 0f3FB8EBD1;
|
|
mul.f32 %f531, %f504, 0f3FB8EBD1;
|
|
ld.const.u64 %rd112, [params+272];
|
|
cvta.to.global.u64 %rd113, %rd112;
|
|
ld.const.u32 %r426, [params+264];
|
|
mad.lo.s32 %r427, %r426, %r7, %r6;
|
|
mul.wide.u32 %rd114, %r427, 8;
|
|
add.s64 %rd25, %rd113, %rd114;
|
|
@%p182 bra $L__BB0_151;
|
|
|
|
ld.global.v4.u16 {%rs59, %rs60, %rs61, %rs62}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1626, %rs59;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1627, %rs60;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1628, %rs61;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1629, %f529, %f1626;
|
|
add.f32 %f1630, %f530, %f1627;
|
|
add.f32 %f1631, %f531, %f1628;
|
|
mov.f32 %f1632, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1631;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f1630;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f1629;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f1632;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs55, %rs56, %rs57, %rs58};
|
|
bra.uni $L__BB0_152;
|
|
|
|
$L__BB0_151:
|
|
mov.f32 %f1636, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f1636;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f531;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f530;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f529;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs63, %rs64, %rs65, %rs66};
|
|
|
|
$L__BB0_152:
|
|
mul.f32 %f532, %f505, 0f3FB8EBD1;
|
|
mul.f32 %f533, %f506, 0f3FB8EBD1;
|
|
mul.f32 %f534, %f507, 0f3FB8EBD1;
|
|
ld.const.u64 %rd115, [params+288];
|
|
cvta.to.global.u64 %rd116, %rd115;
|
|
ld.const.u32 %r428, [params+280];
|
|
mad.lo.s32 %r429, %r428, %r7, %r6;
|
|
mul.wide.u32 %rd117, %r429, 8;
|
|
add.s64 %rd26, %rd116, %rd117;
|
|
@%p182 bra $L__BB0_154;
|
|
|
|
ld.global.v4.u16 {%rs74, %rs75, %rs76, %rs77}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1637, %rs74;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1638, %rs75;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1639, %rs76;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1640, %f532, %f1637;
|
|
add.f32 %f1641, %f533, %f1638;
|
|
add.f32 %f1642, %f534, %f1639;
|
|
mov.f32 %f1643, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1642;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f1641;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1640;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1643;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs70, %rs71, %rs72, %rs73};
|
|
bra.uni $L__BB0_155;
|
|
|
|
$L__BB0_154:
|
|
mov.f32 %f1647, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f1647;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f534;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f533;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f532;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs78, %rs79, %rs80, %rs81};
|
|
|
|
$L__BB0_155:
|
|
mul.f32 %f535, %f508, 0f3FB8EBD1;
|
|
mul.f32 %f536, %f509, 0f3FB8EBD1;
|
|
mul.f32 %f537, %f510, 0f3FB8EBD1;
|
|
ld.const.u64 %rd118, [params+304];
|
|
cvta.to.global.u64 %rd119, %rd118;
|
|
ld.const.u32 %r430, [params+296];
|
|
mad.lo.s32 %r431, %r430, %r7, %r6;
|
|
mul.wide.u32 %rd120, %r431, 8;
|
|
add.s64 %rd27, %rd119, %rd120;
|
|
@%p182 bra $L__BB0_157;
|
|
|
|
ld.global.v4.u16 {%rs89, %rs90, %rs91, %rs92}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1648, %rs89;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1649, %rs90;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1650, %rs91;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1651, %f535, %f1648;
|
|
add.f32 %f1652, %f536, %f1649;
|
|
add.f32 %f1653, %f537, %f1650;
|
|
mov.f32 %f1654, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1653;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1652;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1651;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1654;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs85, %rs86, %rs87, %rs88};
|
|
bra.uni $L__BB0_158;
|
|
|
|
$L__BB0_157:
|
|
mov.f32 %f1658, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f1658;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f537;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f536;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f535;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs93, %rs94, %rs95, %rs96};
|
|
|
|
$L__BB0_158:
|
|
mul.f32 %f538, %f511, 0f404EBF87;
|
|
mul.f32 %f539, %f512, 0f404EBF87;
|
|
mul.f32 %f540, %f513, 0f404EBF87;
|
|
ld.const.u64 %rd121, [params+320];
|
|
cvta.to.global.u64 %rd122, %rd121;
|
|
ld.const.u32 %r432, [params+312];
|
|
mad.lo.s32 %r433, %r432, %r7, %r6;
|
|
mul.wide.u32 %rd123, %r433, 8;
|
|
add.s64 %rd28, %rd122, %rd123;
|
|
@%p182 bra $L__BB0_160;
|
|
|
|
ld.global.v4.u16 {%rs104, %rs105, %rs106, %rs107}, [%rd28];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1659, %rs104;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1660, %rs105;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1661, %rs106;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1662, %f538, %f1659;
|
|
add.f32 %f1663, %f539, %f1660;
|
|
add.f32 %f1664, %f540, %f1661;
|
|
mov.f32 %f1665, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs102, %f1664;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs101, %f1663;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs100, %f1662;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs103, %f1665;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd28], {%rs100, %rs101, %rs102, %rs103};
|
|
bra.uni $L__BB0_161;
|
|
|
|
$L__BB0_160:
|
|
mov.f32 %f1669, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs111, %f1669;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs110, %f540;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs109, %f539;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f538;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd28], {%rs108, %rs109, %rs110, %rs111};
|
|
|
|
$L__BB0_161:
|
|
mul.f32 %f541, %f514, 0f404EBF87;
|
|
mul.f32 %f542, %f515, 0f404EBF87;
|
|
mul.f32 %f543, %f516, 0f404EBF87;
|
|
ld.const.u64 %rd124, [params+336];
|
|
cvta.to.global.u64 %rd125, %rd124;
|
|
ld.const.u32 %r434, [params+328];
|
|
mad.lo.s32 %r435, %r434, %r7, %r6;
|
|
mul.wide.u32 %rd126, %r435, 8;
|
|
add.s64 %rd29, %rd125, %rd126;
|
|
@%p182 bra $L__BB0_163;
|
|
|
|
ld.global.v4.u16 {%rs119, %rs120, %rs121, %rs122}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1670, %rs119;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1671, %rs120;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1672, %rs121;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1673, %f541, %f1670;
|
|
add.f32 %f1674, %f542, %f1671;
|
|
add.f32 %f1675, %f543, %f1672;
|
|
mov.f32 %f1676, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs117, %f1675;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs116, %f1674;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1673;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs118, %f1676;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd29], {%rs115, %rs116, %rs117, %rs118};
|
|
bra.uni $L__BB0_164;
|
|
|
|
$L__BB0_163:
|
|
mov.f32 %f1680, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs126, %f1680;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs125, %f543;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs124, %f542;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f541;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd29], {%rs123, %rs124, %rs125, %rs126};
|
|
|
|
$L__BB0_164:
|
|
mul.f32 %f544, %f517, 0f40330C94;
|
|
mul.f32 %f545, %f518, 0f40330C94;
|
|
mul.f32 %f546, %f519, 0f40330C94;
|
|
ld.const.u64 %rd127, [params+352];
|
|
cvta.to.global.u64 %rd128, %rd127;
|
|
ld.const.u32 %r436, [params+344];
|
|
mad.lo.s32 %r437, %r436, %r7, %r6;
|
|
mul.wide.u32 %rd129, %r437, 8;
|
|
add.s64 %rd30, %rd128, %rd129;
|
|
@%p182 bra $L__BB0_166;
|
|
|
|
ld.global.v4.u16 {%rs134, %rs135, %rs136, %rs137}, [%rd30];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1681, %rs134;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1682, %rs135;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1683, %rs136;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1684, %f544, %f1681;
|
|
add.f32 %f1685, %f545, %f1682;
|
|
add.f32 %f1686, %f546, %f1683;
|
|
mov.f32 %f1687, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs132, %f1686;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs131, %f1685;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1684;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs133, %f1687;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd30], {%rs130, %rs131, %rs132, %rs133};
|
|
bra.uni $L__BB0_167;
|
|
|
|
$L__BB0_166:
|
|
mov.f32 %f1691, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs141, %f1691;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs140, %f546;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs139, %f545;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f544;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd30], {%rs138, %rs139, %rs140, %rs141};
|
|
|
|
$L__BB0_167:
|
|
mul.f32 %f547, %f520, 0f404EBF87;
|
|
mul.f32 %f548, %f521, 0f404EBF87;
|
|
mul.f32 %f549, %f522, 0f404EBF87;
|
|
ld.const.u64 %rd130, [params+368];
|
|
cvta.to.global.u64 %rd131, %rd130;
|
|
ld.const.u32 %r438, [params+360];
|
|
mad.lo.s32 %r439, %r438, %r7, %r6;
|
|
mul.wide.u32 %rd132, %r439, 8;
|
|
add.s64 %rd31, %rd131, %rd132;
|
|
@%p182 bra $L__BB0_169;
|
|
|
|
ld.global.v4.u16 {%rs149, %rs150, %rs151, %rs152}, [%rd31];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1692, %rs149;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1693, %rs150;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1694, %rs151;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1695, %f547, %f1692;
|
|
add.f32 %f1696, %f548, %f1693;
|
|
add.f32 %f1697, %f549, %f1694;
|
|
mov.f32 %f1698, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs147, %f1697;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs146, %f1696;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1695;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs148, %f1698;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd31], {%rs145, %rs146, %rs147, %rs148};
|
|
bra.uni $L__BB0_170;
|
|
|
|
$L__BB0_169:
|
|
mov.f32 %f1702, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs156, %f1702;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs155, %f549;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs154, %f548;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f547;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd31], {%rs153, %rs154, %rs155, %rs156};
|
|
|
|
$L__BB0_170:
|
|
mul.f32 %f550, %f523, 0f3FCEBF87;
|
|
mul.f32 %f551, %f524, 0f3FCEBF87;
|
|
mul.f32 %f552, %f525, 0f3FCEBF87;
|
|
ld.const.u64 %rd133, [params+384];
|
|
cvta.to.global.u64 %rd134, %rd133;
|
|
ld.const.u32 %r440, [params+376];
|
|
mad.lo.s32 %r441, %r440, %r7, %r6;
|
|
mul.wide.u32 %rd135, %r441, 8;
|
|
add.s64 %rd32, %rd134, %rd135;
|
|
@%p182 bra $L__BB0_172;
|
|
|
|
ld.global.v4.u16 {%rs164, %rs165, %rs166, %rs167}, [%rd32];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1703, %rs164;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1704, %rs165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1705, %rs166;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1706, %f550, %f1703;
|
|
add.f32 %f1707, %f551, %f1704;
|
|
add.f32 %f1708, %f552, %f1705;
|
|
mov.f32 %f1709, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs162, %f1708;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs161, %f1707;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1706;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs163, %f1709;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd32], {%rs160, %rs161, %rs162, %rs163};
|
|
bra.uni $L__BB0_208;
|
|
|
|
$L__BB0_172:
|
|
mov.f32 %f1713, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs171, %f1713;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs170, %f552;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs169, %f551;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs168, %f550;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd32], {%rs168, %rs169, %rs170, %rs171};
|
|
|
|
$L__BB0_208:
|
|
ret;
|
|
|
|
}
|
|
|