114 lines
2.4 KiB
Plaintext
114 lines
2.4 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl oxMain
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.const .align 16 .b8 params[1184];
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.visible .entry oxMain()
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{
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.reg .pred %p<2>;
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.reg .b16 %rs<13>;
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.reg .f32 %f<13>;
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.reg .b32 %r<15>;
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.reg .b64 %rd<13>;
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mov.u32 %r1, %ctaid.x;
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mov.u32 %r2, %ntid.x;
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mov.u32 %r3, %tid.x;
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mad.lo.s32 %r4, %r1, %r2, %r3;
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mov.u32 %r5, %ctaid.y;
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mov.u32 %r6, %ntid.y;
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mov.u32 %r7, %tid.y;
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mad.lo.s32 %r8, %r5, %r6, %r7;
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ld.const.u64 %rd1, [params+144];
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cvta.to.global.u64 %rd2, %rd1;
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ld.const.u32 %r9, [params+136];
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mad.lo.s32 %r10, %r9, %r8, %r4;
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mul.wide.u32 %rd3, %r10, 8;
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add.s64 %rd4, %rd2, %rd3;
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ld.global.u16 %rs1, [%rd4];
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// begin inline asm
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{ cvt.f32.f16 %f1, %rs1;}
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// end inline asm
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ld.global.u16 %rs2, [%rd4+2];
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// begin inline asm
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{ cvt.f32.f16 %f2, %rs2;}
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// end inline asm
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ld.global.u16 %rs3, [%rd4+4];
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// begin inline asm
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{ cvt.f32.f16 %f3, %rs3;}
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// end inline asm
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ld.const.u64 %rd5, [params+160];
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cvta.to.global.u64 %rd6, %rd5;
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ld.const.u32 %r11, [params+152];
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mad.lo.s32 %r12, %r11, %r8, %r4;
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mul.wide.u32 %rd7, %r12, 8;
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add.s64 %rd8, %rd6, %rd7;
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ld.global.u16 %rs4, [%rd8];
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// begin inline asm
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{ cvt.f32.f16 %f4, %rs4;}
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// end inline asm
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ld.global.u16 %rs5, [%rd8+2];
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// begin inline asm
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{ cvt.f32.f16 %f5, %rs5;}
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// end inline asm
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ld.global.u16 %rs6, [%rd8+4];
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// begin inline asm
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{ cvt.f32.f16 %f6, %rs6;}
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// end inline asm
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ld.global.u16 %rs7, [%rd8+6];
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// begin inline asm
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{ cvt.f32.f16 %f7, %rs7;}
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// end inline asm
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ld.const.u64 %rd9, [params+176];
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cvta.to.global.u64 %rd10, %rd9;
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ld.const.u32 %r13, [params+168];
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mad.lo.s32 %r14, %r13, %r8, %r4;
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mul.wide.u32 %rd11, %r14, 4;
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add.s64 %rd12, %rd10, %rd11;
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ld.global.u8 %rs12, [%rd12+3];
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setp.eq.s16 %p1, %rs12, 0;
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selp.f32 %f12, 0f00000000, 0f3F800000, %p1;
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max.f32 %f11, %f12, %f7;
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fma.rn.f32 %f8, %f1, %f12, %f4;
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fma.rn.f32 %f9, %f2, %f12, %f5;
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fma.rn.f32 %f10, %f3, %f12, %f6;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs10, %f10;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs9, %f9;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs8, %f8;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs11, %f11;}
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// end inline asm
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st.global.v4.u16 [%rd8], {%rs8, %rs9, %rs10, %rs11};
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ret;
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}
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