141 lines
2.8 KiB
Plaintext
141 lines
2.8 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-23083092
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// Cuda compilation tools, release 9.1, V9.1.85
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// Based on LLVM 3.4svn
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//
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.version 6.1
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.target sm_52
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.address_size 64
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// .globl oxMain
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.const .align 16 .b8 params[1184];
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.visible .entry oxMain(
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)
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{
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.reg .b16 %rs<31>;
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.reg .f32 %f<20>;
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.reg .b32 %r<15>;
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.reg .b64 %rd<13>;
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mov.u32 %r1, %ctaid.x;
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mov.u32 %r2, %ntid.x;
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mov.u32 %r3, %tid.x;
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mad.lo.s32 %r4, %r2, %r1, %r3;
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mov.u32 %r5, %ctaid.y;
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mov.u32 %r6, %ntid.y;
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mov.u32 %r7, %tid.y;
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mad.lo.s32 %r8, %r6, %r5, %r7;
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ld.const.u64 %rd1, [params+144];
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cvta.to.global.u64 %rd2, %rd1;
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ld.const.u32 %r9, [params+136];
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mad.lo.s32 %r10, %r9, %r8, %r4;
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mul.wide.u32 %rd3, %r10, 8;
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add.s64 %rd4, %rd2, %rd3;
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ld.global.v4.u16 {%rs19, %rs20, %rs21, %rs22}, [%rd4];
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// inline asm
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{ cvt.f32.f16 %f1, %rs22;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f2, %rs19;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f3, %rs20;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f4, %rs21;}
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// inline asm
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ld.const.u64 %rd5, [params+160];
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cvta.to.global.u64 %rd6, %rd5;
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ld.const.u32 %r11, [params+152];
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mad.lo.s32 %r12, %r11, %r8, %r4;
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mul.wide.u32 %rd7, %r12, 8;
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add.s64 %rd8, %rd6, %rd7;
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ld.global.v4.u16 {%rs23, %rs24, %rs25, %rs26}, [%rd8];
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// inline asm
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{ cvt.f32.f16 %f5, %rs26;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f6, %rs23;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f7, %rs24;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f8, %rs25;}
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// inline asm
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add.f32 %f9, %f2, %f6;
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add.f32 %f10, %f3, %f7;
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add.f32 %f11, %f4, %f8;
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min.f32 %f12, %f1, %f5;
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// inline asm
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{ cvt.rn.f16.f32 %rs12, %f12;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs11, %f11;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs10, %f10;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs9, %f9;}
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// inline asm
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st.global.v4.u16 [%rd8], {%rs9, %rs10, %rs11, %rs12};
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ld.const.u64 %rd9, [params+744];
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cvta.to.global.u64 %rd10, %rd9;
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ld.const.u32 %r13, [params+736];
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mad.lo.s32 %r14, %r13, %r8, %r4;
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mul.wide.u32 %rd11, %r14, 8;
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add.s64 %rd12, %rd10, %rd11;
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ld.global.v4.u16 {%rs27, %rs28, %rs29, %rs30}, [%rd12];
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// inline asm
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{ cvt.f32.f16 %f13, %rs27;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f14, %rs28;}
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// inline asm
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// inline asm
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{ cvt.f32.f16 %f15, %rs29;}
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// inline asm
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ld.const.f32 %f19, [params+752];
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fma.rn.f32 %f16, %f2, %f19, %f13;
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fma.rn.f32 %f17, %f3, %f19, %f14;
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fma.rn.f32 %f18, %f4, %f19, %f15;
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// inline asm
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{ cvt.rn.f16.f32 %rs18, %f18;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs17, %f17;}
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// inline asm
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// inline asm
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{ cvt.rn.f16.f32 %rs16, %f16;}
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// inline asm
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st.global.v4.u16 [%rd12], {%rs16, %rs17, %rs18, %rs12};
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ret;
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}
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