2245 lines
60 KiB
Plaintext
2245 lines
60 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<155>;
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.reg .b16 %rs<166>;
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.reg .f32 %f<1164>;
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.reg .b32 %r<364>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<122>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r53), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r54), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+540];
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shl.b32 %r4, %r3, 1;
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ld.const.u64 %rd27, [params+400];
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cvta.to.global.u64 %rd28, %rd27;
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ld.const.u32 %r59, [params+392];
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mad.lo.s32 %r60, %r59, %r54, %r53;
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mul.wide.u32 %rd29, %r60, 4;
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add.s64 %rd2, %rd28, %rd29;
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ld.global.v2.u8 {%rs7, %rs165}, [%rd2];
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or.b16 %rs9, %rs7, %rs165;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p7, %rs10, 0;
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@%p7 bra $L__BB0_2;
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ld.global.u8 %rs164, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs164, [%rd2+2];
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setp.eq.s16 %p8, %rs164, 0;
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mov.f32 %f1089, 0f00000000;
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mov.u16 %rs165, 0;
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mov.f32 %f1090, %f1089;
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mov.f32 %f1091, %f1089;
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@%p8 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f228, %rs7;
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div.rn.f32 %f229, %f228, 0f437F0000;
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fma.rn.f32 %f230, %f229, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs165, 255;
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cvt.rn.f32.u16 %f231, %rs13;
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div.rn.f32 %f232, %f231, 0f437F0000;
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fma.rn.f32 %f233, %f232, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f234, %rs164;
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div.rn.f32 %f235, %f234, 0f437F0000;
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fma.rn.f32 %f236, %f235, 0f40000000, 0fBF800000;
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mul.f32 %f237, %f233, %f233;
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fma.rn.f32 %f238, %f230, %f230, %f237;
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fma.rn.f32 %f239, %f236, %f236, %f238;
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sqrt.rn.f32 %f240, %f239;
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rcp.rn.f32 %f241, %f240;
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mul.f32 %f1091, %f241, %f236;
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mul.f32 %f1090, %f241, %f233;
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mul.f32 %f1089, %f230, %f241;
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$L__BB0_4:
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ld.const.v2.u32 {%r61, %r62}, [params];
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add.s32 %r5, %r61, %r53;
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add.s32 %r6, %r62, %r54;
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setp.eq.f32 %p9, %f1089, 0f00000000;
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setp.eq.f32 %p10, %f1090, 0f00000000;
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and.pred %p11, %p9, %p10;
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setp.eq.f32 %p12, %f1091, 0f00000000;
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and.pred %p13, %p12, %p11;
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@%p13 bra $L__BB0_128;
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bra.uni $L__BB0_5;
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$L__BB0_128:
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ld.const.u32 %r51, [params+104];
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and.b32 %r316, %r51, 1;
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setp.eq.b32 %p144, %r316, 1;
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mov.pred %p145, 0;
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xor.pred %p146, %p144, %p145;
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not.pred %p147, %p146;
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@%p147 bra $L__BB0_130;
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ld.const.u64 %rd90, [params+144];
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cvta.to.global.u64 %rd91, %rd90;
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ld.const.u32 %r317, [params+136];
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mad.lo.s32 %r318, %r317, %r6, %r5;
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mul.wide.u32 %rd92, %r318, 4;
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add.s64 %rd93, %rd91, %rd92;
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mov.u16 %rs95, 0;
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st.global.v4.u8 [%rd93], {%rs95, %rs95, %rs95, %rs95};
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$L__BB0_130:
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and.b32 %r319, %r51, 4;
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setp.eq.s32 %p148, %r319, 0;
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@%p148 bra $L__BB0_132;
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ld.const.u64 %rd94, [params+224];
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cvta.to.global.u64 %rd95, %rd94;
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ld.const.u32 %r320, [params+216];
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mad.lo.s32 %r321, %r320, %r6, %r5;
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mov.f32 %f1019, 0f00000000;
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mul.wide.u32 %rd96, %r321, 8;
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add.s64 %rd97, %rd95, %rd96;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs98, %f1019;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs97, %f1019;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs96, %f1019;}
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// end inline asm
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mov.u16 %rs99, 0;
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st.global.v4.u16 [%rd97], {%rs96, %rs97, %rs98, %rs99};
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$L__BB0_132:
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and.b32 %r322, %r51, 16;
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setp.eq.s32 %p149, %r322, 0;
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@%p149 bra $L__BB0_134;
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ld.const.u64 %rd98, [params+240];
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cvta.to.global.u64 %rd99, %rd98;
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ld.const.u32 %r323, [params+232];
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mad.lo.s32 %r324, %r323, %r6, %r5;
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mov.f32 %f1022, 0f00000000;
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mul.wide.u32 %rd100, %r324, 8;
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add.s64 %rd101, %rd99, %rd100;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs102, %f1022;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs101, %f1022;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs100, %f1022;}
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// end inline asm
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mov.u16 %rs103, 0;
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st.global.v4.u16 [%rd101], {%rs100, %rs101, %rs102, %rs103};
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$L__BB0_134:
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ld.const.u32 %r52, [params+108];
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setp.eq.s32 %p150, %r52, 0;
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ld.const.u64 %rd102, [params+256];
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cvta.to.global.u64 %rd103, %rd102;
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ld.const.u32 %r325, [params+248];
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mad.lo.s32 %r326, %r325, %r6, %r5;
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mul.wide.u32 %rd104, %r326, 8;
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add.s64 %rd22, %rd103, %rd104;
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@%p150 bra $L__BB0_136;
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ld.global.v4.u16 {%rs110, %rs111, %rs112, %rs113}, [%rd22];
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// begin inline asm
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{ cvt.f32.f16 %f1023, %rs110;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1024, %rs111;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1025, %rs112;}
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// end inline asm
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add.f32 %f1026, %f1023, 0f00000000;
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add.f32 %f1027, %f1024, 0f00000000;
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add.f32 %f1028, %f1025, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs109, %f1028;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs108, %f1027;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs107, %f1026;}
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// end inline asm
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mov.u16 %rs114, 0;
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st.global.v4.u16 [%rd22], {%rs107, %rs108, %rs109, %rs114};
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bra.uni $L__BB0_137;
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$L__BB0_5:
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ld.const.u64 %rd30, [params+496];
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cvta.to.global.u64 %rd31, %rd30;
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ld.const.u32 %r65, [params+488];
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mad.lo.s32 %r66, %r65, %r54, %r53;
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mul.wide.u32 %rd32, %r66, 8;
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add.s64 %rd33, %rd31, %rd32;
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ld.global.v4.u16 {%rs19, %rs20, %rs21, %rs22}, [%rd33];
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// begin inline asm
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{ cvt.f32.f16 %f242, %rs19;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f243, %rs20;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f244, %rs21;}
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// end inline asm
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ld.const.u64 %rd34, [params+432];
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cvta.to.global.u64 %rd35, %rd34;
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ld.const.u32 %r67, [params+424];
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mad.lo.s32 %r68, %r67, %r54, %r53;
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mul.wide.u32 %rd36, %r68, 12;
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add.s64 %rd37, %rd35, %rd36;
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ld.global.f32 %f261, [%rd37];
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mul.f32 %f262, %f261, 0f3456BF95;
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ld.global.f32 %f263, [%rd37+4];
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mul.f32 %f264, %f263, 0f3456BF95;
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ld.global.f32 %f265, [%rd37+8];
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mul.f32 %f266, %f265, 0f3456BF95;
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abs.f32 %f267, %f1089;
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div.rn.f32 %f268, %f262, %f267;
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abs.f32 %f269, %f1090;
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div.rn.f32 %f270, %f264, %f269;
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abs.f32 %f271, %f1091;
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div.rn.f32 %f272, %f266, %f271;
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abs.f32 %f273, %f268;
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abs.f32 %f274, %f270;
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abs.f32 %f275, %f272;
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mov.f32 %f276, 0f38D1B717;
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max.f32 %f277, %f273, %f276;
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max.f32 %f278, %f274, %f276;
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max.f32 %f279, %f275, %f276;
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fma.rn.f32 %f13, %f1089, %f277, %f261;
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fma.rn.f32 %f14, %f1090, %f278, %f263;
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fma.rn.f32 %f15, %f1091, %f279, %f265;
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setp.gt.f32 %p14, %f267, %f271;
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neg.f32 %f280, %f1090;
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selp.f32 %f281, %f280, 0f00000000, %p14;
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mov.f32 %f1121, 0f00000000;
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neg.f32 %f282, %f1091;
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selp.f32 %f283, %f1089, %f282, %p14;
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selp.f32 %f284, 0f00000000, %f1090, %p14;
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mul.f32 %f285, %f283, %f283;
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fma.rn.f32 %f286, %f281, %f281, %f285;
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fma.rn.f32 %f287, %f284, %f284, %f286;
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sqrt.rn.f32 %f288, %f287;
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rcp.rn.f32 %f289, %f288;
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mul.f32 %f16, %f281, %f289;
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mul.f32 %f17, %f283, %f289;
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mul.f32 %f18, %f284, %f289;
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ld.const.u64 %rd38, [params+128];
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cvta.to.global.u64 %rd39, %rd38;
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ld.const.u32 %r69, [params+120];
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mad.lo.s32 %r70, %r69, %r54, %r53;
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mul.wide.u32 %rd40, %r70, 4;
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add.s64 %rd3, %rd39, %rd40;
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setp.lt.s32 %p15, %r3, 1;
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mov.f32 %f1120, %f1121;
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mov.f32 %f1119, %f1121;
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mov.f32 %f1118, %f1121;
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mov.f32 %f1117, %f1121;
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mov.f32 %f1116, %f1121;
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mov.f32 %f1115, %f1121;
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mov.f32 %f1114, %f1121;
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mov.f32 %f1113, %f1121;
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mov.f32 %f1112, %f1121;
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mov.f32 %f1111, %f1121;
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mov.f32 %f1110, %f1121;
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mov.f32 %f1109, %f1121;
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mov.f32 %f1108, %f1121;
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mov.f32 %f1107, %f1121;
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@%p15 bra $L__BB0_34;
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cvt.rn.f32.s32 %f305, %r4;
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rcp.rn.f32 %f19, %f305;
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ld.global.u32 %r356, [%rd3];
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mul.f32 %f20, %f13, 0f3456BF95;
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mul.f32 %f21, %f14, 0f3456BF95;
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mul.f32 %f22, %f15, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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mul.f32 %f306, %f1089, %f17;
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mul.f32 %f307, %f1090, %f16;
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sub.f32 %f23, %f307, %f306;
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mul.f32 %f308, %f1091, %f16;
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mul.f32 %f309, %f1089, %f18;
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sub.f32 %f24, %f309, %f308;
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mul.f32 %f310, %f1090, %f18;
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mul.f32 %f311, %f1091, %f17;
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sub.f32 %f25, %f311, %f310;
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mov.u32 %r71, 0;
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add.s64 %rd5, %rd1, 24;
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mov.u64 %rd41, __cudart_i2opi_f;
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abs.f32 %f376, %f21;
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abs.f32 %f377, %f20;
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max.f32 %f378, %f377, %f376;
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abs.f32 %f379, %f22;
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max.f32 %f380, %f378, %f379;
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mov.u32 %r353, %r71;
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$L__BB0_7:
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mov.u32 %r355, %r71;
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$L__BB0_8:
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cvt.rn.f32.s32 %f1065, %r353;
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mad.lo.s32 %r73, %r356, 1664525, 1013904223;
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and.b32 %r74, %r73, 16777215;
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cvt.rn.f32.u32 %f312, %r74;
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fma.rn.f32 %f313, %f312, 0f33800000, %f1065;
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mul.f32 %f314, %f19, %f313;
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mad.lo.s32 %r356, %r73, 1664525, 1013904223;
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and.b32 %r75, %r356, 16777215;
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cvt.rn.f32.u32 %f315, %r75;
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cvt.rn.f32.s32 %f316, %r355;
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fma.rn.f32 %f317, %f315, 0f33800000, %f316;
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mul.f32 %f318, %f19, %f317;
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fma.rn.f32 %f319, %f19, %f313, %f314;
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mov.f32 %f320, 0f3F800000;
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sub.f32 %f57, %f320, %f319;
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mul.f32 %f321, %f57, %f57;
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sub.f32 %f322, %f320, %f321;
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mov.f32 %f323, 0f00000000;
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max.f32 %f324, %f323, %f322;
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sqrt.rn.f32 %f58, %f324;
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mul.f32 %f59, %f318, 0f40C90FDB;
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mul.f32 %f325, %f59, 0f3F22F983;
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cvt.rni.s32.f32 %r360, %f325;
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cvt.rn.f32.s32 %f326, %r360;
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mov.f32 %f327, 0fBFC90FDA;
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fma.rn.f32 %f328, %f326, %f327, %f59;
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mov.f32 %f329, 0fB3A22168;
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fma.rn.f32 %f330, %f326, %f329, %f328;
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mov.f32 %f331, 0fA7C234C5;
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fma.rn.f32 %f1125, %f326, %f331, %f330;
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abs.f32 %f61, %f59;
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setp.ltu.f32 %p16, %f61, 0f47CE4780;
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mov.f32 %f1122, %f1125;
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@%p16 bra $L__BB0_16;
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setp.eq.f32 %p17, %f61, 0f7F800000;
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@%p17 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f334, 0f00000000;
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mul.rn.f32 %f1122, %f59, %f334;
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mov.u32 %r360, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r14, %f59;
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bfe.u32 %r77, %r14, 23, 8;
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mov.u64 %rd119, 0;
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mov.u32 %r357, 0;
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mov.u64 %rd117, %rd1;
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mov.u64 %rd118, %rd41;
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$L__BB0_11:
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.pragma "nounroll";
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mov.b32 %r336, %f59;
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shl.b32 %r335, %r336, 8;
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or.b32 %r334, %r335, -2147483648;
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ld.global.nc.u32 %r79, [%rd118];
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mad.wide.u32 %rd43, %r79, %r334, %rd119;
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|
shr.u64 %rd119, %rd43, 32;
|
|
st.local.u32 [%rd117], %rd43;
|
|
add.s64 %rd118, %rd118, 4;
|
|
add.s64 %rd117, %rd117, 4;
|
|
add.s32 %r357, %r357, 1;
|
|
setp.ne.s32 %p18, %r357, 6;
|
|
@%p18 bra $L__BB0_11;
|
|
|
|
add.s32 %r341, %r77, -128;
|
|
mov.b32 %r340, %f59;
|
|
bfe.u32 %r339, %r340, 23, 8;
|
|
add.s32 %r338, %r339, -128;
|
|
shr.u32 %r337, %r338, 5;
|
|
st.local.u32 [%rd5], %rd119;
|
|
mov.u32 %r81, 6;
|
|
sub.s32 %r82, %r81, %r337;
|
|
mul.wide.s32 %rd44, %r82, 4;
|
|
add.s64 %rd45, %rd1, %rd44;
|
|
ld.local.u32 %r358, [%rd45];
|
|
ld.local.u32 %r359, [%rd45+-4];
|
|
and.b32 %r23, %r338, 31;
|
|
setp.eq.s32 %p19, %r23, 0;
|
|
@%p19 bra $L__BB0_14;
|
|
|
|
mov.b32 %r348, %f59;
|
|
bfe.u32 %r347, %r348, 23, 8;
|
|
add.s32 %r346, %r347, -128;
|
|
shr.u32 %r345, %r346, 5;
|
|
mov.u32 %r344, 4;
|
|
sub.s32 %r343, %r344, %r345;
|
|
mov.u32 %r83, 32;
|
|
sub.s32 %r84, %r83, %r23;
|
|
shr.u32 %r85, %r359, %r84;
|
|
shl.b32 %r86, %r358, %r23;
|
|
add.s32 %r358, %r85, %r86;
|
|
mul.wide.s32 %rd46, %r343, 4;
|
|
add.s64 %rd47, %rd1, %rd46;
|
|
ld.local.u32 %r87, [%rd47];
|
|
shr.u32 %r88, %r87, %r84;
|
|
shl.b32 %r89, %r359, %r23;
|
|
add.s32 %r359, %r88, %r89;
|
|
|
|
$L__BB0_14:
|
|
mov.b32 %r342, %f59;
|
|
and.b32 %r90, %r342, -2147483648;
|
|
shr.u32 %r91, %r359, 30;
|
|
shl.b32 %r92, %r358, 2;
|
|
or.b32 %r93, %r91, %r92;
|
|
shr.u32 %r94, %r93, 31;
|
|
shr.u32 %r95, %r358, 30;
|
|
add.s32 %r96, %r94, %r95;
|
|
neg.s32 %r97, %r96;
|
|
setp.eq.s32 %p20, %r90, 0;
|
|
selp.b32 %r360, %r96, %r97, %p20;
|
|
setp.ne.s32 %p21, %r94, 0;
|
|
xor.b32 %r98, %r90, -2147483648;
|
|
selp.b32 %r99, %r98, %r90, %p21;
|
|
selp.b32 %r100, -1, 0, %p21;
|
|
xor.b32 %r101, %r93, %r100;
|
|
shl.b32 %r102, %r359, 2;
|
|
xor.b32 %r103, %r102, %r100;
|
|
cvt.u64.u32 %rd48, %r101;
|
|
cvt.u64.u32 %rd49, %r103;
|
|
bfi.b64 %rd50, %rd48, %rd49, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd50;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f332, %fd2;
|
|
setp.eq.s32 %p22, %r99, 0;
|
|
neg.f32 %f333, %f332;
|
|
selp.f32 %f1122, %f332, %f333, %p22;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r30, %r360, 1;
|
|
and.b32 %r31, %r30, 1;
|
|
setp.eq.s32 %p23, %r31, 0;
|
|
selp.f32 %f65, %f1122, 0f3F800000, %p23;
|
|
mul.rn.f32 %f66, %f1122, %f1122;
|
|
mov.f32 %f1123, 0fB94D4153;
|
|
@%p23 bra $L__BB0_18;
|
|
|
|
mov.f32 %f336, 0fBAB607ED;
|
|
mov.f32 %f337, 0f37CBAC00;
|
|
fma.rn.f32 %f1123, %f337, %f66, %f336;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f338, 0f3C0885E4, 0f3D2AAABB, %p23;
|
|
fma.rn.f32 %f339, %f1123, %f66, %f338;
|
|
selp.f32 %f340, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
|
|
fma.rn.f32 %f341, %f339, %f66, %f340;
|
|
mov.f32 %f342, 0f00000000;
|
|
fma.rn.f32 %f343, %f66, %f65, %f342;
|
|
fma.rn.f32 %f1124, %f341, %f343, %f65;
|
|
and.b32 %r105, %r30, 2;
|
|
setp.eq.s32 %p25, %r105, 0;
|
|
@%p25 bra $L__BB0_20;
|
|
|
|
mov.f32 %f345, 0fBF800000;
|
|
fma.rn.f32 %f1124, %f1124, %f345, %f342;
|
|
|
|
$L__BB0_20:
|
|
mul.f32 %f1066, %f59, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r363, %f1066;
|
|
setp.ltu.f32 %p154, %f61, 0f47CE4780;
|
|
@%p154 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p27, %f61, 0f7F800000;
|
|
@%p27 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f348, 0f00000000;
|
|
mul.rn.f32 %f1125, %f59, %f348;
|
|
mov.u32 %r363, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r32, %f59;
|
|
bfe.u32 %r106, %r32, 23, 8;
|
|
add.s32 %r33, %r106, -128;
|
|
shl.b32 %r107, %r32, 8;
|
|
or.b32 %r34, %r107, -2147483648;
|
|
shr.u32 %r35, %r33, 5;
|
|
mov.u64 %rd120, 0;
|
|
mov.u64 %rd121, %rd120;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd53, %rd120, 2;
|
|
mov.u64 %rd54, __cudart_i2opi_f;
|
|
add.s64 %rd55, %rd54, %rd53;
|
|
ld.global.nc.u32 %r108, [%rd55];
|
|
mad.wide.u32 %rd56, %r108, %r34, %rd121;
|
|
shr.u64 %rd121, %rd56, 32;
|
|
add.s64 %rd57, %rd1, %rd53;
|
|
st.local.u32 [%rd57], %rd56;
|
|
cvt.u32.u64 %r109, %rd120;
|
|
add.s32 %r110, %r109, 1;
|
|
cvt.s64.s32 %rd120, %r110;
|
|
setp.ne.s32 %p28, %r110, 6;
|
|
@%p28 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd5], %rd121;
|
|
mov.u32 %r111, 4;
|
|
sub.s32 %r36, %r111, %r35;
|
|
mov.u32 %r112, 6;
|
|
sub.s32 %r113, %r112, %r35;
|
|
mul.wide.s32 %rd58, %r113, 4;
|
|
add.s64 %rd59, %rd1, %rd58;
|
|
ld.local.u32 %r361, [%rd59];
|
|
ld.local.u32 %r362, [%rd59+-4];
|
|
and.b32 %r39, %r33, 31;
|
|
setp.eq.s32 %p29, %r39, 0;
|
|
@%p29 bra $L__BB0_26;
|
|
|
|
mov.u32 %r114, 32;
|
|
sub.s32 %r115, %r114, %r39;
|
|
shr.u32 %r116, %r362, %r115;
|
|
shl.b32 %r117, %r361, %r39;
|
|
add.s32 %r361, %r116, %r117;
|
|
mul.wide.s32 %rd60, %r36, 4;
|
|
add.s64 %rd61, %rd1, %rd60;
|
|
ld.local.u32 %r118, [%rd61];
|
|
shr.u32 %r119, %r118, %r115;
|
|
shl.b32 %r120, %r362, %r39;
|
|
add.s32 %r362, %r119, %r120;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r121, %r32, -2147483648;
|
|
shr.u32 %r122, %r362, 30;
|
|
shl.b32 %r123, %r361, 2;
|
|
or.b32 %r124, %r122, %r123;
|
|
shr.u32 %r125, %r124, 31;
|
|
shr.u32 %r126, %r361, 30;
|
|
add.s32 %r127, %r125, %r126;
|
|
neg.s32 %r128, %r127;
|
|
setp.eq.s32 %p30, %r121, 0;
|
|
selp.b32 %r363, %r127, %r128, %p30;
|
|
setp.ne.s32 %p31, %r125, 0;
|
|
xor.b32 %r129, %r121, -2147483648;
|
|
selp.b32 %r130, %r129, %r121, %p31;
|
|
selp.b32 %r131, -1, 0, %p31;
|
|
xor.b32 %r132, %r124, %r131;
|
|
shl.b32 %r133, %r362, 2;
|
|
xor.b32 %r134, %r133, %r131;
|
|
cvt.u64.u32 %rd62, %r132;
|
|
cvt.u64.u32 %rd63, %r134;
|
|
bfi.b64 %rd64, %rd62, %rd63, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd64;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f346, %fd4;
|
|
setp.eq.s32 %p32, %r130, 0;
|
|
neg.f32 %f347, %f346;
|
|
selp.f32 %f1125, %f346, %f347, %p32;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f75, %f58, %f1124;
|
|
and.b32 %r46, %r363, 1;
|
|
setp.eq.s32 %p33, %r46, 0;
|
|
mul.rn.f32 %f77, %f1125, %f1125;
|
|
mov.f32 %f1126, 0fB94D4153;
|
|
@%p33 bra $L__BB0_30;
|
|
|
|
mov.f32 %f350, 0fBAB607ED;
|
|
mov.f32 %f351, 0f37CBAC00;
|
|
fma.rn.f32 %f1126, %f351, %f77, %f350;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f1067, %f1125, 0f3F800000, %p33;
|
|
selp.f32 %f352, 0f3C0885E4, 0f3D2AAABB, %p33;
|
|
fma.rn.f32 %f353, %f1126, %f77, %f352;
|
|
selp.f32 %f354, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
|
|
fma.rn.f32 %f355, %f353, %f77, %f354;
|
|
mov.f32 %f356, 0f00000000;
|
|
fma.rn.f32 %f357, %f77, %f1067, %f356;
|
|
fma.rn.f32 %f1127, %f355, %f357, %f1067;
|
|
and.b32 %r136, %r363, 2;
|
|
setp.eq.s32 %p35, %r136, 0;
|
|
@%p35 bra $L__BB0_32;
|
|
|
|
mov.f32 %f359, 0fBF800000;
|
|
fma.rn.f32 %f1127, %f1127, %f359, %f356;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f369, %f58, %f1127;
|
|
mul.f32 %f370, %f16, %f369;
|
|
mul.f32 %f371, %f17, %f369;
|
|
mul.f32 %f372, %f18, %f369;
|
|
fma.rn.f32 %f373, %f25, %f75, %f370;
|
|
fma.rn.f32 %f374, %f24, %f75, %f371;
|
|
fma.rn.f32 %f375, %f23, %f75, %f372;
|
|
fma.rn.f32 %f363, %f1089, %f57, %f373;
|
|
fma.rn.f32 %f364, %f1090, %f57, %f374;
|
|
fma.rn.f32 %f365, %f1091, %f57, %f375;
|
|
mov.f32 %f381, 0f38D1B717;
|
|
max.f32 %f366, %f380, %f381;
|
|
mov.f32 %f367, 0f6C4ECB8F;
|
|
mov.u32 %r170, 1;
|
|
mov.u32 %r173, 2;
|
|
mov.u32 %r175, 3;
|
|
mov.u32 %r207, 0;
|
|
// begin inline asm
|
|
call(%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168),_optix_trace_typed_32,(%r207,%rd4,%f13,%f14,%f15,%f363,%f364,%f365,%f366,%f367,%f356,%r170,%r207,%r207,%r173,%r207,%r175,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207);
|
|
// end inline asm
|
|
mov.b32 %f382, %r137;
|
|
mov.b32 %f383, %r138;
|
|
mov.b32 %f384, %r139;
|
|
mul.f32 %f385, %f1090, %f364;
|
|
fma.rn.f32 %f386, %f1089, %f363, %f385;
|
|
fma.rn.f32 %f387, %f1091, %f365, %f386;
|
|
fma.rn.f32 %f1115, %f363, %f382, %f1115;
|
|
fma.rn.f32 %f1114, %f363, %f383, %f1114;
|
|
fma.rn.f32 %f1113, %f363, %f384, %f1113;
|
|
fma.rn.f32 %f1118, %f364, %f382, %f1118;
|
|
fma.rn.f32 %f1117, %f364, %f383, %f1117;
|
|
fma.rn.f32 %f1116, %f364, %f384, %f1116;
|
|
fma.rn.f32 %f1121, %f365, %f382, %f1121;
|
|
fma.rn.f32 %f1120, %f365, %f383, %f1120;
|
|
fma.rn.f32 %f1119, %f365, %f384, %f1119;
|
|
add.f32 %f1112, %f1112, %f382;
|
|
add.f32 %f1111, %f1111, %f383;
|
|
add.f32 %f1110, %f1110, %f384;
|
|
cvt.sat.f32.f32 %f388, %f387;
|
|
fma.rn.f32 %f1109, %f388, %f382, %f1109;
|
|
fma.rn.f32 %f1108, %f388, %f383, %f1108;
|
|
fma.rn.f32 %f1107, %f388, %f384, %f1107;
|
|
add.s32 %r355, %r355, 1;
|
|
setp.lt.s32 %p36, %r355, %r4;
|
|
@%p36 bra $L__BB0_8;
|
|
|
|
add.s32 %r353, %r353, 1;
|
|
setp.lt.s32 %p37, %r353, %r4;
|
|
@%p37 bra $L__BB0_7;
|
|
|
|
$L__BB0_34:
|
|
mov.f32 %f1143, 0f00000000;
|
|
mul.lo.s32 %r208, %r4, %r4;
|
|
cvt.rn.f32.s32 %f392, %r208;
|
|
rcp.rn.f32 %f393, %f392;
|
|
mul.f32 %f394, %f393, %f1109;
|
|
mul.f32 %f395, %f393, %f1108;
|
|
mul.f32 %f396, %f393, %f1107;
|
|
mul.f32 %f113, %f393, %f1112;
|
|
mul.f32 %f114, %f393, %f1111;
|
|
mul.f32 %f115, %f393, %f1110;
|
|
mul.f32 %f116, %f393, %f1115;
|
|
mul.f32 %f117, %f393, %f1114;
|
|
mul.f32 %f118, %f393, %f1113;
|
|
mul.f32 %f119, %f393, %f1118;
|
|
mul.f32 %f120, %f393, %f1117;
|
|
mul.f32 %f121, %f393, %f1116;
|
|
mul.f32 %f122, %f393, %f1121;
|
|
mul.f32 %f123, %f393, %f1120;
|
|
mul.f32 %f124, %f393, %f1119;
|
|
fma.rn.f32 %f397, %f393, %f1109, %f394;
|
|
fma.rn.f32 %f398, %f393, %f1108, %f395;
|
|
fma.rn.f32 %f399, %f393, %f1107, %f396;
|
|
ld.const.u64 %rd66, [params+504];
|
|
cvt.rn.f32.u32 %f400, %r6;
|
|
cvt.rn.f32.u32 %f401, %r5;
|
|
tex.2d.v4.f32.f32 {%f402, %f403, %f404, %f405}, [%rd66, {%f401, %f400}];
|
|
mul.f32 %f125, %f397, %f402;
|
|
mul.f32 %f126, %f398, %f403;
|
|
mul.f32 %f127, %f399, %f404;
|
|
add.f32 %f128, %f242, %f125;
|
|
add.f32 %f129, %f243, %f126;
|
|
add.f32 %f130, %f244, %f127;
|
|
abs.f32 %f406, %f128;
|
|
setp.gtu.f32 %p38, %f406, 0f7F800000;
|
|
mov.f32 %f1144, %f1143;
|
|
mov.f32 %f1145, %f1143;
|
|
@%p38 bra $L__BB0_38;
|
|
|
|
mov.f32 %f1143, 0f00000000;
|
|
abs.f32 %f410, %f129;
|
|
setp.gtu.f32 %p39, %f410, 0f7F800000;
|
|
@%p39 bra $L__BB0_38;
|
|
|
|
mov.f32 %f1143, 0f00000000;
|
|
abs.f32 %f414, %f130;
|
|
setp.gtu.f32 %p40, %f414, 0f7F800000;
|
|
mov.f32 %f1144, %f1143;
|
|
mov.f32 %f1145, %f1143;
|
|
@%p40 bra $L__BB0_38;
|
|
|
|
mov.f32 %f1143, %f128;
|
|
mov.f32 %f1144, %f129;
|
|
mov.f32 %f1145, %f130;
|
|
|
|
$L__BB0_38:
|
|
ld.const.u32 %r49, [params+104];
|
|
and.b32 %r209, %r49, 1;
|
|
setp.eq.b32 %p41, %r209, 1;
|
|
mov.pred %p42, 0;
|
|
xor.pred %p43, %p41, %p42;
|
|
not.pred %p44, %p43;
|
|
@%p44 bra $L__BB0_112;
|
|
|
|
mov.f32 %f419, 0f3EE66666;
|
|
abs.f32 %f141, %f1143;
|
|
setp.lt.f32 %p45, %f141, 0f00800000;
|
|
mul.f32 %f421, %f141, 0f4B800000;
|
|
selp.f32 %f422, %f421, %f141, %p45;
|
|
selp.f32 %f423, 0fC3170000, 0fC2FE0000, %p45;
|
|
mov.b32 %r210, %f422;
|
|
and.b32 %r211, %r210, 8388607;
|
|
or.b32 %r212, %r211, 1065353216;
|
|
mov.b32 %f424, %r212;
|
|
shr.u32 %r213, %r210, 23;
|
|
cvt.rn.f32.u32 %f425, %r213;
|
|
add.f32 %f426, %f423, %f425;
|
|
setp.gt.f32 %p46, %f424, 0f3FB504F3;
|
|
mul.f32 %f427, %f424, 0f3F000000;
|
|
add.f32 %f428, %f426, 0f3F800000;
|
|
selp.f32 %f429, %f428, %f426, %p46;
|
|
selp.f32 %f430, %f427, %f424, %p46;
|
|
add.f32 %f431, %f430, 0fBF800000;
|
|
add.f32 %f432, %f430, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f433, %f432;
|
|
add.f32 %f434, %f431, %f431;
|
|
mul.f32 %f435, %f434, %f433;
|
|
mul.f32 %f436, %f435, %f435;
|
|
mov.f32 %f437, 0f3C4CAF63;
|
|
mov.f32 %f438, 0f3B18F0FE;
|
|
fma.rn.f32 %f439, %f438, %f436, %f437;
|
|
mov.f32 %f440, 0f3DAAAABD;
|
|
fma.rn.f32 %f441, %f439, %f436, %f440;
|
|
mul.rn.f32 %f442, %f441, %f436;
|
|
mul.rn.f32 %f443, %f442, %f435;
|
|
sub.f32 %f444, %f431, %f435;
|
|
add.f32 %f445, %f444, %f444;
|
|
neg.f32 %f446, %f435;
|
|
fma.rn.f32 %f447, %f446, %f431, %f445;
|
|
mul.rn.f32 %f448, %f433, %f447;
|
|
add.f32 %f449, %f443, %f435;
|
|
sub.f32 %f450, %f435, %f449;
|
|
add.f32 %f451, %f443, %f450;
|
|
add.f32 %f452, %f448, %f451;
|
|
add.f32 %f453, %f449, %f452;
|
|
sub.f32 %f454, %f449, %f453;
|
|
add.f32 %f455, %f452, %f454;
|
|
mov.f32 %f456, 0f3F317200;
|
|
mul.rn.f32 %f457, %f429, %f456;
|
|
mov.f32 %f458, 0f35BFBE8E;
|
|
mul.rn.f32 %f459, %f429, %f458;
|
|
add.f32 %f460, %f457, %f453;
|
|
sub.f32 %f461, %f457, %f460;
|
|
add.f32 %f462, %f453, %f461;
|
|
add.f32 %f463, %f455, %f462;
|
|
add.f32 %f464, %f459, %f463;
|
|
add.f32 %f465, %f460, %f464;
|
|
sub.f32 %f466, %f460, %f465;
|
|
add.f32 %f467, %f464, %f466;
|
|
mul.rn.f32 %f468, %f419, %f465;
|
|
neg.f32 %f469, %f468;
|
|
fma.rn.f32 %f470, %f419, %f465, %f469;
|
|
fma.rn.f32 %f471, %f419, %f467, %f470;
|
|
mov.f32 %f472, 0f00000000;
|
|
fma.rn.f32 %f473, %f472, %f465, %f471;
|
|
add.rn.f32 %f474, %f468, %f473;
|
|
neg.f32 %f475, %f474;
|
|
add.rn.f32 %f476, %f468, %f475;
|
|
add.rn.f32 %f477, %f476, %f473;
|
|
mov.b32 %r214, %f474;
|
|
setp.eq.s32 %p47, %r214, 1118925336;
|
|
add.s32 %r215, %r214, -1;
|
|
mov.b32 %f478, %r215;
|
|
add.f32 %f479, %f477, 0f37000000;
|
|
selp.f32 %f142, %f479, %f477, %p47;
|
|
selp.f32 %f480, %f478, %f474, %p47;
|
|
mov.f32 %f481, 0f3FB8AA3B;
|
|
mul.rn.f32 %f482, %f480, %f481;
|
|
cvt.rzi.f32.f32 %f483, %f482;
|
|
abs.f32 %f484, %f483;
|
|
setp.gt.f32 %p48, %f484, 0f42FC0000;
|
|
mov.b32 %r216, %f483;
|
|
and.b32 %r217, %r216, -2147483648;
|
|
or.b32 %r218, %r217, 1123811328;
|
|
mov.b32 %f485, %r218;
|
|
selp.f32 %f486, %f485, %f483, %p48;
|
|
mov.f32 %f487, 0fBF317218;
|
|
fma.rn.f32 %f488, %f486, %f487, %f480;
|
|
mov.f32 %f489, 0f3102E308;
|
|
fma.rn.f32 %f490, %f486, %f489, %f488;
|
|
mul.f32 %f491, %f490, 0f3FB8AA3B;
|
|
add.f32 %f492, %f486, 0f4B40007F;
|
|
mov.b32 %r219, %f492;
|
|
shl.b32 %r220, %r219, 23;
|
|
mov.b32 %f493, %r220;
|
|
ex2.approx.ftz.f32 %f494, %f491;
|
|
mul.f32 %f143, %f494, %f493;
|
|
setp.eq.f32 %p49, %f143, 0f7F800000;
|
|
mov.f32 %f1146, 0f7F800000;
|
|
@%p49 bra $L__BB0_41;
|
|
|
|
fma.rn.f32 %f1146, %f143, %f142, %f143;
|
|
|
|
$L__BB0_41:
|
|
mov.f32 %f1073, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1072, %f1073;
|
|
add.f32 %f1071, %f1072, %f1072;
|
|
mov.f32 %f1070, 0f3EE66666;
|
|
sub.f32 %f1069, %f1070, %f1071;
|
|
abs.f32 %f1068, %f1069;
|
|
setp.lt.f32 %p50, %f1143, 0f00000000;
|
|
setp.eq.f32 %p51, %f1068, 0f3F800000;
|
|
and.pred %p1, %p50, %p51;
|
|
setp.eq.f32 %p52, %f1143, 0f00000000;
|
|
@%p52 bra $L__BB0_45;
|
|
bra.uni $L__BB0_42;
|
|
|
|
$L__BB0_45:
|
|
add.f32 %f499, %f1143, %f1143;
|
|
selp.f32 %f1148, %f499, 0f00000000, %p51;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_136:
|
|
mov.f32 %f1031, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs117, %f1031;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs116, %f1031;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1031;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs118, 0;
|
|
st.global.v4.u16 [%rd22], {%rs115, %rs116, %rs117, %rs118};
|
|
|
|
$L__BB0_137:
|
|
ld.const.u64 %rd105, [params+272];
|
|
cvta.to.global.u64 %rd106, %rd105;
|
|
ld.const.u32 %r327, [params+264];
|
|
mad.lo.s32 %r328, %r327, %r6, %r5;
|
|
mul.wide.u32 %rd107, %r328, 8;
|
|
add.s64 %rd23, %rd106, %rd107;
|
|
@%p150 bra $L__BB0_139;
|
|
|
|
ld.global.v4.u16 {%rs125, %rs126, %rs127, %rs128}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1032, %rs125;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1033, %rs126;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1034, %rs127;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1035, %f1032, 0f00000000;
|
|
add.f32 %f1036, %f1033, 0f00000000;
|
|
add.f32 %f1037, %f1034, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs124, %f1037;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f1036;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f1035;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs129, 0;
|
|
st.global.v4.u16 [%rd23], {%rs122, %rs123, %rs124, %rs129};
|
|
bra.uni $L__BB0_140;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f1040, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs132, %f1040;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs131, %f1040;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1040;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs133, 0;
|
|
st.global.v4.u16 [%rd23], {%rs130, %rs131, %rs132, %rs133};
|
|
|
|
$L__BB0_140:
|
|
ld.const.u64 %rd108, [params+288];
|
|
cvta.to.global.u64 %rd109, %rd108;
|
|
ld.const.u32 %r329, [params+280];
|
|
mad.lo.s32 %r330, %r329, %r6, %r5;
|
|
mul.wide.u32 %rd110, %r330, 8;
|
|
add.s64 %rd24, %rd109, %rd110;
|
|
@%p150 bra $L__BB0_142;
|
|
|
|
ld.global.v4.u16 {%rs140, %rs141, %rs142, %rs143}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1041, %rs140;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1042, %rs141;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1043, %rs142;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1044, %f1041, 0f00000000;
|
|
add.f32 %f1045, %f1042, 0f00000000;
|
|
add.f32 %f1046, %f1043, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs139, %f1046;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f1045;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f1044;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs144, 0;
|
|
st.global.v4.u16 [%rd24], {%rs137, %rs138, %rs139, %rs144};
|
|
bra.uni $L__BB0_143;
|
|
|
|
$L__BB0_142:
|
|
mov.f32 %f1049, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs147, %f1049;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs146, %f1049;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1049;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs148, 0;
|
|
st.global.v4.u16 [%rd24], {%rs145, %rs146, %rs147, %rs148};
|
|
|
|
$L__BB0_143:
|
|
ld.const.u64 %rd111, [params+304];
|
|
cvta.to.global.u64 %rd112, %rd111;
|
|
ld.const.u32 %r331, [params+296];
|
|
mad.lo.s32 %r332, %r331, %r6, %r5;
|
|
mul.wide.u32 %rd113, %r332, 8;
|
|
add.s64 %rd25, %rd112, %rd113;
|
|
@%p150 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs155, %rs156, %rs157, %rs158}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1050, %rs155;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1051, %rs156;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1052, %rs157;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1053, %f1050, 0f00000000;
|
|
add.f32 %f1054, %f1051, 0f00000000;
|
|
add.f32 %f1055, %f1052, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs154, %f1055;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f1054;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f1053;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs159, 0;
|
|
st.global.v4.u16 [%rd25], {%rs152, %rs153, %rs154, %rs159};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1058, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs162, %f1058;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs161, %f1058;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1058;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs163, 0;
|
|
st.global.v4.u16 [%rd25], {%rs160, %rs161, %rs162, %rs163};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_42:
|
|
mov.b32 %r221, %f1146;
|
|
xor.b32 %r222, %r221, -2147483648;
|
|
mov.b32 %f495, %r222;
|
|
selp.f32 %f1148, %f495, %f1146, %p1;
|
|
setp.geu.f32 %p53, %f1143, 0f00000000;
|
|
@%p53 bra $L__BB0_46;
|
|
|
|
mov.f32 %f496, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f497, %f496;
|
|
setp.eq.f32 %p54, %f497, 0f3EE66666;
|
|
@%p54 bra $L__BB0_46;
|
|
|
|
mov.f32 %f1148, 0f7FFFFFFF;
|
|
|
|
$L__BB0_46:
|
|
abs.f32 %f1074, %f1143;
|
|
add.f32 %f500, %f1074, 0f3EE66666;
|
|
mov.b32 %r223, %f500;
|
|
setp.lt.s32 %p56, %r223, 2139095040;
|
|
@%p56 bra $L__BB0_51;
|
|
|
|
abs.f32 %f1075, %f1143;
|
|
setp.gtu.f32 %p57, %f1075, 0f7F800000;
|
|
@%p57 bra $L__BB0_50;
|
|
bra.uni $L__BB0_48;
|
|
|
|
$L__BB0_50:
|
|
add.f32 %f1148, %f1143, 0f3EE66666;
|
|
bra.uni $L__BB0_51;
|
|
|
|
$L__BB0_48:
|
|
abs.f32 %f1076, %f1143;
|
|
setp.neu.f32 %p58, %f1076, 0f7F800000;
|
|
@%p58 bra $L__BB0_51;
|
|
|
|
selp.f32 %f1148, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_51:
|
|
setp.eq.f32 %p59, %f1143, 0f3F800000;
|
|
selp.f32 %f152, 0f3F800000, %f1148, %p59;
|
|
abs.f32 %f153, %f1144;
|
|
setp.lt.f32 %p60, %f153, 0f00800000;
|
|
mul.f32 %f502, %f153, 0f4B800000;
|
|
selp.f32 %f503, %f502, %f153, %p60;
|
|
selp.f32 %f504, 0fC3170000, 0fC2FE0000, %p60;
|
|
mov.b32 %r224, %f503;
|
|
and.b32 %r225, %r224, 8388607;
|
|
or.b32 %r226, %r225, 1065353216;
|
|
mov.b32 %f505, %r226;
|
|
shr.u32 %r227, %r224, 23;
|
|
cvt.rn.f32.u32 %f506, %r227;
|
|
add.f32 %f507, %f504, %f506;
|
|
setp.gt.f32 %p61, %f505, 0f3FB504F3;
|
|
mul.f32 %f508, %f505, 0f3F000000;
|
|
add.f32 %f509, %f507, 0f3F800000;
|
|
selp.f32 %f510, %f509, %f507, %p61;
|
|
selp.f32 %f511, %f508, %f505, %p61;
|
|
add.f32 %f512, %f511, 0fBF800000;
|
|
add.f32 %f513, %f511, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f514, %f513;
|
|
add.f32 %f515, %f512, %f512;
|
|
mul.f32 %f516, %f515, %f514;
|
|
mul.f32 %f517, %f516, %f516;
|
|
mov.f32 %f518, 0f3C4CAF63;
|
|
mov.f32 %f519, 0f3B18F0FE;
|
|
fma.rn.f32 %f520, %f519, %f517, %f518;
|
|
mov.f32 %f521, 0f3DAAAABD;
|
|
fma.rn.f32 %f522, %f520, %f517, %f521;
|
|
mul.rn.f32 %f523, %f522, %f517;
|
|
mul.rn.f32 %f524, %f523, %f516;
|
|
sub.f32 %f525, %f512, %f516;
|
|
add.f32 %f526, %f525, %f525;
|
|
neg.f32 %f527, %f516;
|
|
fma.rn.f32 %f528, %f527, %f512, %f526;
|
|
mul.rn.f32 %f529, %f514, %f528;
|
|
add.f32 %f530, %f524, %f516;
|
|
sub.f32 %f531, %f516, %f530;
|
|
add.f32 %f532, %f524, %f531;
|
|
add.f32 %f533, %f529, %f532;
|
|
add.f32 %f534, %f530, %f533;
|
|
sub.f32 %f535, %f530, %f534;
|
|
add.f32 %f536, %f533, %f535;
|
|
mov.f32 %f537, 0f3F317200;
|
|
mul.rn.f32 %f538, %f510, %f537;
|
|
mov.f32 %f539, 0f35BFBE8E;
|
|
mul.rn.f32 %f540, %f510, %f539;
|
|
add.f32 %f541, %f538, %f534;
|
|
sub.f32 %f542, %f538, %f541;
|
|
add.f32 %f543, %f534, %f542;
|
|
add.f32 %f544, %f536, %f543;
|
|
add.f32 %f545, %f540, %f544;
|
|
add.f32 %f546, %f541, %f545;
|
|
sub.f32 %f547, %f541, %f546;
|
|
add.f32 %f548, %f545, %f547;
|
|
mov.f32 %f549, 0f3EE66666;
|
|
mul.rn.f32 %f550, %f549, %f546;
|
|
neg.f32 %f551, %f550;
|
|
fma.rn.f32 %f552, %f549, %f546, %f551;
|
|
fma.rn.f32 %f553, %f549, %f548, %f552;
|
|
mov.f32 %f554, 0f00000000;
|
|
fma.rn.f32 %f555, %f554, %f546, %f553;
|
|
add.rn.f32 %f556, %f550, %f555;
|
|
neg.f32 %f557, %f556;
|
|
add.rn.f32 %f558, %f550, %f557;
|
|
add.rn.f32 %f559, %f558, %f555;
|
|
mov.b32 %r228, %f556;
|
|
setp.eq.s32 %p62, %r228, 1118925336;
|
|
add.s32 %r229, %r228, -1;
|
|
mov.b32 %f560, %r229;
|
|
add.f32 %f561, %f559, 0f37000000;
|
|
selp.f32 %f154, %f561, %f559, %p62;
|
|
selp.f32 %f562, %f560, %f556, %p62;
|
|
mov.f32 %f563, 0f3FB8AA3B;
|
|
mul.rn.f32 %f564, %f562, %f563;
|
|
cvt.rzi.f32.f32 %f565, %f564;
|
|
abs.f32 %f566, %f565;
|
|
setp.gt.f32 %p63, %f566, 0f42FC0000;
|
|
mov.b32 %r230, %f565;
|
|
and.b32 %r231, %r230, -2147483648;
|
|
or.b32 %r232, %r231, 1123811328;
|
|
mov.b32 %f567, %r232;
|
|
selp.f32 %f568, %f567, %f565, %p63;
|
|
mov.f32 %f569, 0fBF317218;
|
|
fma.rn.f32 %f570, %f568, %f569, %f562;
|
|
mov.f32 %f571, 0f3102E308;
|
|
fma.rn.f32 %f572, %f568, %f571, %f570;
|
|
mul.f32 %f573, %f572, 0f3FB8AA3B;
|
|
add.f32 %f574, %f568, 0f4B40007F;
|
|
mov.b32 %r233, %f574;
|
|
shl.b32 %r234, %r233, 23;
|
|
mov.b32 %f575, %r234;
|
|
ex2.approx.ftz.f32 %f576, %f573;
|
|
mul.f32 %f155, %f576, %f575;
|
|
setp.eq.f32 %p64, %f155, 0f7F800000;
|
|
mov.f32 %f1149, 0f7F800000;
|
|
@%p64 bra $L__BB0_53;
|
|
|
|
fma.rn.f32 %f1149, %f155, %f154, %f155;
|
|
|
|
$L__BB0_53:
|
|
setp.lt.f32 %p65, %f1144, 0f00000000;
|
|
and.pred %p2, %p65, %p51;
|
|
setp.eq.f32 %p67, %f1144, 0f00000000;
|
|
@%p67 bra $L__BB0_57;
|
|
bra.uni $L__BB0_54;
|
|
|
|
$L__BB0_57:
|
|
add.f32 %f581, %f1144, %f1144;
|
|
selp.f32 %f1151, %f581, 0f00000000, %p51;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_54:
|
|
mov.b32 %r235, %f1149;
|
|
xor.b32 %r236, %r235, -2147483648;
|
|
mov.b32 %f577, %r236;
|
|
selp.f32 %f1151, %f577, %f1149, %p2;
|
|
setp.geu.f32 %p68, %f1144, 0f00000000;
|
|
@%p68 bra $L__BB0_58;
|
|
|
|
mov.f32 %f578, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f579, %f578;
|
|
setp.eq.f32 %p69, %f579, 0f3EE66666;
|
|
@%p69 bra $L__BB0_58;
|
|
|
|
mov.f32 %f1151, 0f7FFFFFFF;
|
|
|
|
$L__BB0_58:
|
|
abs.f32 %f1077, %f1144;
|
|
add.f32 %f582, %f1077, 0f3EE66666;
|
|
mov.b32 %r237, %f582;
|
|
setp.lt.s32 %p71, %r237, 2139095040;
|
|
@%p71 bra $L__BB0_63;
|
|
|
|
abs.f32 %f1078, %f1144;
|
|
setp.gtu.f32 %p72, %f1078, 0f7F800000;
|
|
@%p72 bra $L__BB0_62;
|
|
bra.uni $L__BB0_60;
|
|
|
|
$L__BB0_62:
|
|
add.f32 %f1151, %f1144, 0f3EE66666;
|
|
bra.uni $L__BB0_63;
|
|
|
|
$L__BB0_60:
|
|
abs.f32 %f1079, %f1144;
|
|
setp.neu.f32 %p73, %f1079, 0f7F800000;
|
|
@%p73 bra $L__BB0_63;
|
|
|
|
selp.f32 %f1151, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_63:
|
|
setp.eq.f32 %p74, %f1144, 0f3F800000;
|
|
selp.f32 %f164, 0f3F800000, %f1151, %p74;
|
|
abs.f32 %f165, %f1145;
|
|
setp.lt.f32 %p75, %f165, 0f00800000;
|
|
mul.f32 %f584, %f165, 0f4B800000;
|
|
selp.f32 %f585, %f584, %f165, %p75;
|
|
selp.f32 %f586, 0fC3170000, 0fC2FE0000, %p75;
|
|
mov.b32 %r238, %f585;
|
|
and.b32 %r239, %r238, 8388607;
|
|
or.b32 %r240, %r239, 1065353216;
|
|
mov.b32 %f587, %r240;
|
|
shr.u32 %r241, %r238, 23;
|
|
cvt.rn.f32.u32 %f588, %r241;
|
|
add.f32 %f589, %f586, %f588;
|
|
setp.gt.f32 %p76, %f587, 0f3FB504F3;
|
|
mul.f32 %f590, %f587, 0f3F000000;
|
|
add.f32 %f591, %f589, 0f3F800000;
|
|
selp.f32 %f592, %f591, %f589, %p76;
|
|
selp.f32 %f593, %f590, %f587, %p76;
|
|
add.f32 %f594, %f593, 0fBF800000;
|
|
add.f32 %f595, %f593, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f596, %f595;
|
|
add.f32 %f597, %f594, %f594;
|
|
mul.f32 %f598, %f597, %f596;
|
|
mul.f32 %f599, %f598, %f598;
|
|
mov.f32 %f600, 0f3C4CAF63;
|
|
mov.f32 %f601, 0f3B18F0FE;
|
|
fma.rn.f32 %f602, %f601, %f599, %f600;
|
|
mov.f32 %f603, 0f3DAAAABD;
|
|
fma.rn.f32 %f604, %f602, %f599, %f603;
|
|
mul.rn.f32 %f605, %f604, %f599;
|
|
mul.rn.f32 %f606, %f605, %f598;
|
|
sub.f32 %f607, %f594, %f598;
|
|
add.f32 %f608, %f607, %f607;
|
|
neg.f32 %f609, %f598;
|
|
fma.rn.f32 %f610, %f609, %f594, %f608;
|
|
mul.rn.f32 %f611, %f596, %f610;
|
|
add.f32 %f612, %f606, %f598;
|
|
sub.f32 %f613, %f598, %f612;
|
|
add.f32 %f614, %f606, %f613;
|
|
add.f32 %f615, %f611, %f614;
|
|
add.f32 %f616, %f612, %f615;
|
|
sub.f32 %f617, %f612, %f616;
|
|
add.f32 %f618, %f615, %f617;
|
|
mov.f32 %f619, 0f3F317200;
|
|
mul.rn.f32 %f620, %f592, %f619;
|
|
mov.f32 %f621, 0f35BFBE8E;
|
|
mul.rn.f32 %f622, %f592, %f621;
|
|
add.f32 %f623, %f620, %f616;
|
|
sub.f32 %f624, %f620, %f623;
|
|
add.f32 %f625, %f616, %f624;
|
|
add.f32 %f626, %f618, %f625;
|
|
add.f32 %f627, %f622, %f626;
|
|
add.f32 %f628, %f623, %f627;
|
|
sub.f32 %f629, %f623, %f628;
|
|
add.f32 %f630, %f627, %f629;
|
|
mov.f32 %f631, 0f3EE66666;
|
|
mul.rn.f32 %f632, %f631, %f628;
|
|
neg.f32 %f633, %f632;
|
|
fma.rn.f32 %f634, %f631, %f628, %f633;
|
|
fma.rn.f32 %f635, %f631, %f630, %f634;
|
|
mov.f32 %f636, 0f00000000;
|
|
fma.rn.f32 %f637, %f636, %f628, %f635;
|
|
add.rn.f32 %f638, %f632, %f637;
|
|
neg.f32 %f639, %f638;
|
|
add.rn.f32 %f640, %f632, %f639;
|
|
add.rn.f32 %f641, %f640, %f637;
|
|
mov.b32 %r242, %f638;
|
|
setp.eq.s32 %p77, %r242, 1118925336;
|
|
add.s32 %r243, %r242, -1;
|
|
mov.b32 %f642, %r243;
|
|
add.f32 %f643, %f641, 0f37000000;
|
|
selp.f32 %f166, %f643, %f641, %p77;
|
|
selp.f32 %f644, %f642, %f638, %p77;
|
|
mov.f32 %f645, 0f3FB8AA3B;
|
|
mul.rn.f32 %f646, %f644, %f645;
|
|
cvt.rzi.f32.f32 %f647, %f646;
|
|
abs.f32 %f648, %f647;
|
|
setp.gt.f32 %p78, %f648, 0f42FC0000;
|
|
mov.b32 %r244, %f647;
|
|
and.b32 %r245, %r244, -2147483648;
|
|
or.b32 %r246, %r245, 1123811328;
|
|
mov.b32 %f649, %r246;
|
|
selp.f32 %f650, %f649, %f647, %p78;
|
|
mov.f32 %f651, 0fBF317218;
|
|
fma.rn.f32 %f652, %f650, %f651, %f644;
|
|
mov.f32 %f653, 0f3102E308;
|
|
fma.rn.f32 %f654, %f650, %f653, %f652;
|
|
mul.f32 %f655, %f654, 0f3FB8AA3B;
|
|
add.f32 %f656, %f650, 0f4B40007F;
|
|
mov.b32 %r247, %f656;
|
|
shl.b32 %r248, %r247, 23;
|
|
mov.b32 %f657, %r248;
|
|
ex2.approx.ftz.f32 %f658, %f655;
|
|
mul.f32 %f167, %f658, %f657;
|
|
setp.eq.f32 %p79, %f167, 0f7F800000;
|
|
mov.f32 %f1152, 0f7F800000;
|
|
@%p79 bra $L__BB0_65;
|
|
|
|
fma.rn.f32 %f1152, %f167, %f166, %f167;
|
|
|
|
$L__BB0_65:
|
|
setp.lt.f32 %p80, %f1145, 0f00000000;
|
|
and.pred %p3, %p80, %p51;
|
|
setp.eq.f32 %p82, %f1145, 0f00000000;
|
|
@%p82 bra $L__BB0_69;
|
|
bra.uni $L__BB0_66;
|
|
|
|
$L__BB0_69:
|
|
add.f32 %f663, %f1145, %f1145;
|
|
selp.f32 %f1154, %f663, 0f00000000, %p51;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_66:
|
|
mov.b32 %r249, %f1152;
|
|
xor.b32 %r250, %r249, -2147483648;
|
|
mov.b32 %f659, %r250;
|
|
selp.f32 %f1154, %f659, %f1152, %p3;
|
|
setp.geu.f32 %p83, %f1145, 0f00000000;
|
|
@%p83 bra $L__BB0_70;
|
|
|
|
mov.f32 %f660, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f661, %f660;
|
|
setp.eq.f32 %p84, %f661, 0f3EE66666;
|
|
@%p84 bra $L__BB0_70;
|
|
|
|
mov.f32 %f1154, 0f7FFFFFFF;
|
|
|
|
$L__BB0_70:
|
|
abs.f32 %f1080, %f1145;
|
|
add.f32 %f664, %f1080, 0f3EE66666;
|
|
mov.b32 %r251, %f664;
|
|
setp.lt.s32 %p86, %r251, 2139095040;
|
|
@%p86 bra $L__BB0_75;
|
|
|
|
abs.f32 %f1081, %f1145;
|
|
setp.gtu.f32 %p87, %f1081, 0f7F800000;
|
|
@%p87 bra $L__BB0_74;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_74:
|
|
add.f32 %f1154, %f1145, 0f3EE66666;
|
|
bra.uni $L__BB0_75;
|
|
|
|
$L__BB0_72:
|
|
abs.f32 %f1082, %f1145;
|
|
setp.neu.f32 %p88, %f1082, 0f7F800000;
|
|
@%p88 bra $L__BB0_75;
|
|
|
|
selp.f32 %f1154, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_75:
|
|
setp.eq.f32 %p89, %f1145, 0f3F800000;
|
|
mov.f32 %f666, 0f3F800000;
|
|
selp.f32 %f667, 0f3F800000, %f1154, %p89;
|
|
min.f32 %f668, %f152, %f666;
|
|
mov.f32 %f669, 0f00000000;
|
|
max.f32 %f176, %f669, %f668;
|
|
min.f32 %f670, %f164, %f666;
|
|
max.f32 %f177, %f669, %f670;
|
|
min.f32 %f671, %f667, %f666;
|
|
max.f32 %f178, %f669, %f671;
|
|
mov.f32 %f675, 0f3ED55555;
|
|
abs.f32 %f180, %f176;
|
|
setp.lt.f32 %p90, %f180, 0f00800000;
|
|
mul.f32 %f677, %f180, 0f4B800000;
|
|
selp.f32 %f678, %f677, %f180, %p90;
|
|
selp.f32 %f679, 0fC3170000, 0fC2FE0000, %p90;
|
|
mov.b32 %r254, %f678;
|
|
and.b32 %r255, %r254, 8388607;
|
|
or.b32 %r256, %r255, 1065353216;
|
|
mov.b32 %f680, %r256;
|
|
shr.u32 %r257, %r254, 23;
|
|
cvt.rn.f32.u32 %f681, %r257;
|
|
add.f32 %f682, %f679, %f681;
|
|
setp.gt.f32 %p91, %f680, 0f3FB504F3;
|
|
mul.f32 %f683, %f680, 0f3F000000;
|
|
add.f32 %f684, %f682, 0f3F800000;
|
|
selp.f32 %f685, %f684, %f682, %p91;
|
|
selp.f32 %f686, %f683, %f680, %p91;
|
|
add.f32 %f687, %f686, 0fBF800000;
|
|
add.f32 %f688, %f686, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f689, %f688;
|
|
add.f32 %f690, %f687, %f687;
|
|
mul.f32 %f691, %f690, %f689;
|
|
mul.f32 %f692, %f691, %f691;
|
|
mov.f32 %f693, 0f3C4CAF63;
|
|
mov.f32 %f694, 0f3B18F0FE;
|
|
fma.rn.f32 %f695, %f694, %f692, %f693;
|
|
mov.f32 %f696, 0f3DAAAABD;
|
|
fma.rn.f32 %f697, %f695, %f692, %f696;
|
|
mul.rn.f32 %f698, %f697, %f692;
|
|
mul.rn.f32 %f699, %f698, %f691;
|
|
sub.f32 %f700, %f687, %f691;
|
|
add.f32 %f701, %f700, %f700;
|
|
neg.f32 %f702, %f691;
|
|
fma.rn.f32 %f703, %f702, %f687, %f701;
|
|
mul.rn.f32 %f704, %f689, %f703;
|
|
add.f32 %f705, %f699, %f691;
|
|
sub.f32 %f706, %f691, %f705;
|
|
add.f32 %f707, %f699, %f706;
|
|
add.f32 %f708, %f704, %f707;
|
|
add.f32 %f709, %f705, %f708;
|
|
sub.f32 %f710, %f705, %f709;
|
|
add.f32 %f711, %f708, %f710;
|
|
mov.f32 %f712, 0f3F317200;
|
|
mul.rn.f32 %f713, %f685, %f712;
|
|
mov.f32 %f714, 0f35BFBE8E;
|
|
mul.rn.f32 %f715, %f685, %f714;
|
|
add.f32 %f716, %f713, %f709;
|
|
sub.f32 %f717, %f713, %f716;
|
|
add.f32 %f718, %f709, %f717;
|
|
add.f32 %f719, %f711, %f718;
|
|
add.f32 %f720, %f715, %f719;
|
|
add.f32 %f721, %f716, %f720;
|
|
sub.f32 %f722, %f716, %f721;
|
|
add.f32 %f723, %f720, %f722;
|
|
mul.rn.f32 %f724, %f675, %f721;
|
|
neg.f32 %f725, %f724;
|
|
fma.rn.f32 %f726, %f675, %f721, %f725;
|
|
fma.rn.f32 %f727, %f675, %f723, %f726;
|
|
fma.rn.f32 %f728, %f669, %f721, %f727;
|
|
add.rn.f32 %f729, %f724, %f728;
|
|
neg.f32 %f730, %f729;
|
|
add.rn.f32 %f731, %f724, %f730;
|
|
add.rn.f32 %f732, %f731, %f728;
|
|
mov.b32 %r258, %f729;
|
|
setp.eq.s32 %p92, %r258, 1118925336;
|
|
add.s32 %r259, %r258, -1;
|
|
mov.b32 %f733, %r259;
|
|
add.f32 %f734, %f732, 0f37000000;
|
|
selp.f32 %f181, %f734, %f732, %p92;
|
|
selp.f32 %f735, %f733, %f729, %p92;
|
|
mov.f32 %f736, 0f3FB8AA3B;
|
|
mul.rn.f32 %f737, %f735, %f736;
|
|
cvt.rzi.f32.f32 %f738, %f737;
|
|
abs.f32 %f739, %f738;
|
|
setp.gt.f32 %p93, %f739, 0f42FC0000;
|
|
mov.b32 %r260, %f738;
|
|
and.b32 %r261, %r260, -2147483648;
|
|
or.b32 %r262, %r261, 1123811328;
|
|
mov.b32 %f740, %r262;
|
|
selp.f32 %f741, %f740, %f738, %p93;
|
|
mov.f32 %f742, 0fBF317218;
|
|
fma.rn.f32 %f743, %f741, %f742, %f735;
|
|
mov.f32 %f744, 0f3102E308;
|
|
fma.rn.f32 %f745, %f741, %f744, %f743;
|
|
mul.f32 %f746, %f745, 0f3FB8AA3B;
|
|
add.f32 %f747, %f741, 0f4B40007F;
|
|
mov.b32 %r263, %f747;
|
|
shl.b32 %r264, %r263, 23;
|
|
mov.b32 %f748, %r264;
|
|
ex2.approx.ftz.f32 %f749, %f746;
|
|
mul.f32 %f182, %f749, %f748;
|
|
setp.eq.f32 %p94, %f182, 0f7F800000;
|
|
mov.f32 %f1155, 0f7F800000;
|
|
@%p94 bra $L__BB0_77;
|
|
|
|
fma.rn.f32 %f1155, %f182, %f181, %f182;
|
|
|
|
$L__BB0_77:
|
|
mov.f32 %f1088, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1087, %f1088;
|
|
add.f32 %f1086, %f1087, %f1087;
|
|
mov.f32 %f1085, 0f3ED55555;
|
|
sub.f32 %f1084, %f1085, %f1086;
|
|
abs.f32 %f1083, %f1084;
|
|
setp.lt.f32 %p95, %f176, 0f00000000;
|
|
setp.eq.f32 %p96, %f1083, 0f3F800000;
|
|
and.pred %p4, %p95, %p96;
|
|
setp.eq.f32 %p97, %f176, 0f00000000;
|
|
@%p97 bra $L__BB0_81;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_81:
|
|
add.f32 %f754, %f176, %f176;
|
|
selp.f32 %f1157, %f754, 0f00000000, %p96;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_78:
|
|
mov.b32 %r265, %f1155;
|
|
xor.b32 %r266, %r265, -2147483648;
|
|
mov.b32 %f750, %r266;
|
|
selp.f32 %f1157, %f750, %f1155, %p4;
|
|
setp.geu.f32 %p98, %f176, 0f00000000;
|
|
@%p98 bra $L__BB0_82;
|
|
|
|
mov.f32 %f751, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f752, %f751;
|
|
setp.eq.f32 %p99, %f752, 0f3ED55555;
|
|
@%p99 bra $L__BB0_82;
|
|
|
|
mov.f32 %f1157, 0f7FFFFFFF;
|
|
|
|
$L__BB0_82:
|
|
add.f32 %f755, %f180, 0f3ED55555;
|
|
mov.b32 %r267, %f755;
|
|
setp.lt.s32 %p101, %r267, 2139095040;
|
|
@%p101 bra $L__BB0_87;
|
|
|
|
setp.gtu.f32 %p102, %f180, 0f7F800000;
|
|
@%p102 bra $L__BB0_86;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_86:
|
|
add.f32 %f1157, %f176, 0f3ED55555;
|
|
bra.uni $L__BB0_87;
|
|
|
|
$L__BB0_84:
|
|
setp.neu.f32 %p103, %f180, 0f7F800000;
|
|
@%p103 bra $L__BB0_87;
|
|
|
|
selp.f32 %f1157, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_87:
|
|
abs.f32 %f191, %f177;
|
|
setp.lt.f32 %p104, %f191, 0f00800000;
|
|
mul.f32 %f757, %f191, 0f4B800000;
|
|
selp.f32 %f758, %f757, %f191, %p104;
|
|
selp.f32 %f759, 0fC3170000, 0fC2FE0000, %p104;
|
|
mov.b32 %r268, %f758;
|
|
and.b32 %r269, %r268, 8388607;
|
|
or.b32 %r270, %r269, 1065353216;
|
|
mov.b32 %f760, %r270;
|
|
shr.u32 %r271, %r268, 23;
|
|
cvt.rn.f32.u32 %f761, %r271;
|
|
add.f32 %f762, %f759, %f761;
|
|
setp.gt.f32 %p105, %f760, 0f3FB504F3;
|
|
mul.f32 %f763, %f760, 0f3F000000;
|
|
add.f32 %f764, %f762, 0f3F800000;
|
|
selp.f32 %f765, %f764, %f762, %p105;
|
|
selp.f32 %f766, %f763, %f760, %p105;
|
|
add.f32 %f767, %f766, 0fBF800000;
|
|
add.f32 %f768, %f766, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f769, %f768;
|
|
add.f32 %f770, %f767, %f767;
|
|
mul.f32 %f771, %f770, %f769;
|
|
mul.f32 %f772, %f771, %f771;
|
|
mov.f32 %f773, 0f3C4CAF63;
|
|
mov.f32 %f774, 0f3B18F0FE;
|
|
fma.rn.f32 %f775, %f774, %f772, %f773;
|
|
mov.f32 %f776, 0f3DAAAABD;
|
|
fma.rn.f32 %f777, %f775, %f772, %f776;
|
|
mul.rn.f32 %f778, %f777, %f772;
|
|
mul.rn.f32 %f779, %f778, %f771;
|
|
sub.f32 %f780, %f767, %f771;
|
|
add.f32 %f781, %f780, %f780;
|
|
neg.f32 %f782, %f771;
|
|
fma.rn.f32 %f783, %f782, %f767, %f781;
|
|
mul.rn.f32 %f784, %f769, %f783;
|
|
add.f32 %f785, %f779, %f771;
|
|
sub.f32 %f786, %f771, %f785;
|
|
add.f32 %f787, %f779, %f786;
|
|
add.f32 %f788, %f784, %f787;
|
|
add.f32 %f789, %f785, %f788;
|
|
sub.f32 %f790, %f785, %f789;
|
|
add.f32 %f791, %f788, %f790;
|
|
mov.f32 %f792, 0f3F317200;
|
|
mul.rn.f32 %f793, %f765, %f792;
|
|
mov.f32 %f794, 0f35BFBE8E;
|
|
mul.rn.f32 %f795, %f765, %f794;
|
|
add.f32 %f796, %f793, %f789;
|
|
sub.f32 %f797, %f793, %f796;
|
|
add.f32 %f798, %f789, %f797;
|
|
add.f32 %f799, %f791, %f798;
|
|
add.f32 %f800, %f795, %f799;
|
|
add.f32 %f801, %f796, %f800;
|
|
sub.f32 %f802, %f796, %f801;
|
|
add.f32 %f803, %f800, %f802;
|
|
mov.f32 %f804, 0f3ED55555;
|
|
mul.rn.f32 %f805, %f804, %f801;
|
|
neg.f32 %f806, %f805;
|
|
fma.rn.f32 %f807, %f804, %f801, %f806;
|
|
fma.rn.f32 %f808, %f804, %f803, %f807;
|
|
mov.f32 %f809, 0f00000000;
|
|
fma.rn.f32 %f810, %f809, %f801, %f808;
|
|
add.rn.f32 %f811, %f805, %f810;
|
|
neg.f32 %f812, %f811;
|
|
add.rn.f32 %f813, %f805, %f812;
|
|
add.rn.f32 %f814, %f813, %f810;
|
|
mov.b32 %r272, %f811;
|
|
setp.eq.s32 %p106, %r272, 1118925336;
|
|
add.s32 %r273, %r272, -1;
|
|
mov.b32 %f815, %r273;
|
|
add.f32 %f816, %f814, 0f37000000;
|
|
selp.f32 %f192, %f816, %f814, %p106;
|
|
selp.f32 %f817, %f815, %f811, %p106;
|
|
mov.f32 %f818, 0f3FB8AA3B;
|
|
mul.rn.f32 %f819, %f817, %f818;
|
|
cvt.rzi.f32.f32 %f820, %f819;
|
|
abs.f32 %f821, %f820;
|
|
setp.gt.f32 %p107, %f821, 0f42FC0000;
|
|
mov.b32 %r274, %f820;
|
|
and.b32 %r275, %r274, -2147483648;
|
|
or.b32 %r276, %r275, 1123811328;
|
|
mov.b32 %f822, %r276;
|
|
selp.f32 %f823, %f822, %f820, %p107;
|
|
mov.f32 %f824, 0fBF317218;
|
|
fma.rn.f32 %f825, %f823, %f824, %f817;
|
|
mov.f32 %f826, 0f3102E308;
|
|
fma.rn.f32 %f827, %f823, %f826, %f825;
|
|
mul.f32 %f828, %f827, 0f3FB8AA3B;
|
|
add.f32 %f829, %f823, 0f4B40007F;
|
|
mov.b32 %r277, %f829;
|
|
shl.b32 %r278, %r277, 23;
|
|
mov.b32 %f830, %r278;
|
|
ex2.approx.ftz.f32 %f831, %f828;
|
|
mul.f32 %f193, %f831, %f830;
|
|
setp.eq.f32 %p108, %f193, 0f7F800000;
|
|
mov.f32 %f1158, 0f7F800000;
|
|
@%p108 bra $L__BB0_89;
|
|
|
|
fma.rn.f32 %f1158, %f193, %f192, %f193;
|
|
|
|
$L__BB0_89:
|
|
setp.lt.f32 %p109, %f177, 0f00000000;
|
|
and.pred %p5, %p109, %p96;
|
|
setp.eq.f32 %p111, %f177, 0f00000000;
|
|
@%p111 bra $L__BB0_93;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_93:
|
|
add.f32 %f836, %f177, %f177;
|
|
selp.f32 %f1160, %f836, 0f00000000, %p96;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_90:
|
|
mov.b32 %r279, %f1158;
|
|
xor.b32 %r280, %r279, -2147483648;
|
|
mov.b32 %f832, %r280;
|
|
selp.f32 %f1160, %f832, %f1158, %p5;
|
|
setp.geu.f32 %p112, %f177, 0f00000000;
|
|
@%p112 bra $L__BB0_94;
|
|
|
|
mov.f32 %f833, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f834, %f833;
|
|
setp.eq.f32 %p113, %f834, 0f3ED55555;
|
|
@%p113 bra $L__BB0_94;
|
|
|
|
mov.f32 %f1160, 0f7FFFFFFF;
|
|
|
|
$L__BB0_94:
|
|
add.f32 %f837, %f191, 0f3ED55555;
|
|
mov.b32 %r281, %f837;
|
|
setp.lt.s32 %p115, %r281, 2139095040;
|
|
@%p115 bra $L__BB0_99;
|
|
|
|
setp.gtu.f32 %p116, %f191, 0f7F800000;
|
|
@%p116 bra $L__BB0_98;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_98:
|
|
add.f32 %f1160, %f177, 0f3ED55555;
|
|
bra.uni $L__BB0_99;
|
|
|
|
$L__BB0_96:
|
|
setp.neu.f32 %p117, %f191, 0f7F800000;
|
|
@%p117 bra $L__BB0_99;
|
|
|
|
selp.f32 %f1160, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_99:
|
|
abs.f32 %f202, %f178;
|
|
setp.lt.f32 %p118, %f202, 0f00800000;
|
|
mul.f32 %f839, %f202, 0f4B800000;
|
|
selp.f32 %f840, %f839, %f202, %p118;
|
|
selp.f32 %f841, 0fC3170000, 0fC2FE0000, %p118;
|
|
mov.b32 %r282, %f840;
|
|
and.b32 %r283, %r282, 8388607;
|
|
or.b32 %r284, %r283, 1065353216;
|
|
mov.b32 %f842, %r284;
|
|
shr.u32 %r285, %r282, 23;
|
|
cvt.rn.f32.u32 %f843, %r285;
|
|
add.f32 %f844, %f841, %f843;
|
|
setp.gt.f32 %p119, %f842, 0f3FB504F3;
|
|
mul.f32 %f845, %f842, 0f3F000000;
|
|
add.f32 %f846, %f844, 0f3F800000;
|
|
selp.f32 %f847, %f846, %f844, %p119;
|
|
selp.f32 %f848, %f845, %f842, %p119;
|
|
add.f32 %f849, %f848, 0fBF800000;
|
|
add.f32 %f850, %f848, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f851, %f850;
|
|
add.f32 %f852, %f849, %f849;
|
|
mul.f32 %f853, %f852, %f851;
|
|
mul.f32 %f854, %f853, %f853;
|
|
mov.f32 %f855, 0f3C4CAF63;
|
|
mov.f32 %f856, 0f3B18F0FE;
|
|
fma.rn.f32 %f857, %f856, %f854, %f855;
|
|
mov.f32 %f858, 0f3DAAAABD;
|
|
fma.rn.f32 %f859, %f857, %f854, %f858;
|
|
mul.rn.f32 %f860, %f859, %f854;
|
|
mul.rn.f32 %f861, %f860, %f853;
|
|
sub.f32 %f862, %f849, %f853;
|
|
add.f32 %f863, %f862, %f862;
|
|
neg.f32 %f864, %f853;
|
|
fma.rn.f32 %f865, %f864, %f849, %f863;
|
|
mul.rn.f32 %f866, %f851, %f865;
|
|
add.f32 %f867, %f861, %f853;
|
|
sub.f32 %f868, %f853, %f867;
|
|
add.f32 %f869, %f861, %f868;
|
|
add.f32 %f870, %f866, %f869;
|
|
add.f32 %f871, %f867, %f870;
|
|
sub.f32 %f872, %f867, %f871;
|
|
add.f32 %f873, %f870, %f872;
|
|
mov.f32 %f874, 0f3F317200;
|
|
mul.rn.f32 %f875, %f847, %f874;
|
|
mov.f32 %f876, 0f35BFBE8E;
|
|
mul.rn.f32 %f877, %f847, %f876;
|
|
add.f32 %f878, %f875, %f871;
|
|
sub.f32 %f879, %f875, %f878;
|
|
add.f32 %f880, %f871, %f879;
|
|
add.f32 %f881, %f873, %f880;
|
|
add.f32 %f882, %f877, %f881;
|
|
add.f32 %f883, %f878, %f882;
|
|
sub.f32 %f884, %f878, %f883;
|
|
add.f32 %f885, %f882, %f884;
|
|
mov.f32 %f886, 0f3ED55555;
|
|
mul.rn.f32 %f887, %f886, %f883;
|
|
neg.f32 %f888, %f887;
|
|
fma.rn.f32 %f889, %f886, %f883, %f888;
|
|
fma.rn.f32 %f890, %f886, %f885, %f889;
|
|
mov.f32 %f891, 0f00000000;
|
|
fma.rn.f32 %f892, %f891, %f883, %f890;
|
|
add.rn.f32 %f893, %f887, %f892;
|
|
neg.f32 %f894, %f893;
|
|
add.rn.f32 %f895, %f887, %f894;
|
|
add.rn.f32 %f896, %f895, %f892;
|
|
mov.b32 %r286, %f893;
|
|
setp.eq.s32 %p120, %r286, 1118925336;
|
|
add.s32 %r287, %r286, -1;
|
|
mov.b32 %f897, %r287;
|
|
add.f32 %f898, %f896, 0f37000000;
|
|
selp.f32 %f203, %f898, %f896, %p120;
|
|
selp.f32 %f899, %f897, %f893, %p120;
|
|
mov.f32 %f900, 0f3FB8AA3B;
|
|
mul.rn.f32 %f901, %f899, %f900;
|
|
cvt.rzi.f32.f32 %f902, %f901;
|
|
abs.f32 %f903, %f902;
|
|
setp.gt.f32 %p121, %f903, 0f42FC0000;
|
|
mov.b32 %r288, %f902;
|
|
and.b32 %r289, %r288, -2147483648;
|
|
or.b32 %r290, %r289, 1123811328;
|
|
mov.b32 %f904, %r290;
|
|
selp.f32 %f905, %f904, %f902, %p121;
|
|
mov.f32 %f906, 0fBF317218;
|
|
fma.rn.f32 %f907, %f905, %f906, %f899;
|
|
mov.f32 %f908, 0f3102E308;
|
|
fma.rn.f32 %f909, %f905, %f908, %f907;
|
|
mul.f32 %f910, %f909, 0f3FB8AA3B;
|
|
add.f32 %f911, %f905, 0f4B40007F;
|
|
mov.b32 %r291, %f911;
|
|
shl.b32 %r292, %r291, 23;
|
|
mov.b32 %f912, %r292;
|
|
ex2.approx.ftz.f32 %f913, %f910;
|
|
mul.f32 %f204, %f913, %f912;
|
|
setp.eq.f32 %p122, %f204, 0f7F800000;
|
|
mov.f32 %f1161, 0f7F800000;
|
|
@%p122 bra $L__BB0_101;
|
|
|
|
fma.rn.f32 %f1161, %f204, %f203, %f204;
|
|
|
|
$L__BB0_101:
|
|
setp.lt.f32 %p123, %f178, 0f00000000;
|
|
and.pred %p6, %p123, %p96;
|
|
setp.eq.f32 %p125, %f178, 0f00000000;
|
|
@%p125 bra $L__BB0_105;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_105:
|
|
add.f32 %f918, %f178, %f178;
|
|
selp.f32 %f1163, %f918, 0f00000000, %p96;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_102:
|
|
mov.b32 %r293, %f1161;
|
|
xor.b32 %r294, %r293, -2147483648;
|
|
mov.b32 %f914, %r294;
|
|
selp.f32 %f1163, %f914, %f1161, %p6;
|
|
setp.geu.f32 %p126, %f178, 0f00000000;
|
|
@%p126 bra $L__BB0_106;
|
|
|
|
mov.f32 %f915, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f916, %f915;
|
|
setp.eq.f32 %p127, %f916, 0f3ED55555;
|
|
@%p127 bra $L__BB0_106;
|
|
|
|
mov.f32 %f1163, 0f7FFFFFFF;
|
|
|
|
$L__BB0_106:
|
|
add.f32 %f919, %f202, 0f3ED55555;
|
|
mov.b32 %r295, %f919;
|
|
setp.lt.s32 %p129, %r295, 2139095040;
|
|
@%p129 bra $L__BB0_111;
|
|
|
|
setp.gtu.f32 %p130, %f202, 0f7F800000;
|
|
@%p130 bra $L__BB0_110;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_110:
|
|
add.f32 %f1163, %f178, 0f3ED55555;
|
|
bra.uni $L__BB0_111;
|
|
|
|
$L__BB0_108:
|
|
setp.neu.f32 %p131, %f202, 0f7F800000;
|
|
@%p131 bra $L__BB0_111;
|
|
|
|
selp.f32 %f1163, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_111:
|
|
ld.const.u64 %rd116, [params+144];
|
|
cvta.to.global.u64 %rd115, %rd116;
|
|
ld.const.u32 %r352, [params+136];
|
|
mad.lo.s32 %r351, %r352, %r6, %r5;
|
|
cvt.u64.u32 %rd114, %r351;
|
|
fma.rn.f32 %f920, %f1157, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p132, %f176, 0f3F800000;
|
|
mov.f32 %f921, 0f3F800000;
|
|
selp.f32 %f922, 0f3F7FFFFF, %f920, %p132;
|
|
mul.f32 %f923, %f176, 0f414EB852;
|
|
setp.lt.f32 %p133, %f176, 0f3B4D2E1C;
|
|
selp.f32 %f924, %f923, %f922, %p133;
|
|
fma.rn.f32 %f925, %f1160, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p134, %f177, 0f3F800000;
|
|
selp.f32 %f926, 0f3F7FFFFF, %f925, %p134;
|
|
mul.f32 %f927, %f177, 0f414EB852;
|
|
setp.lt.f32 %p135, %f177, 0f3B4D2E1C;
|
|
selp.f32 %f928, %f927, %f926, %p135;
|
|
fma.rn.f32 %f929, %f1163, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p136, %f178, 0f3F800000;
|
|
selp.f32 %f930, 0f3F7FFFFF, %f929, %p136;
|
|
mul.f32 %f931, %f178, 0f414EB852;
|
|
setp.lt.f32 %p137, %f178, 0f3B4D2E1C;
|
|
selp.f32 %f932, %f931, %f930, %p137;
|
|
min.f32 %f933, %f924, %f921;
|
|
mov.f32 %f934, 0f00000000;
|
|
max.f32 %f935, %f934, %f933;
|
|
mul.f32 %f936, %f935, 0f43800000;
|
|
cvt.rzi.u32.f32 %r296, %f936;
|
|
min.u32 %r297, %r296, 255;
|
|
min.f32 %f937, %f928, %f921;
|
|
max.f32 %f938, %f934, %f937;
|
|
mul.f32 %f939, %f938, 0f43800000;
|
|
cvt.rzi.u32.f32 %r298, %f939;
|
|
min.u32 %r299, %r298, 255;
|
|
min.f32 %f940, %f932, %f921;
|
|
max.f32 %f941, %f934, %f940;
|
|
mul.f32 %f942, %f941, 0f43800000;
|
|
cvt.rzi.u32.f32 %r300, %f942;
|
|
min.u32 %r301, %r300, 255;
|
|
shl.b64 %rd68, %rd114, 2;
|
|
add.s64 %rd69, %rd115, %rd68;
|
|
cvt.u16.u32 %rs23, %r301;
|
|
cvt.u16.u32 %rs24, %r299;
|
|
cvt.u16.u32 %rs25, %r297;
|
|
mov.u16 %rs26, 255;
|
|
st.global.v4.u8 [%rd69], {%rs25, %rs24, %rs23, %rs26};
|
|
|
|
$L__BB0_112:
|
|
ld.const.u32 %r349, [params+104];
|
|
and.b32 %r302, %r349, 4;
|
|
setp.eq.s32 %p138, %r302, 0;
|
|
@%p138 bra $L__BB0_114;
|
|
|
|
ld.const.u64 %rd70, [params+224];
|
|
cvta.to.global.u64 %rd71, %rd70;
|
|
ld.const.u32 %r303, [params+216];
|
|
mad.lo.s32 %r304, %r303, %r6, %r5;
|
|
mov.f32 %f946, 0f3F800000;
|
|
mul.wide.u32 %rd72, %r304, 8;
|
|
add.s64 %rd73, %rd71, %rd72;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f946;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f1145;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f1144;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f1143;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd73], {%rs27, %rs28, %rs29, %rs30};
|
|
|
|
$L__BB0_114:
|
|
ld.const.u32 %r350, [params+104];
|
|
and.b32 %r305, %r350, 16;
|
|
setp.eq.s32 %p139, %r305, 0;
|
|
@%p139 bra $L__BB0_116;
|
|
|
|
ld.const.u64 %rd74, [params+240];
|
|
cvta.to.global.u64 %rd75, %rd74;
|
|
ld.const.u32 %r306, [params+232];
|
|
mad.lo.s32 %r307, %r306, %r6, %r5;
|
|
mov.f32 %f950, 0f3F800000;
|
|
mul.wide.u32 %rd76, %r307, 8;
|
|
add.s64 %rd77, %rd75, %rd76;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f950;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f127;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs32, %f126;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs31, %f125;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd77], {%rs31, %rs32, %rs33, %rs34};
|
|
|
|
$L__BB0_116:
|
|
mul.f32 %f213, %f113, 0f3F000000;
|
|
mul.f32 %f214, %f114, 0f3F000000;
|
|
mul.f32 %f215, %f115, 0f3F000000;
|
|
ld.const.u32 %r50, [params+108];
|
|
setp.eq.s32 %p140, %r50, 0;
|
|
ld.const.u64 %rd78, [params+256];
|
|
cvta.to.global.u64 %rd79, %rd78;
|
|
ld.const.u32 %r308, [params+248];
|
|
mad.lo.s32 %r309, %r308, %r6, %r5;
|
|
mul.wide.u32 %rd80, %r309, 8;
|
|
add.s64 %rd18, %rd79, %rd80;
|
|
@%p140 bra $L__BB0_118;
|
|
|
|
ld.global.v4.u16 {%rs42, %rs43, %rs44, %rs45}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f951, %rs42;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f952, %rs43;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f953, %rs44;}
|
|
|
|
// end inline asm
|
|
add.f32 %f954, %f213, %f951;
|
|
add.f32 %f955, %f214, %f952;
|
|
add.f32 %f956, %f215, %f953;
|
|
mov.f32 %f957, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f956;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs39, %f955;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f954;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f957;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs38, %rs39, %rs40, %rs41};
|
|
bra.uni $L__BB0_119;
|
|
|
|
$L__BB0_118:
|
|
mov.f32 %f961, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f961;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f215;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs47, %f214;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs46, %f213;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs46, %rs47, %rs48, %rs49};
|
|
|
|
$L__BB0_119:
|
|
mov.f32 %f962, 0f34000000;
|
|
max.f32 %f963, %f213, %f962;
|
|
mul.f32 %f964, %f116, 0f3F000000;
|
|
div.rn.f32 %f965, %f964, %f963;
|
|
max.f32 %f966, %f214, %f962;
|
|
mul.f32 %f967, %f117, 0f3F000000;
|
|
div.rn.f32 %f968, %f967, %f966;
|
|
max.f32 %f969, %f215, %f962;
|
|
mul.f32 %f970, %f118, 0f3F000000;
|
|
div.rn.f32 %f971, %f970, %f969;
|
|
fma.rn.f32 %f216, %f965, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f217, %f968, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f218, %f971, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f972, %f119, 0f3F000000;
|
|
div.rn.f32 %f973, %f972, %f963;
|
|
mul.f32 %f974, %f120, 0f3F000000;
|
|
div.rn.f32 %f975, %f974, %f966;
|
|
mul.f32 %f976, %f121, 0f3F000000;
|
|
div.rn.f32 %f977, %f976, %f969;
|
|
fma.rn.f32 %f219, %f973, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f220, %f975, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f221, %f977, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f978, %f122, 0f3F000000;
|
|
div.rn.f32 %f979, %f978, %f963;
|
|
mul.f32 %f980, %f123, 0f3F000000;
|
|
div.rn.f32 %f981, %f980, %f966;
|
|
mul.f32 %f982, %f124, 0f3F000000;
|
|
div.rn.f32 %f983, %f982, %f969;
|
|
fma.rn.f32 %f222, %f979, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f223, %f981, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f224, %f983, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd81, [params+272];
|
|
cvta.to.global.u64 %rd82, %rd81;
|
|
ld.const.u32 %r310, [params+264];
|
|
mad.lo.s32 %r311, %r310, %r6, %r5;
|
|
mul.wide.u32 %rd83, %r311, 8;
|
|
add.s64 %rd19, %rd82, %rd83;
|
|
@%p140 bra $L__BB0_121;
|
|
|
|
ld.global.v4.u16 {%rs57, %rs58, %rs59, %rs60}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f984, %rs57;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f985, %rs58;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f986, %rs59;}
|
|
|
|
// end inline asm
|
|
add.f32 %f987, %f216, %f984;
|
|
add.f32 %f988, %f217, %f985;
|
|
add.f32 %f989, %f218, %f986;
|
|
mov.f32 %f990, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f989;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f988;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f987;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f990;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs53, %rs54, %rs55, %rs56};
|
|
bra.uni $L__BB0_122;
|
|
|
|
$L__BB0_121:
|
|
mov.f32 %f994, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f994;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f218;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f217;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f216;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs61, %rs62, %rs63, %rs64};
|
|
|
|
$L__BB0_122:
|
|
ld.const.u64 %rd84, [params+288];
|
|
cvta.to.global.u64 %rd85, %rd84;
|
|
ld.const.u32 %r312, [params+280];
|
|
mad.lo.s32 %r313, %r312, %r6, %r5;
|
|
mul.wide.u32 %rd86, %r313, 8;
|
|
add.s64 %rd20, %rd85, %rd86;
|
|
@%p140 bra $L__BB0_124;
|
|
|
|
ld.global.v4.u16 {%rs72, %rs73, %rs74, %rs75}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f995, %rs72;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f996, %rs73;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f997, %rs74;}
|
|
|
|
// end inline asm
|
|
add.f32 %f998, %f219, %f995;
|
|
add.f32 %f999, %f220, %f996;
|
|
add.f32 %f1000, %f221, %f997;
|
|
mov.f32 %f1001, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1000;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f999;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f998;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f1001;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs68, %rs69, %rs70, %rs71};
|
|
bra.uni $L__BB0_125;
|
|
|
|
$L__BB0_124:
|
|
mov.f32 %f1005, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f1005;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f221;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f220;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f219;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs76, %rs77, %rs78, %rs79};
|
|
|
|
$L__BB0_125:
|
|
ld.const.u64 %rd87, [params+304];
|
|
cvta.to.global.u64 %rd88, %rd87;
|
|
ld.const.u32 %r314, [params+296];
|
|
mad.lo.s32 %r315, %r314, %r6, %r5;
|
|
mul.wide.u32 %rd89, %r315, 8;
|
|
add.s64 %rd21, %rd88, %rd89;
|
|
@%p140 bra $L__BB0_127;
|
|
|
|
ld.global.v4.u16 {%rs87, %rs88, %rs89, %rs90}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1006, %rs87;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1007, %rs88;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1008, %rs89;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1009, %f222, %f1006;
|
|
add.f32 %f1010, %f223, %f1007;
|
|
add.f32 %f1011, %f224, %f1008;
|
|
mov.f32 %f1012, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1011;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1010;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1009;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1012;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs83, %rs84, %rs85, %rs86};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_127:
|
|
mov.f32 %f1016, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f1016;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f224;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f223;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f222;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs91, %rs92, %rs93, %rs94};
|
|
|
|
$L__BB0_146:
|
|
ret;
|
|
|
|
}
|
|
|