2839 lines
80 KiB
Plaintext
2839 lines
80 KiB
Plaintext
//
|
|
// Generated by NVIDIA NVVM Compiler
|
|
//
|
|
// Compiler Build ID: CL-31968024
|
|
// Cuda compilation tools, release 12.0, V12.0.76
|
|
// Based on NVVM 7.0.1
|
|
//
|
|
|
|
.version 8.0
|
|
.target sm_52
|
|
.address_size 64
|
|
|
|
// .globl __raygen__oxMain
|
|
.const .align 16 .b8 params[1184];
|
|
|
|
.visible .entry __raygen__oxMain()
|
|
{
|
|
.reg .pred %p<210>;
|
|
.reg .b16 %rs<180>;
|
|
.reg .f32 %f<1764>;
|
|
.reg .b32 %r<454>;
|
|
.reg .b64 %rd<78>;
|
|
|
|
|
|
// begin inline asm
|
|
call (%r26), _optix_get_launch_index_x, ();
|
|
// end inline asm
|
|
// begin inline asm
|
|
call (%r27), _optix_get_launch_index_y, ();
|
|
// end inline asm
|
|
ld.const.u64 %rd21, [params+400];
|
|
cvta.to.global.u64 %rd22, %rd21;
|
|
ld.const.u32 %r32, [params+392];
|
|
mad.lo.s32 %r33, %r32, %r27, %r26;
|
|
mul.wide.u32 %rd23, %r33, 4;
|
|
add.s64 %rd1, %rd22, %rd23;
|
|
ld.global.v2.u8 {%rs9, %rs178}, [%rd1];
|
|
or.b16 %rs11, %rs9, %rs178;
|
|
and.b16 %rs12, %rs11, 255;
|
|
setp.eq.s16 %p11, %rs12, 0;
|
|
@%p11 bra $L__BB0_2;
|
|
|
|
ld.global.u8 %rs177, [%rd1+2];
|
|
bra.uni $L__BB0_3;
|
|
|
|
$L__BB0_2:
|
|
ld.global.u8 %rs177, [%rd1+2];
|
|
setp.eq.s16 %p12, %rs177, 0;
|
|
mov.f32 %f1647, 0f00000000;
|
|
mov.u16 %rs178, 0;
|
|
mov.f32 %f1648, %f1647;
|
|
mov.f32 %f1649, %f1647;
|
|
@%p12 bra $L__BB0_4;
|
|
|
|
$L__BB0_3:
|
|
cvt.rn.f32.u16 %f329, %rs9;
|
|
div.rn.f32 %f330, %f329, 0f437F0000;
|
|
fma.rn.f32 %f331, %f330, 0f40000000, 0fBF800000;
|
|
and.b16 %rs15, %rs178, 255;
|
|
cvt.rn.f32.u16 %f332, %rs15;
|
|
div.rn.f32 %f333, %f332, 0f437F0000;
|
|
fma.rn.f32 %f334, %f333, 0f40000000, 0fBF800000;
|
|
cvt.rn.f32.u16 %f335, %rs177;
|
|
div.rn.f32 %f336, %f335, 0f437F0000;
|
|
fma.rn.f32 %f337, %f336, 0f40000000, 0fBF800000;
|
|
mul.f32 %f338, %f334, %f334;
|
|
fma.rn.f32 %f339, %f331, %f331, %f338;
|
|
fma.rn.f32 %f340, %f337, %f337, %f339;
|
|
sqrt.rn.f32 %f341, %f340;
|
|
rcp.rn.f32 %f342, %f341;
|
|
mul.f32 %f1649, %f342, %f337;
|
|
mul.f32 %f1648, %f342, %f334;
|
|
mul.f32 %f1647, %f331, %f342;
|
|
|
|
$L__BB0_4:
|
|
ld.const.v2.u32 {%r34, %r35}, [params];
|
|
add.s32 %r3, %r34, %r26;
|
|
add.s32 %r4, %r35, %r27;
|
|
setp.eq.f32 %p13, %f1647, 0f00000000;
|
|
setp.eq.f32 %p14, %f1648, 0f00000000;
|
|
and.pred %p15, %p13, %p14;
|
|
setp.eq.f32 %p16, %f1649, 0f00000000;
|
|
and.pred %p17, %p16, %p15;
|
|
@%p17 bra $L__BB0_163;
|
|
bra.uni $L__BB0_5;
|
|
|
|
$L__BB0_163:
|
|
ld.const.u32 %r23, [params+104];
|
|
and.b32 %r428, %r23, 1;
|
|
setp.eq.b32 %p198, %r428, 1;
|
|
mov.pred %p199, 0;
|
|
xor.pred %p200, %p198, %p199;
|
|
not.pred %p201, %p200;
|
|
@%p201 bra $L__BB0_165;
|
|
|
|
ld.const.u64 %rd54, [params+144];
|
|
cvta.to.global.u64 %rd55, %rd54;
|
|
ld.const.u32 %r429, [params+136];
|
|
mad.lo.s32 %r430, %r429, %r4, %r3;
|
|
mul.wide.u32 %rd56, %r430, 4;
|
|
add.s64 %rd57, %rd55, %rd56;
|
|
mov.u16 %rs99, 0;
|
|
st.global.v4.u8 [%rd57], {%rs99, %rs99, %rs99, %rs99};
|
|
|
|
$L__BB0_165:
|
|
and.b32 %r431, %r23, 8;
|
|
setp.eq.s32 %p202, %r431, 0;
|
|
@%p202 bra $L__BB0_167;
|
|
|
|
ld.const.u64 %rd58, [params+192];
|
|
cvta.to.global.u64 %rd59, %rd58;
|
|
ld.const.u32 %r432, [params+184];
|
|
mad.lo.s32 %r433, %r432, %r4, %r3;
|
|
mov.f32 %f1598, 0f00000000;
|
|
cvt.rzi.u32.f32 %r434, %f1598;
|
|
mul.wide.u32 %rd60, %r433, 2;
|
|
add.s64 %rd61, %rd59, %rd60;
|
|
mov.u16 %rs100, 0;
|
|
cvt.u16.u32 %rs101, %r434;
|
|
st.global.v2.u8 [%rd61], {%rs101, %rs100};
|
|
|
|
$L__BB0_167:
|
|
and.b32 %r435, %r23, 4;
|
|
setp.eq.s32 %p203, %r435, 0;
|
|
ld.const.u32 %r453, [params+108];
|
|
@%p203 bra $L__BB0_171;
|
|
|
|
setp.eq.s32 %p204, %r453, 0;
|
|
ld.const.u64 %rd62, [params+224];
|
|
cvta.to.global.u64 %rd63, %rd62;
|
|
ld.const.u32 %r436, [params+216];
|
|
mad.lo.s32 %r437, %r436, %r4, %r3;
|
|
mul.wide.u32 %rd64, %r437, 8;
|
|
add.s64 %rd16, %rd63, %rd64;
|
|
@%p204 bra $L__BB0_170;
|
|
|
|
ld.global.v4.u16 {%rs108, %rs109, %rs110, %rs111}, [%rd16];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1599, %rs108;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1600, %rs109;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1601, %rs110;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1602, %f1599, 0f00000000;
|
|
add.f32 %f1603, %f1600, 0f00000000;
|
|
add.f32 %f1604, %f1601, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f1604;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f1603;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs105, %f1602;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs112, 0;
|
|
st.global.v4.u16 [%rd16], {%rs105, %rs106, %rs107, %rs112};
|
|
bra.uni $L__BB0_171;
|
|
|
|
$L__BB0_5:
|
|
ld.const.u64 %rd24, [params+432];
|
|
cvta.to.global.u64 %rd25, %rd24;
|
|
ld.const.u32 %r38, [params+424];
|
|
mad.lo.s32 %r39, %r38, %r27, %r26;
|
|
mul.wide.u32 %rd26, %r39, 12;
|
|
add.s64 %rd27, %rd25, %rd26;
|
|
ld.global.f32 %f10, [%rd27];
|
|
mul.f32 %f343, %f10, 0f3456BF95;
|
|
ld.global.f32 %f11, [%rd27+4];
|
|
mul.f32 %f344, %f11, 0f3456BF95;
|
|
ld.global.f32 %f12, [%rd27+8];
|
|
mul.f32 %f345, %f12, 0f3456BF95;
|
|
abs.f32 %f346, %f1647;
|
|
div.rn.f32 %f347, %f343, %f346;
|
|
abs.f32 %f348, %f1648;
|
|
div.rn.f32 %f349, %f344, %f348;
|
|
abs.f32 %f350, %f1649;
|
|
div.rn.f32 %f351, %f345, %f350;
|
|
abs.f32 %f352, %f347;
|
|
abs.f32 %f353, %f349;
|
|
abs.f32 %f354, %f351;
|
|
mov.f32 %f355, 0f38D1B717;
|
|
max.f32 %f356, %f352, %f355;
|
|
max.f32 %f357, %f353, %f355;
|
|
max.f32 %f358, %f354, %f355;
|
|
fma.rn.f32 %f13, %f1647, %f356, %f10;
|
|
fma.rn.f32 %f14, %f1648, %f357, %f11;
|
|
fma.rn.f32 %f15, %f1649, %f358, %f12;
|
|
ld.const.u32 %r5, [params+600];
|
|
setp.eq.s32 %p18, %r5, 0;
|
|
@%p18 bra $L__BB0_58;
|
|
|
|
ld.const.u64 %rd28, [params+608];
|
|
cvta.to.global.u64 %rd2, %rd28;
|
|
mov.f32 %f375, 0f40000000;
|
|
cvt.rzi.f32.f32 %f376, %f375;
|
|
add.f32 %f377, %f376, %f376;
|
|
mov.f32 %f378, 0f40800000;
|
|
sub.f32 %f379, %f378, %f377;
|
|
abs.f32 %f16, %f379;
|
|
ld.const.u32 %r6, [params+544];
|
|
ld.const.u32 %r451, [params+104];
|
|
mul.f32 %f17, %f13, 0f3456BF95;
|
|
mul.f32 %f18, %f14, 0f3456BF95;
|
|
mul.f32 %f19, %f15, 0f3456BF95;
|
|
mov.f32 %f374, 0f00000000;
|
|
mov.u32 %r447, 0;
|
|
ld.const.u64 %rd3, [params+96];
|
|
abs.f32 %f587, %f17;
|
|
abs.f32 %f588, %f18;
|
|
max.f32 %f589, %f587, %f588;
|
|
abs.f32 %f590, %f19;
|
|
max.f32 %f591, %f589, %f590;
|
|
mov.f32 %f1726, %f374;
|
|
mov.f32 %f1725, %f374;
|
|
mov.f32 %f1724, %f374;
|
|
mov.f32 %f1723, %f374;
|
|
mov.f32 %f1722, %f374;
|
|
mov.f32 %f1721, %f374;
|
|
mov.f32 %f1720, %f374;
|
|
mov.f32 %f1719, %f374;
|
|
mov.f32 %f1718, %f374;
|
|
mov.f32 %f1717, %f374;
|
|
mov.f32 %f1716, %f374;
|
|
mov.f32 %f1715, %f374;
|
|
mov.f32 %f1714, %f374;
|
|
mov.f32 %f1713, %f374;
|
|
mov.f32 %f1712, %f374;
|
|
mov.f32 %f1711, %f374;
|
|
|
|
$L__BB0_7:
|
|
mul.wide.u32 %rd29, %r447, 112;
|
|
add.s64 %rd5, %rd2, %rd29;
|
|
ld.global.v4.f32 {%f381, %f382, %f383, %f384}, [%rd5];
|
|
ld.global.v4.f32 {%f385, %f386, %f387, %f388}, [%rd5+16];
|
|
ld.global.v4.f32 {%f391, %f1674, %f1675, %f394}, [%rd5+32];
|
|
ld.global.v4.f32 {%f395, %f396, %f397, %f1672}, [%rd5+48];
|
|
ld.global.v4.f32 {%f399, %f400, %f401, %f402}, [%rd5+64];
|
|
ld.global.v4.u32 {%r41, %r42, %r43, %r44}, [%rd5+80];
|
|
mov.b32 %f55, %r43;
|
|
mov.b32 %f54, %r42;
|
|
mov.b32 %f53, %r41;
|
|
ld.global.u64 %rd6, [%rd5+96];
|
|
sub.f32 %f403, %f382, %f10;
|
|
sub.f32 %f404, %f383, %f11;
|
|
sub.f32 %f405, %f384, %f12;
|
|
mul.f32 %f406, %f404, %f404;
|
|
fma.rn.f32 %f407, %f403, %f403, %f406;
|
|
fma.rn.f32 %f408, %f405, %f405, %f407;
|
|
sqrt.rn.f32 %f409, %f408;
|
|
rcp.rn.f32 %f410, %f409;
|
|
mul.f32 %f57, %f403, %f410;
|
|
mul.f32 %f58, %f404, %f410;
|
|
mul.f32 %f59, %f405, %f410;
|
|
mul.f32 %f60, %f409, %f386;
|
|
mul.f32 %f61, %f409, %f388;
|
|
abs.f32 %f62, %f61;
|
|
setp.lt.f32 %p19, %f62, 0f00800000;
|
|
mul.f32 %f411, %f62, 0f4B800000;
|
|
selp.f32 %f412, %f411, %f62, %p19;
|
|
selp.f32 %f413, 0fC3170000, 0fC2FE0000, %p19;
|
|
mov.b32 %r48, %f412;
|
|
and.b32 %r49, %r48, 8388607;
|
|
or.b32 %r50, %r49, 1065353216;
|
|
mov.b32 %f414, %r50;
|
|
shr.u32 %r51, %r48, 23;
|
|
cvt.rn.f32.u32 %f415, %r51;
|
|
add.f32 %f416, %f413, %f415;
|
|
setp.gt.f32 %p20, %f414, 0f3FB504F3;
|
|
mul.f32 %f417, %f414, 0f3F000000;
|
|
add.f32 %f418, %f416, 0f3F800000;
|
|
selp.f32 %f419, %f418, %f416, %p20;
|
|
selp.f32 %f420, %f417, %f414, %p20;
|
|
add.f32 %f421, %f420, 0fBF800000;
|
|
add.f32 %f422, %f420, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f423, %f422;
|
|
add.f32 %f424, %f421, %f421;
|
|
mul.f32 %f425, %f424, %f423;
|
|
mul.f32 %f426, %f425, %f425;
|
|
mov.f32 %f427, 0f3C4CAF63;
|
|
mov.f32 %f428, 0f3B18F0FE;
|
|
fma.rn.f32 %f429, %f428, %f426, %f427;
|
|
mov.f32 %f430, 0f3DAAAABD;
|
|
fma.rn.f32 %f431, %f429, %f426, %f430;
|
|
mul.rn.f32 %f432, %f431, %f426;
|
|
mul.rn.f32 %f433, %f432, %f425;
|
|
sub.f32 %f434, %f421, %f425;
|
|
add.f32 %f435, %f434, %f434;
|
|
neg.f32 %f436, %f425;
|
|
fma.rn.f32 %f437, %f436, %f421, %f435;
|
|
mul.rn.f32 %f438, %f423, %f437;
|
|
add.f32 %f439, %f433, %f425;
|
|
sub.f32 %f440, %f425, %f439;
|
|
add.f32 %f441, %f433, %f440;
|
|
add.f32 %f442, %f438, %f441;
|
|
add.f32 %f443, %f439, %f442;
|
|
sub.f32 %f444, %f439, %f443;
|
|
add.f32 %f445, %f442, %f444;
|
|
mov.f32 %f446, 0f3F317200;
|
|
mul.rn.f32 %f447, %f419, %f446;
|
|
mov.f32 %f448, 0f35BFBE8E;
|
|
mul.rn.f32 %f449, %f419, %f448;
|
|
add.f32 %f450, %f447, %f443;
|
|
sub.f32 %f451, %f447, %f450;
|
|
add.f32 %f452, %f443, %f451;
|
|
add.f32 %f453, %f445, %f452;
|
|
add.f32 %f454, %f449, %f453;
|
|
add.f32 %f455, %f450, %f454;
|
|
sub.f32 %f456, %f450, %f455;
|
|
add.f32 %f457, %f454, %f456;
|
|
mul.rn.f32 %f459, %f378, %f455;
|
|
neg.f32 %f460, %f459;
|
|
fma.rn.f32 %f461, %f378, %f455, %f460;
|
|
fma.rn.f32 %f462, %f378, %f457, %f461;
|
|
fma.rn.f32 %f464, %f374, %f455, %f462;
|
|
add.rn.f32 %f465, %f459, %f464;
|
|
neg.f32 %f466, %f465;
|
|
add.rn.f32 %f467, %f459, %f466;
|
|
add.rn.f32 %f468, %f467, %f464;
|
|
mov.b32 %r52, %f465;
|
|
setp.eq.s32 %p21, %r52, 1118925336;
|
|
add.s32 %r53, %r52, -1;
|
|
mov.b32 %f469, %r53;
|
|
add.f32 %f470, %f468, 0f37000000;
|
|
selp.f32 %f63, %f470, %f468, %p21;
|
|
selp.f32 %f471, %f469, %f465, %p21;
|
|
mov.f32 %f472, 0f3FB8AA3B;
|
|
mul.rn.f32 %f473, %f471, %f472;
|
|
cvt.rzi.f32.f32 %f474, %f473;
|
|
abs.f32 %f475, %f474;
|
|
setp.gt.f32 %p22, %f475, 0f42FC0000;
|
|
mov.b32 %r54, %f474;
|
|
and.b32 %r55, %r54, -2147483648;
|
|
or.b32 %r56, %r55, 1123811328;
|
|
mov.b32 %f476, %r56;
|
|
selp.f32 %f477, %f476, %f474, %p22;
|
|
mov.f32 %f478, 0fBF317218;
|
|
fma.rn.f32 %f479, %f477, %f478, %f471;
|
|
mov.f32 %f480, 0f3102E308;
|
|
fma.rn.f32 %f481, %f477, %f480, %f479;
|
|
mul.f32 %f482, %f481, 0f3FB8AA3B;
|
|
add.f32 %f483, %f477, 0f4B40007F;
|
|
mov.b32 %r57, %f483;
|
|
shl.b32 %r58, %r57, 23;
|
|
mov.b32 %f484, %r58;
|
|
ex2.approx.ftz.f32 %f485, %f482;
|
|
mul.f32 %f64, %f485, %f484;
|
|
setp.eq.f32 %p23, %f64, 0f7F800000;
|
|
mov.f32 %f1666, 0f7F800000;
|
|
@%p23 bra $L__BB0_9;
|
|
|
|
fma.rn.f32 %f1666, %f64, %f63, %f64;
|
|
|
|
$L__BB0_9:
|
|
setp.lt.f32 %p24, %f61, 0f00000000;
|
|
setp.eq.f32 %p25, %f16, 0f3F800000;
|
|
and.pred %p1, %p24, %p25;
|
|
setp.eq.f32 %p26, %f61, 0f00000000;
|
|
@%p26 bra $L__BB0_13;
|
|
bra.uni $L__BB0_10;
|
|
|
|
$L__BB0_13:
|
|
add.f32 %f490, %f61, %f61;
|
|
selp.f32 %f1668, %f490, 0f00000000, %p25;
|
|
bra.uni $L__BB0_14;
|
|
|
|
$L__BB0_10:
|
|
mov.b32 %r59, %f1666;
|
|
xor.b32 %r60, %r59, -2147483648;
|
|
mov.b32 %f486, %r60;
|
|
selp.f32 %f1668, %f486, %f1666, %p1;
|
|
setp.geu.f32 %p27, %f61, 0f00000000;
|
|
@%p27 bra $L__BB0_14;
|
|
|
|
mov.f32 %f487, 0f40800000;
|
|
cvt.rzi.f32.f32 %f488, %f487;
|
|
setp.eq.f32 %p28, %f488, 0f40800000;
|
|
@%p28 bra $L__BB0_14;
|
|
|
|
mov.f32 %f1668, 0f7FFFFFFF;
|
|
|
|
$L__BB0_14:
|
|
abs.f32 %f1644, %f61;
|
|
add.f32 %f491, %f1644, 0f40800000;
|
|
mov.b32 %r61, %f491;
|
|
setp.lt.s32 %p30, %r61, 2139095040;
|
|
@%p30 bra $L__BB0_19;
|
|
|
|
abs.f32 %f1645, %f61;
|
|
setp.gtu.f32 %p31, %f1645, 0f7F800000;
|
|
@%p31 bra $L__BB0_18;
|
|
bra.uni $L__BB0_16;
|
|
|
|
$L__BB0_18:
|
|
add.f32 %f1668, %f61, 0f40800000;
|
|
bra.uni $L__BB0_19;
|
|
|
|
$L__BB0_16:
|
|
abs.f32 %f1646, %f61;
|
|
setp.neu.f32 %p32, %f1646, 0f7F800000;
|
|
@%p32 bra $L__BB0_19;
|
|
|
|
selp.f32 %f1668, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_19:
|
|
mov.f32 %f492, 0f3F800000;
|
|
sub.f32 %f493, %f492, %f1668;
|
|
setp.eq.f32 %p33, %f61, 0f3F800000;
|
|
selp.f32 %f494, 0f00000000, %f493, %p33;
|
|
cvt.sat.f32.f32 %f495, %f494;
|
|
fma.rn.f32 %f496, %f60, %f60, %f387;
|
|
div.rn.f32 %f73, %f495, %f496;
|
|
mul.f32 %f497, %f1648, %f58;
|
|
fma.rn.f32 %f498, %f1647, %f57, %f497;
|
|
fma.rn.f32 %f499, %f1649, %f59, %f498;
|
|
setp.eq.s32 %p34, %r6, 0;
|
|
selp.f32 %f74, %f499, 0f3F800000, %p34;
|
|
mul.f32 %f500, %f74, 0f40800000;
|
|
cvt.sat.f32.f32 %f75, %f500;
|
|
setp.eq.f32 %p35, %f381, 0f3F800000;
|
|
@%p35 bra $L__BB0_25;
|
|
bra.uni $L__BB0_20;
|
|
|
|
$L__BB0_25:
|
|
setp.eq.s64 %p39, %rd6, 0;
|
|
mov.f32 %f1673, %f391;
|
|
mov.f32 %f1676, %f73;
|
|
@%p39 bra $L__BB0_29;
|
|
|
|
setp.geu.f32 %p40, %f1672, 0f00000000;
|
|
mov.f32 %f1669, %f57;
|
|
mov.f32 %f1670, %f58;
|
|
mov.f32 %f1671, %f59;
|
|
@%p40 bra $L__BB0_28;
|
|
|
|
mul.f32 %f525, %f54, %f404;
|
|
fma.rn.f32 %f526, %f53, %f403, %f525;
|
|
fma.rn.f32 %f528, %f55, %f405, %f526;
|
|
rcp.rn.f32 %f529, %f528;
|
|
mul.f32 %f1669, %f403, %f529;
|
|
mul.f32 %f1670, %f404, %f529;
|
|
mul.f32 %f1671, %f405, %f529;
|
|
neg.f32 %f1672, %f1672;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f530, %f55, %f59;
|
|
mul.f32 %f531, %f54, %f58;
|
|
neg.f32 %f532, %f531;
|
|
mul.f32 %f533, %f53, %f57;
|
|
sub.f32 %f534, %f532, %f533;
|
|
sub.f32 %f535, %f534, %f530;
|
|
setp.gt.f32 %p41, %f535, 0f00000000;
|
|
selp.f32 %f536, 0f3F800000, 0f00000000, %p41;
|
|
mov.f32 %f537, 0f3F800000;
|
|
mul.f32 %f538, %f396, %f1670;
|
|
mul.f32 %f539, %f400, %f1670;
|
|
fma.rn.f32 %f540, %f395, %f1669, %f538;
|
|
fma.rn.f32 %f541, %f399, %f1669, %f539;
|
|
fma.rn.f32 %f542, %f397, %f1671, %f540;
|
|
fma.rn.f32 %f543, %f401, %f1671, %f541;
|
|
fma.rn.f32 %f544, %f1672, %f542, 0f3F000000;
|
|
sub.f32 %f545, %f537, %f544;
|
|
fma.rn.f32 %f546, %f1672, %f543, 0f3F000000;
|
|
tex.2d.v4.f32.f32 {%f547, %f548, %f549, %f550}, [%rd6, {%f545, %f546}];
|
|
mul.f32 %f551, %f536, %f547;
|
|
mul.f32 %f552, %f536, %f548;
|
|
mul.f32 %f553, %f536, %f549;
|
|
mul.f32 %f1673, %f391, %f551;
|
|
mul.f32 %f1674, %f1674, %f552;
|
|
mul.f32 %f1675, %f1675, %f553;
|
|
mov.f32 %f1676, %f73;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_20:
|
|
setp.eq.f32 %p36, %f381, 0f40000000;
|
|
@%p36 bra $L__BB0_23;
|
|
bra.uni $L__BB0_21;
|
|
|
|
$L__BB0_23:
|
|
setp.eq.s64 %p38, %rd6, 0;
|
|
mov.f32 %f1673, %f391;
|
|
mov.f32 %f1676, %f73;
|
|
@%p38 bra $L__BB0_29;
|
|
|
|
mul.f32 %f510, %f396, %f58;
|
|
mul.f32 %f511, %f400, %f58;
|
|
mul.f32 %f512, %f54, %f58;
|
|
fma.rn.f32 %f513, %f395, %f57, %f510;
|
|
fma.rn.f32 %f514, %f399, %f57, %f511;
|
|
fma.rn.f32 %f515, %f53, %f57, %f512;
|
|
fma.rn.f32 %f516, %f397, %f59, %f513;
|
|
fma.rn.f32 %f517, %f401, %f59, %f514;
|
|
fma.rn.f32 %f518, %f55, %f59, %f515;
|
|
tex.cube.v4.f32.f32 {%f519, %f520, %f521, %f522}, [%rd6, {%f516, %f517, %f518, %f518}];
|
|
mul.f32 %f1673, %f391, %f519;
|
|
mul.f32 %f1674, %f1674, %f520;
|
|
mul.f32 %f1675, %f1675, %f521;
|
|
mov.f32 %f1676, %f73;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_21:
|
|
setp.neu.f32 %p37, %f381, 0f40800000;
|
|
mov.f32 %f1673, %f391;
|
|
mov.f32 %f1676, %f73;
|
|
@%p37 bra $L__BB0_29;
|
|
|
|
mul.f32 %f501, %f53, %f57;
|
|
mul.f32 %f502, %f54, %f58;
|
|
neg.f32 %f503, %f502;
|
|
sub.f32 %f504, %f503, %f501;
|
|
mul.f32 %f505, %f55, %f59;
|
|
sub.f32 %f506, %f504, %f505;
|
|
fma.rn.f32 %f507, %f394, %f506, %f1672;
|
|
cvt.sat.f32.f32 %f508, %f507;
|
|
mul.f32 %f509, %f508, %f508;
|
|
mul.f32 %f1676, %f73, %f509;
|
|
mov.f32 %f1673, %f391;
|
|
|
|
$L__BB0_29:
|
|
max.f32 %f569, %f1673, %f1674;
|
|
max.f32 %f570, %f569, %f1675;
|
|
mul.f32 %f571, %f75, %f1676;
|
|
mul.f32 %f572, %f571, %f570;
|
|
setp.lt.f32 %p43, %f572, 0f3727C5AC;
|
|
mov.pred %p209, -1;
|
|
mov.f32 %f1677, 0f00000000;
|
|
mov.f32 %f1678, %f1677;
|
|
mov.f32 %f1679, %f1677;
|
|
mov.f32 %f1680, %f1677;
|
|
mov.f32 %f1681, %f1677;
|
|
mov.f32 %f1682, %f1677;
|
|
mov.f32 %f1683, %f1677;
|
|
mov.f32 %f1684, %f1677;
|
|
mov.f32 %f1685, %f1677;
|
|
mov.f32 %f1686, %f1677;
|
|
mov.f32 %f1687, %f1677;
|
|
mov.f32 %f1688, %f1677;
|
|
mov.f32 %f1689, %f1677;
|
|
mov.f32 %f1690, %f1677;
|
|
mov.f32 %f1691, %f1677;
|
|
@%p43 bra $L__BB0_31;
|
|
|
|
cvt.sat.f32.f32 %f573, %f74;
|
|
mul.f32 %f574, %f1676, %f573;
|
|
mul.f32 %f1677, %f1673, %f574;
|
|
mul.f32 %f1678, %f1674, %f574;
|
|
mul.f32 %f1679, %f1675, %f574;
|
|
mul.f32 %f575, %f1676, 0f3E800000;
|
|
mul.f32 %f576, %f75, %f575;
|
|
mul.f32 %f1680, %f1673, %f576;
|
|
mul.f32 %f1681, %f1674, %f576;
|
|
mul.f32 %f1682, %f1675, %f576;
|
|
mul.f32 %f1683, %f57, %f1680;
|
|
mul.f32 %f1684, %f57, %f1681;
|
|
mul.f32 %f1685, %f57, %f1682;
|
|
mul.f32 %f1686, %f58, %f1680;
|
|
mul.f32 %f1687, %f58, %f1681;
|
|
mul.f32 %f1688, %f58, %f1682;
|
|
mul.f32 %f1689, %f59, %f1680;
|
|
mul.f32 %f1690, %f59, %f1681;
|
|
mul.f32 %f1691, %f59, %f1682;
|
|
mov.pred %p209, 0;
|
|
|
|
$L__BB0_31:
|
|
@%p209 bra $L__BB0_57;
|
|
|
|
setp.eq.s32 %p45, %r44, 0;
|
|
mov.u16 %rs179, 0;
|
|
mov.f32 %f1710, 0f3F800000;
|
|
mov.f32 %f1705, %f1710;
|
|
mov.f32 %f1706, %f1710;
|
|
@%p45 bra $L__BB0_40;
|
|
|
|
abs.s32 %r10, %r44;
|
|
setp.lt.s32 %p46, %r10, 1;
|
|
mov.f32 %f1695, 0f00000000;
|
|
mov.f32 %f1696, %f1695;
|
|
mov.f32 %f1697, %f1695;
|
|
@%p46 bra $L__BB0_39;
|
|
|
|
mov.f32 %f592, 0f38D1B717;
|
|
max.f32 %f593, %f591, %f592;
|
|
and.b32 %r63, %r451, 32;
|
|
setp.eq.s32 %p47, %r63, 0;
|
|
mov.u32 %r450, 0;
|
|
selp.f32 %f594, 0f3F800000, 0f41200000, %p47;
|
|
mul.f32 %f138, %f594, %f593;
|
|
and.b32 %r11, %r10, 1;
|
|
setp.eq.s32 %p48, %r10, 1;
|
|
mov.f32 %f1697, 0f00000000;
|
|
mov.f32 %f1696, %f1697;
|
|
mov.f32 %f1695, %f1697;
|
|
@%p48 bra $L__BB0_37;
|
|
|
|
sub.s32 %r449, %r10, %r11;
|
|
|
|
$L__BB0_36:
|
|
cvt.rn.f32.s32 %f616, %r450;
|
|
mul.f32 %f617, %f616, 0f3DD32618;
|
|
cvt.rmi.f32.f32 %f618, %f617;
|
|
sub.f32 %f619, %f617, %f618;
|
|
mul.f32 %f620, %f616, 0f3DD2F1AA;
|
|
cvt.rmi.f32.f32 %f621, %f620;
|
|
sub.f32 %f622, %f620, %f621;
|
|
mul.f32 %f623, %f616, 0f3DC74539;
|
|
cvt.rmi.f32.f32 %f624, %f623;
|
|
sub.f32 %f625, %f623, %f624;
|
|
add.f32 %f626, %f622, 0f4199851F;
|
|
add.f32 %f627, %f625, 0f4199851F;
|
|
add.f32 %f628, %f619, 0f4199851F;
|
|
mul.f32 %f629, %f622, %f627;
|
|
fma.rn.f32 %f630, %f619, %f626, %f629;
|
|
fma.rn.f32 %f631, %f628, %f625, %f630;
|
|
add.f32 %f632, %f619, %f631;
|
|
add.f32 %f633, %f622, %f631;
|
|
add.f32 %f634, %f625, %f631;
|
|
add.f32 %f635, %f632, %f633;
|
|
mul.f32 %f636, %f634, %f635;
|
|
cvt.rmi.f32.f32 %f637, %f636;
|
|
sub.f32 %f638, %f636, %f637;
|
|
add.f32 %f639, %f632, %f634;
|
|
mul.f32 %f640, %f633, %f639;
|
|
cvt.rmi.f32.f32 %f641, %f640;
|
|
sub.f32 %f642, %f640, %f641;
|
|
add.f32 %f643, %f633, %f634;
|
|
mul.f32 %f644, %f632, %f643;
|
|
cvt.rmi.f32.f32 %f645, %f644;
|
|
sub.f32 %f646, %f644, %f645;
|
|
fma.rn.f32 %f647, %f638, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f648, %f642, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f649, %f646, 0f40000000, 0fBF800000;
|
|
ld.global.f32 %f650, [%rd5+16];
|
|
ld.global.f32 %f651, [%rd5+4];
|
|
fma.rn.f32 %f652, %f650, %f647, %f651;
|
|
ld.global.f32 %f653, [%rd5+8];
|
|
fma.rn.f32 %f654, %f650, %f648, %f653;
|
|
ld.global.f32 %f655, [%rd5+12];
|
|
fma.rn.f32 %f656, %f650, %f649, %f655;
|
|
sub.f32 %f657, %f652, %f10;
|
|
sub.f32 %f658, %f654, %f11;
|
|
sub.f32 %f659, %f656, %f12;
|
|
mul.f32 %f660, %f658, %f658;
|
|
fma.rn.f32 %f661, %f657, %f657, %f660;
|
|
fma.rn.f32 %f662, %f659, %f659, %f661;
|
|
sqrt.rn.f32 %f605, %f662;
|
|
rcp.rn.f32 %f663, %f605;
|
|
mul.f32 %f601, %f663, %f657;
|
|
mul.f32 %f602, %f663, %f658;
|
|
mul.f32 %f603, %f663, %f659;
|
|
mov.f32 %f615, 0f00000000;
|
|
mov.u32 %r172, 2;
|
|
mov.u32 %r173, 1;
|
|
mov.u32 %r174, 3;
|
|
mov.u32 %r177, 1065353216;
|
|
mov.u32 %r206, 0;
|
|
// begin inline asm
|
|
call(%r65,%r66,%r67,%r68,%r69,%r70,%r71,%r72,%r73,%r74,%r75,%r76,%r77,%r78,%r79,%r80,%r81,%r82,%r83,%r84,%r85,%r86,%r87,%r88,%r89,%r90,%r91,%r92,%r93,%r94,%r95,%r96),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f601,%f602,%f603,%f138,%f605,%f615,%r173,%r206,%r173,%r172,%r173,%r174,%r177,%r177,%r177,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f664, %r65;
|
|
mov.b32 %f665, %r66;
|
|
mov.b32 %f666, %r67;
|
|
add.f32 %f667, %f1695, %f664;
|
|
add.f32 %f668, %f1696, %f665;
|
|
add.f32 %f669, %f1697, %f666;
|
|
add.s32 %r207, %r450, 1;
|
|
cvt.rn.f32.s32 %f670, %r207;
|
|
mul.f32 %f671, %f670, 0f3DD32618;
|
|
cvt.rmi.f32.f32 %f672, %f671;
|
|
sub.f32 %f673, %f671, %f672;
|
|
mul.f32 %f674, %f670, 0f3DD2F1AA;
|
|
cvt.rmi.f32.f32 %f675, %f674;
|
|
sub.f32 %f676, %f674, %f675;
|
|
mul.f32 %f677, %f670, 0f3DC74539;
|
|
cvt.rmi.f32.f32 %f678, %f677;
|
|
sub.f32 %f679, %f677, %f678;
|
|
add.f32 %f680, %f676, 0f4199851F;
|
|
add.f32 %f681, %f679, 0f4199851F;
|
|
add.f32 %f682, %f673, 0f4199851F;
|
|
mul.f32 %f683, %f676, %f681;
|
|
fma.rn.f32 %f684, %f673, %f680, %f683;
|
|
fma.rn.f32 %f685, %f682, %f679, %f684;
|
|
add.f32 %f686, %f673, %f685;
|
|
add.f32 %f687, %f676, %f685;
|
|
add.f32 %f688, %f679, %f685;
|
|
add.f32 %f689, %f686, %f687;
|
|
mul.f32 %f690, %f688, %f689;
|
|
cvt.rmi.f32.f32 %f691, %f690;
|
|
sub.f32 %f692, %f690, %f691;
|
|
add.f32 %f693, %f686, %f688;
|
|
mul.f32 %f694, %f687, %f693;
|
|
cvt.rmi.f32.f32 %f695, %f694;
|
|
sub.f32 %f696, %f694, %f695;
|
|
add.f32 %f697, %f687, %f688;
|
|
mul.f32 %f698, %f686, %f697;
|
|
cvt.rmi.f32.f32 %f699, %f698;
|
|
sub.f32 %f700, %f698, %f699;
|
|
fma.rn.f32 %f701, %f692, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f702, %f696, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f703, %f700, 0f40000000, 0fBF800000;
|
|
ld.global.f32 %f704, [%rd5+16];
|
|
ld.global.f32 %f705, [%rd5+4];
|
|
fma.rn.f32 %f706, %f704, %f701, %f705;
|
|
ld.global.f32 %f707, [%rd5+8];
|
|
fma.rn.f32 %f708, %f704, %f702, %f707;
|
|
ld.global.f32 %f709, [%rd5+12];
|
|
fma.rn.f32 %f710, %f704, %f703, %f709;
|
|
sub.f32 %f711, %f706, %f10;
|
|
sub.f32 %f712, %f708, %f11;
|
|
sub.f32 %f713, %f710, %f12;
|
|
mul.f32 %f714, %f712, %f712;
|
|
fma.rn.f32 %f715, %f711, %f711, %f714;
|
|
fma.rn.f32 %f716, %f713, %f713, %f715;
|
|
sqrt.rn.f32 %f614, %f716;
|
|
rcp.rn.f32 %f717, %f614;
|
|
mul.f32 %f610, %f717, %f711;
|
|
mul.f32 %f611, %f717, %f712;
|
|
mul.f32 %f612, %f717, %f713;
|
|
// begin inline asm
|
|
call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f610,%f611,%f612,%f138,%f614,%f615,%r173,%r206,%r173,%r172,%r173,%r174,%r177,%r177,%r177,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f718, %r136;
|
|
mov.b32 %f719, %r137;
|
|
mov.b32 %f720, %r138;
|
|
add.f32 %f1695, %f667, %f718;
|
|
add.f32 %f1696, %f668, %f719;
|
|
add.f32 %f1697, %f669, %f720;
|
|
add.s32 %r450, %r450, 2;
|
|
add.s32 %r449, %r449, -2;
|
|
setp.ne.s32 %p49, %r449, 0;
|
|
@%p49 bra $L__BB0_36;
|
|
|
|
$L__BB0_37:
|
|
setp.eq.s32 %p50, %r11, 0;
|
|
@%p50 bra $L__BB0_39;
|
|
|
|
cvt.rn.f32.s32 %f730, %r450;
|
|
mul.f32 %f731, %f730, 0f3DD32618;
|
|
cvt.rmi.f32.f32 %f732, %f731;
|
|
sub.f32 %f733, %f731, %f732;
|
|
mul.f32 %f734, %f730, 0f3DD2F1AA;
|
|
cvt.rmi.f32.f32 %f735, %f734;
|
|
sub.f32 %f736, %f734, %f735;
|
|
mul.f32 %f737, %f730, 0f3DC74539;
|
|
cvt.rmi.f32.f32 %f738, %f737;
|
|
sub.f32 %f739, %f737, %f738;
|
|
add.f32 %f740, %f736, 0f4199851F;
|
|
add.f32 %f741, %f739, 0f4199851F;
|
|
add.f32 %f742, %f733, 0f4199851F;
|
|
mul.f32 %f743, %f736, %f741;
|
|
fma.rn.f32 %f744, %f733, %f740, %f743;
|
|
fma.rn.f32 %f745, %f742, %f739, %f744;
|
|
add.f32 %f746, %f733, %f745;
|
|
add.f32 %f747, %f736, %f745;
|
|
add.f32 %f748, %f739, %f745;
|
|
add.f32 %f749, %f746, %f747;
|
|
mul.f32 %f750, %f748, %f749;
|
|
cvt.rmi.f32.f32 %f751, %f750;
|
|
sub.f32 %f752, %f750, %f751;
|
|
add.f32 %f753, %f746, %f748;
|
|
mul.f32 %f754, %f747, %f753;
|
|
cvt.rmi.f32.f32 %f755, %f754;
|
|
sub.f32 %f756, %f754, %f755;
|
|
add.f32 %f757, %f747, %f748;
|
|
mul.f32 %f758, %f746, %f757;
|
|
cvt.rmi.f32.f32 %f759, %f758;
|
|
sub.f32 %f760, %f758, %f759;
|
|
fma.rn.f32 %f761, %f752, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f762, %f756, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f763, %f760, 0f40000000, 0fBF800000;
|
|
ld.global.f32 %f764, [%rd5+16];
|
|
ld.global.f32 %f765, [%rd5+4];
|
|
fma.rn.f32 %f766, %f764, %f761, %f765;
|
|
ld.global.f32 %f767, [%rd5+8];
|
|
fma.rn.f32 %f768, %f764, %f762, %f767;
|
|
ld.global.f32 %f769, [%rd5+12];
|
|
fma.rn.f32 %f770, %f764, %f763, %f769;
|
|
sub.f32 %f771, %f766, %f10;
|
|
sub.f32 %f772, %f768, %f11;
|
|
sub.f32 %f773, %f770, %f12;
|
|
mul.f32 %f774, %f772, %f772;
|
|
fma.rn.f32 %f775, %f771, %f771, %f774;
|
|
fma.rn.f32 %f776, %f773, %f773, %f775;
|
|
sqrt.rn.f32 %f728, %f776;
|
|
rcp.rn.f32 %f777, %f728;
|
|
mul.f32 %f724, %f777, %f771;
|
|
mul.f32 %f725, %f777, %f772;
|
|
mul.f32 %f726, %f777, %f773;
|
|
mov.f32 %f729, 0f00000000;
|
|
mov.u32 %r244, 2;
|
|
mov.u32 %r245, 1;
|
|
mov.u32 %r246, 3;
|
|
mov.u32 %r249, 1065353216;
|
|
mov.u32 %r278, 0;
|
|
// begin inline asm
|
|
call(%r208,%r209,%r210,%r211,%r212,%r213,%r214,%r215,%r216,%r217,%r218,%r219,%r220,%r221,%r222,%r223,%r224,%r225,%r226,%r227,%r228,%r229,%r230,%r231,%r232,%r233,%r234,%r235,%r236,%r237,%r238,%r239),_optix_trace_typed_32,(%r278,%rd3,%f13,%f14,%f15,%f724,%f725,%f726,%f138,%f728,%f729,%r245,%r278,%r245,%r244,%r245,%r246,%r249,%r249,%r249,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278);
|
|
// end inline asm
|
|
mov.b32 %f778, %r208;
|
|
mov.b32 %f779, %r209;
|
|
mov.b32 %f780, %r210;
|
|
add.f32 %f1695, %f1695, %f778;
|
|
add.f32 %f1696, %f1696, %f779;
|
|
add.f32 %f1697, %f1697, %f780;
|
|
|
|
$L__BB0_39:
|
|
cvt.rn.f32.s32 %f781, %r10;
|
|
rcp.rn.f32 %f782, %f781;
|
|
mul.f32 %f1710, %f782, %f1695;
|
|
mul.f32 %f1705, %f782, %f1696;
|
|
mul.f32 %f1706, %f782, %f1697;
|
|
shr.u32 %r279, %r44, 31;
|
|
cvt.u16.u32 %rs179, %r279;
|
|
|
|
$L__BB0_40:
|
|
fma.rn.f32 %f1711, %f1677, %f1710, %f1711;
|
|
fma.rn.f32 %f1712, %f1678, %f1705, %f1712;
|
|
fma.rn.f32 %f1713, %f1679, %f1706, %f1713;
|
|
fma.rn.f32 %f1714, %f1680, %f1710, %f1714;
|
|
fma.rn.f32 %f1715, %f1681, %f1705, %f1715;
|
|
fma.rn.f32 %f1716, %f1682, %f1706, %f1716;
|
|
fma.rn.f32 %f1717, %f1683, %f1710, %f1717;
|
|
fma.rn.f32 %f1718, %f1684, %f1705, %f1718;
|
|
fma.rn.f32 %f1719, %f1685, %f1706, %f1719;
|
|
fma.rn.f32 %f1720, %f1686, %f1710, %f1720;
|
|
fma.rn.f32 %f1721, %f1687, %f1705, %f1721;
|
|
fma.rn.f32 %f1722, %f1688, %f1706, %f1722;
|
|
fma.rn.f32 %f1723, %f1689, %f1710, %f1723;
|
|
fma.rn.f32 %f1724, %f1690, %f1705, %f1724;
|
|
fma.rn.f32 %f1725, %f1691, %f1706, %f1725;
|
|
setp.eq.s16 %p51, %rs179, 0;
|
|
@%p51 bra $L__BB0_56;
|
|
|
|
mul.f32 %f784, %f1683, 0f3F000000;
|
|
mul.f32 %f785, %f1686, 0f3F000000;
|
|
mul.f32 %f786, %f785, %f785;
|
|
fma.rn.f32 %f787, %f784, %f784, %f786;
|
|
mul.f32 %f788, %f1689, 0f3F000000;
|
|
fma.rn.f32 %f789, %f788, %f788, %f787;
|
|
sqrt.rn.f32 %f790, %f789;
|
|
rcp.rn.f32 %f791, %f790;
|
|
mov.f32 %f792, 0f3F800000;
|
|
mul.f32 %f793, %f784, %f791;
|
|
mul.f32 %f794, %f785, %f791;
|
|
mul.f32 %f795, %f788, %f791;
|
|
mul.f32 %f796, %f1648, %f794;
|
|
fma.rn.f32 %f797, %f1647, %f793, %f796;
|
|
fma.rn.f32 %f798, %f1649, %f795, %f797;
|
|
fma.rn.f32 %f178, %f798, 0f3F000000, 0f3F000000;
|
|
add.f32 %f799, %f790, %f790;
|
|
div.rn.f32 %f800, %f799, %f1680;
|
|
add.f32 %f179, %f800, 0f3F800000;
|
|
div.rn.f32 %f801, %f790, %f1680;
|
|
sub.f32 %f802, %f792, %f801;
|
|
add.f32 %f803, %f801, 0f3F800000;
|
|
div.rn.f32 %f180, %f802, %f803;
|
|
sub.f32 %f804, %f792, %f180;
|
|
add.f32 %f805, %f179, 0f3F800000;
|
|
mul.f32 %f181, %f804, %f805;
|
|
mul.f32 %f806, %f179, 0f3F000000;
|
|
cvt.rzi.f32.f32 %f807, %f806;
|
|
add.f32 %f808, %f807, %f807;
|
|
sub.f32 %f809, %f179, %f808;
|
|
abs.f32 %f182, %f809;
|
|
abs.f32 %f183, %f178;
|
|
setp.lt.f32 %p52, %f183, 0f00800000;
|
|
mul.f32 %f810, %f183, 0f4B800000;
|
|
selp.f32 %f811, %f810, %f183, %p52;
|
|
selp.f32 %f812, 0fC3170000, 0fC2FE0000, %p52;
|
|
mov.b32 %r280, %f811;
|
|
and.b32 %r281, %r280, 8388607;
|
|
or.b32 %r282, %r281, 1065353216;
|
|
mov.b32 %f813, %r282;
|
|
shr.u32 %r283, %r280, 23;
|
|
cvt.rn.f32.u32 %f814, %r283;
|
|
add.f32 %f815, %f812, %f814;
|
|
setp.gt.f32 %p53, %f813, 0f3FB504F3;
|
|
mul.f32 %f816, %f813, 0f3F000000;
|
|
add.f32 %f817, %f815, 0f3F800000;
|
|
selp.f32 %f818, %f817, %f815, %p53;
|
|
selp.f32 %f819, %f816, %f813, %p53;
|
|
add.f32 %f820, %f819, 0fBF800000;
|
|
add.f32 %f821, %f819, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f822, %f821;
|
|
add.f32 %f823, %f820, %f820;
|
|
mul.f32 %f824, %f823, %f822;
|
|
mul.f32 %f825, %f824, %f824;
|
|
mov.f32 %f826, 0f3C4CAF63;
|
|
mov.f32 %f827, 0f3B18F0FE;
|
|
fma.rn.f32 %f828, %f827, %f825, %f826;
|
|
mov.f32 %f829, 0f3DAAAABD;
|
|
fma.rn.f32 %f830, %f828, %f825, %f829;
|
|
mul.rn.f32 %f831, %f830, %f825;
|
|
mul.rn.f32 %f832, %f831, %f824;
|
|
sub.f32 %f833, %f820, %f824;
|
|
add.f32 %f834, %f833, %f833;
|
|
neg.f32 %f835, %f824;
|
|
fma.rn.f32 %f836, %f835, %f820, %f834;
|
|
mul.rn.f32 %f837, %f822, %f836;
|
|
add.f32 %f838, %f832, %f824;
|
|
sub.f32 %f839, %f824, %f838;
|
|
add.f32 %f840, %f832, %f839;
|
|
add.f32 %f841, %f837, %f840;
|
|
add.f32 %f842, %f838, %f841;
|
|
sub.f32 %f843, %f838, %f842;
|
|
add.f32 %f844, %f841, %f843;
|
|
mov.f32 %f845, 0f3F317200;
|
|
mul.rn.f32 %f846, %f818, %f845;
|
|
mov.f32 %f847, 0f35BFBE8E;
|
|
mul.rn.f32 %f848, %f818, %f847;
|
|
add.f32 %f849, %f846, %f842;
|
|
sub.f32 %f850, %f846, %f849;
|
|
add.f32 %f851, %f842, %f850;
|
|
add.f32 %f852, %f844, %f851;
|
|
add.f32 %f853, %f848, %f852;
|
|
add.f32 %f854, %f849, %f853;
|
|
sub.f32 %f855, %f849, %f854;
|
|
add.f32 %f856, %f853, %f855;
|
|
abs.f32 %f184, %f179;
|
|
setp.gt.f32 %p54, %f184, 0f77F684DF;
|
|
mul.f32 %f857, %f179, 0f39000000;
|
|
selp.f32 %f858, %f857, %f179, %p54;
|
|
mul.rn.f32 %f859, %f858, %f854;
|
|
neg.f32 %f860, %f859;
|
|
fma.rn.f32 %f861, %f858, %f854, %f860;
|
|
fma.rn.f32 %f862, %f858, %f856, %f861;
|
|
mov.f32 %f863, 0f00000000;
|
|
fma.rn.f32 %f864, %f863, %f854, %f862;
|
|
add.rn.f32 %f865, %f859, %f864;
|
|
neg.f32 %f866, %f865;
|
|
add.rn.f32 %f867, %f859, %f866;
|
|
add.rn.f32 %f868, %f867, %f864;
|
|
mov.b32 %r284, %f865;
|
|
setp.eq.s32 %p55, %r284, 1118925336;
|
|
add.s32 %r285, %r284, -1;
|
|
mov.b32 %f869, %r285;
|
|
add.f32 %f870, %f868, 0f37000000;
|
|
selp.f32 %f185, %f870, %f868, %p55;
|
|
selp.f32 %f871, %f869, %f865, %p55;
|
|
mov.f32 %f872, 0f3FB8AA3B;
|
|
mul.rn.f32 %f873, %f871, %f872;
|
|
cvt.rzi.f32.f32 %f874, %f873;
|
|
abs.f32 %f875, %f874;
|
|
setp.gt.f32 %p56, %f875, 0f42FC0000;
|
|
mov.b32 %r286, %f874;
|
|
and.b32 %r287, %r286, -2147483648;
|
|
or.b32 %r288, %r287, 1123811328;
|
|
mov.b32 %f876, %r288;
|
|
selp.f32 %f877, %f876, %f874, %p56;
|
|
mov.f32 %f878, 0fBF317218;
|
|
fma.rn.f32 %f879, %f877, %f878, %f871;
|
|
mov.f32 %f880, 0f3102E308;
|
|
fma.rn.f32 %f881, %f877, %f880, %f879;
|
|
mul.f32 %f882, %f881, 0f3FB8AA3B;
|
|
add.f32 %f883, %f877, 0f4B40007F;
|
|
mov.b32 %r289, %f883;
|
|
shl.b32 %r290, %r289, 23;
|
|
mov.b32 %f884, %r290;
|
|
ex2.approx.ftz.f32 %f885, %f882;
|
|
mul.f32 %f186, %f885, %f884;
|
|
setp.eq.f32 %p57, %f186, 0f7F800000;
|
|
mov.f32 %f1707, 0f7F800000;
|
|
@%p57 bra $L__BB0_43;
|
|
|
|
fma.rn.f32 %f1707, %f186, %f185, %f186;
|
|
|
|
$L__BB0_43:
|
|
setp.lt.f32 %p58, %f178, 0f00000000;
|
|
setp.eq.f32 %p59, %f182, 0f3F800000;
|
|
and.pred %p3, %p59, %p58;
|
|
setp.eq.f32 %p60, %f178, 0f00000000;
|
|
@%p60 bra $L__BB0_47;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_47:
|
|
add.f32 %f889, %f178, %f178;
|
|
mov.b32 %r293, %f889;
|
|
selp.b32 %r294, %r293, 0, %p59;
|
|
or.b32 %r295, %r294, 2139095040;
|
|
setp.lt.f32 %p64, %f179, 0f00000000;
|
|
selp.b32 %r296, %r295, %r294, %p64;
|
|
mov.b32 %f1709, %r296;
|
|
bra.uni $L__BB0_48;
|
|
|
|
$L__BB0_44:
|
|
mov.b32 %r291, %f1707;
|
|
xor.b32 %r292, %r291, -2147483648;
|
|
mov.b32 %f886, %r292;
|
|
selp.f32 %f1709, %f886, %f1707, %p3;
|
|
setp.geu.f32 %p61, %f178, 0f00000000;
|
|
@%p61 bra $L__BB0_48;
|
|
|
|
cvt.rzi.f32.f32 %f887, %f179;
|
|
setp.eq.f32 %p62, %f887, %f179;
|
|
@%p62 bra $L__BB0_48;
|
|
|
|
mov.f32 %f1709, 0f7FFFFFFF;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f890, %f183, %f184;
|
|
mov.b32 %r297, %f890;
|
|
setp.lt.s32 %p65, %r297, 2139095040;
|
|
@%p65 bra $L__BB0_55;
|
|
|
|
setp.gtu.f32 %p66, %f183, 0f7F800000;
|
|
setp.gtu.f32 %p67, %f184, 0f7F800000;
|
|
or.pred %p68, %p66, %p67;
|
|
@%p68 bra $L__BB0_54;
|
|
bra.uni $L__BB0_50;
|
|
|
|
$L__BB0_54:
|
|
add.f32 %f1709, %f179, %f178;
|
|
bra.uni $L__BB0_55;
|
|
|
|
$L__BB0_50:
|
|
setp.eq.f32 %p69, %f184, 0f7F800000;
|
|
@%p69 bra $L__BB0_53;
|
|
bra.uni $L__BB0_51;
|
|
|
|
$L__BB0_53:
|
|
setp.gt.f32 %p72, %f183, 0f3F800000;
|
|
selp.b32 %r301, 2139095040, 0, %p72;
|
|
xor.b32 %r302, %r301, 2139095040;
|
|
setp.lt.f32 %p73, %f179, 0f00000000;
|
|
selp.b32 %r303, %r302, %r301, %p73;
|
|
mov.b32 %f891, %r303;
|
|
setp.eq.f32 %p74, %f178, 0fBF800000;
|
|
selp.f32 %f1709, 0f3F800000, %f891, %p74;
|
|
bra.uni $L__BB0_55;
|
|
|
|
$L__BB0_51:
|
|
setp.neu.f32 %p70, %f183, 0f7F800000;
|
|
@%p70 bra $L__BB0_55;
|
|
|
|
setp.ge.f32 %p71, %f179, 0f00000000;
|
|
selp.b32 %r298, 2139095040, 0, %p71;
|
|
or.b32 %r299, %r298, -2147483648;
|
|
selp.b32 %r300, %r299, %r298, %p3;
|
|
mov.b32 %f1709, %r300;
|
|
|
|
$L__BB0_55:
|
|
setp.eq.f32 %p75, %f179, 0f00000000;
|
|
setp.eq.f32 %p76, %f178, 0f3F800000;
|
|
or.pred %p77, %p75, %p76;
|
|
selp.f32 %f892, 0f3F800000, %f1709, %p77;
|
|
fma.rn.f32 %f893, %f181, %f892, %f180;
|
|
mul.f32 %f894, %f1680, %f893;
|
|
div.rn.f32 %f895, %f894, %f391;
|
|
div.rn.f32 %f896, %f895, %f73;
|
|
cvt.sat.f32.f32 %f897, %f896;
|
|
mul.f32 %f1710, %f1710, %f897;
|
|
|
|
$L__BB0_56:
|
|
add.f32 %f1726, %f1726, %f1710;
|
|
|
|
$L__BB0_57:
|
|
cvt.u64.u32 %rd77, %r447;
|
|
cvt.u32.u64 %r304, %rd77;
|
|
add.s32 %r447, %r304, 1;
|
|
setp.lt.u32 %p78, %r447, %r5;
|
|
@%p78 bra $L__BB0_7;
|
|
bra.uni $L__BB0_59;
|
|
|
|
$L__BB0_58:
|
|
mov.f32 %f1711, 0f00000000;
|
|
ld.const.u32 %r451, [params+104];
|
|
mov.f32 %f1712, %f1711;
|
|
mov.f32 %f1713, %f1711;
|
|
mov.f32 %f1714, %f1711;
|
|
mov.f32 %f1715, %f1711;
|
|
mov.f32 %f1716, %f1711;
|
|
mov.f32 %f1717, %f1711;
|
|
mov.f32 %f1718, %f1711;
|
|
mov.f32 %f1719, %f1711;
|
|
mov.f32 %f1720, %f1711;
|
|
mov.f32 %f1721, %f1711;
|
|
mov.f32 %f1722, %f1711;
|
|
mov.f32 %f1723, %f1711;
|
|
mov.f32 %f1724, %f1711;
|
|
mov.f32 %f1725, %f1711;
|
|
mov.f32 %f1726, %f1711;
|
|
|
|
$L__BB0_59:
|
|
and.b32 %r305, %r451, 8;
|
|
setp.eq.s32 %p79, %r305, 0;
|
|
@%p79 bra $L__BB0_73;
|
|
|
|
cvt.sat.f32.f32 %f231, %f1726;
|
|
ld.const.u64 %rd33, [params+192];
|
|
cvta.to.global.u64 %rd7, %rd33;
|
|
ld.const.u32 %r306, [params+184];
|
|
mad.lo.s32 %r307, %r306, %r4, %r3;
|
|
cvt.u64.u32 %rd8, %r307;
|
|
mov.f32 %f915, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f916, %f915;
|
|
add.f32 %f917, %f916, %f916;
|
|
mov.f32 %f918, 0f3EE8BA2E;
|
|
sub.f32 %f919, %f918, %f917;
|
|
abs.f32 %f232, %f919;
|
|
abs.f32 %f233, %f231;
|
|
setp.lt.f32 %p80, %f233, 0f00800000;
|
|
mul.f32 %f920, %f233, 0f4B800000;
|
|
selp.f32 %f921, %f920, %f233, %p80;
|
|
selp.f32 %f922, 0fC3170000, 0fC2FE0000, %p80;
|
|
mov.b32 %r308, %f921;
|
|
and.b32 %r309, %r308, 8388607;
|
|
or.b32 %r310, %r309, 1065353216;
|
|
mov.b32 %f923, %r310;
|
|
shr.u32 %r311, %r308, 23;
|
|
cvt.rn.f32.u32 %f924, %r311;
|
|
add.f32 %f925, %f922, %f924;
|
|
setp.gt.f32 %p81, %f923, 0f3FB504F3;
|
|
mul.f32 %f926, %f923, 0f3F000000;
|
|
add.f32 %f927, %f925, 0f3F800000;
|
|
selp.f32 %f928, %f927, %f925, %p81;
|
|
selp.f32 %f929, %f926, %f923, %p81;
|
|
add.f32 %f930, %f929, 0fBF800000;
|
|
add.f32 %f931, %f929, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f932, %f931;
|
|
add.f32 %f933, %f930, %f930;
|
|
mul.f32 %f934, %f933, %f932;
|
|
mul.f32 %f935, %f934, %f934;
|
|
mov.f32 %f936, 0f3C4CAF63;
|
|
mov.f32 %f937, 0f3B18F0FE;
|
|
fma.rn.f32 %f938, %f937, %f935, %f936;
|
|
mov.f32 %f939, 0f3DAAAABD;
|
|
fma.rn.f32 %f940, %f938, %f935, %f939;
|
|
mul.rn.f32 %f941, %f940, %f935;
|
|
mul.rn.f32 %f942, %f941, %f934;
|
|
sub.f32 %f943, %f930, %f934;
|
|
add.f32 %f944, %f943, %f943;
|
|
neg.f32 %f945, %f934;
|
|
fma.rn.f32 %f946, %f945, %f930, %f944;
|
|
mul.rn.f32 %f947, %f932, %f946;
|
|
add.f32 %f948, %f942, %f934;
|
|
sub.f32 %f949, %f934, %f948;
|
|
add.f32 %f950, %f942, %f949;
|
|
add.f32 %f951, %f947, %f950;
|
|
add.f32 %f952, %f948, %f951;
|
|
sub.f32 %f953, %f948, %f952;
|
|
add.f32 %f954, %f951, %f953;
|
|
mov.f32 %f955, 0f3F317200;
|
|
mul.rn.f32 %f956, %f928, %f955;
|
|
mov.f32 %f957, 0f35BFBE8E;
|
|
mul.rn.f32 %f958, %f928, %f957;
|
|
add.f32 %f959, %f956, %f952;
|
|
sub.f32 %f960, %f956, %f959;
|
|
add.f32 %f961, %f952, %f960;
|
|
add.f32 %f962, %f954, %f961;
|
|
add.f32 %f963, %f958, %f962;
|
|
add.f32 %f964, %f959, %f963;
|
|
sub.f32 %f965, %f959, %f964;
|
|
add.f32 %f966, %f963, %f965;
|
|
mul.rn.f32 %f967, %f918, %f964;
|
|
neg.f32 %f968, %f967;
|
|
fma.rn.f32 %f969, %f918, %f964, %f968;
|
|
fma.rn.f32 %f970, %f918, %f966, %f969;
|
|
mov.f32 %f971, 0f00000000;
|
|
fma.rn.f32 %f972, %f971, %f964, %f970;
|
|
add.rn.f32 %f973, %f967, %f972;
|
|
neg.f32 %f974, %f973;
|
|
add.rn.f32 %f975, %f967, %f974;
|
|
add.rn.f32 %f976, %f975, %f972;
|
|
mov.b32 %r312, %f973;
|
|
setp.eq.s32 %p82, %r312, 1118925336;
|
|
add.s32 %r313, %r312, -1;
|
|
mov.b32 %f977, %r313;
|
|
add.f32 %f978, %f976, 0f37000000;
|
|
selp.f32 %f234, %f978, %f976, %p82;
|
|
selp.f32 %f979, %f977, %f973, %p82;
|
|
mov.f32 %f980, 0f3FB8AA3B;
|
|
mul.rn.f32 %f981, %f979, %f980;
|
|
cvt.rzi.f32.f32 %f982, %f981;
|
|
abs.f32 %f983, %f982;
|
|
setp.gt.f32 %p83, %f983, 0f42FC0000;
|
|
mov.b32 %r314, %f982;
|
|
and.b32 %r315, %r314, -2147483648;
|
|
or.b32 %r316, %r315, 1123811328;
|
|
mov.b32 %f984, %r316;
|
|
selp.f32 %f985, %f984, %f982, %p83;
|
|
mov.f32 %f986, 0fBF317218;
|
|
fma.rn.f32 %f987, %f985, %f986, %f979;
|
|
mov.f32 %f988, 0f3102E308;
|
|
fma.rn.f32 %f989, %f985, %f988, %f987;
|
|
mul.f32 %f990, %f989, 0f3FB8AA3B;
|
|
add.f32 %f991, %f985, 0f4B40007F;
|
|
mov.b32 %r317, %f991;
|
|
shl.b32 %r318, %r317, 23;
|
|
mov.b32 %f992, %r318;
|
|
ex2.approx.ftz.f32 %f993, %f990;
|
|
mul.f32 %f235, %f993, %f992;
|
|
setp.eq.f32 %p84, %f235, 0f7F800000;
|
|
mov.f32 %f1743, 0f7F800000;
|
|
@%p84 bra $L__BB0_62;
|
|
|
|
fma.rn.f32 %f1743, %f235, %f234, %f235;
|
|
|
|
$L__BB0_62:
|
|
setp.lt.f32 %p85, %f231, 0f00000000;
|
|
setp.eq.f32 %p86, %f232, 0f3F800000;
|
|
and.pred %p4, %p85, %p86;
|
|
setp.eq.f32 %p87, %f231, 0f00000000;
|
|
@%p87 bra $L__BB0_66;
|
|
bra.uni $L__BB0_63;
|
|
|
|
$L__BB0_66:
|
|
add.f32 %f998, %f231, %f231;
|
|
selp.f32 %f1745, %f998, 0f00000000, %p86;
|
|
bra.uni $L__BB0_67;
|
|
|
|
$L__BB0_170:
|
|
mov.f32 %f1607, 0f00000000;
|
|
mov.u32 %r453, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1607;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f1607;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1607;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs116, 0;
|
|
st.global.v4.u16 [%rd16], {%rs113, %rs114, %rs115, %rs116};
|
|
|
|
$L__BB0_171:
|
|
ld.const.u64 %rd65, [params+256];
|
|
cvta.to.global.u64 %rd66, %rd65;
|
|
ld.const.u32 %r439, [params+248];
|
|
mad.lo.s32 %r440, %r439, %r4, %r3;
|
|
mul.wide.u32 %rd67, %r440, 8;
|
|
add.s64 %rd17, %rd66, %rd67;
|
|
setp.eq.s32 %p205, %r453, 0;
|
|
@%p205 bra $L__BB0_173;
|
|
|
|
ld.global.v4.u16 {%rs123, %rs124, %rs125, %rs126}, [%rd17];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1608, %rs123;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1609, %rs124;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1610, %rs125;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1611, %f1608, 0f00000000;
|
|
add.f32 %f1612, %f1609, 0f00000000;
|
|
add.f32 %f1613, %f1610, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f1613;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f1612;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f1611;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs127, 0;
|
|
st.global.v4.u16 [%rd17], {%rs120, %rs121, %rs122, %rs127};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_173:
|
|
mov.f32 %f1616, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1616;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1616;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1616;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs131, 0;
|
|
st.global.v4.u16 [%rd17], {%rs128, %rs129, %rs130, %rs131};
|
|
|
|
$L__BB0_174:
|
|
ld.const.u64 %rd68, [params+272];
|
|
cvta.to.global.u64 %rd69, %rd68;
|
|
ld.const.u32 %r441, [params+264];
|
|
mad.lo.s32 %r442, %r441, %r4, %r3;
|
|
mul.wide.u32 %rd70, %r442, 8;
|
|
add.s64 %rd18, %rd69, %rd70;
|
|
@%p205 bra $L__BB0_176;
|
|
|
|
ld.global.v4.u16 {%rs138, %rs139, %rs140, %rs141}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1617, %rs138;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1618, %rs139;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1619, %rs140;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1620, %f1617, 0f00000000;
|
|
add.f32 %f1621, %f1618, 0f00000000;
|
|
add.f32 %f1622, %f1619, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f1622;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f1621;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1620;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs142, 0;
|
|
st.global.v4.u16 [%rd18], {%rs135, %rs136, %rs137, %rs142};
|
|
bra.uni $L__BB0_177;
|
|
|
|
$L__BB0_176:
|
|
mov.f32 %f1625, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1625;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1625;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1625;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs146, 0;
|
|
st.global.v4.u16 [%rd18], {%rs143, %rs144, %rs145, %rs146};
|
|
|
|
$L__BB0_177:
|
|
ld.const.u64 %rd71, [params+288];
|
|
cvta.to.global.u64 %rd72, %rd71;
|
|
ld.const.u32 %r443, [params+280];
|
|
mad.lo.s32 %r444, %r443, %r4, %r3;
|
|
mul.wide.u32 %rd73, %r444, 8;
|
|
add.s64 %rd19, %rd72, %rd73;
|
|
@%p205 bra $L__BB0_179;
|
|
|
|
ld.global.v4.u16 {%rs153, %rs154, %rs155, %rs156}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1626, %rs153;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1627, %rs154;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1628, %rs155;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1629, %f1626, 0f00000000;
|
|
add.f32 %f1630, %f1627, 0f00000000;
|
|
add.f32 %f1631, %f1628, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f1631;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f1630;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1629;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs157, 0;
|
|
st.global.v4.u16 [%rd19], {%rs150, %rs151, %rs152, %rs157};
|
|
bra.uni $L__BB0_180;
|
|
|
|
$L__BB0_179:
|
|
mov.f32 %f1634, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1634;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1634;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1634;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs161, 0;
|
|
st.global.v4.u16 [%rd19], {%rs158, %rs159, %rs160, %rs161};
|
|
|
|
$L__BB0_180:
|
|
ld.const.u64 %rd74, [params+304];
|
|
cvta.to.global.u64 %rd75, %rd74;
|
|
ld.const.u32 %r445, [params+296];
|
|
mad.lo.s32 %r446, %r445, %r4, %r3;
|
|
mul.wide.u32 %rd76, %r446, 8;
|
|
add.s64 %rd20, %rd75, %rd76;
|
|
@%p205 bra $L__BB0_182;
|
|
|
|
ld.global.v4.u16 {%rs168, %rs169, %rs170, %rs171}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1635, %rs168;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1636, %rs169;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1637, %rs170;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1638, %f1635, 0f00000000;
|
|
add.f32 %f1639, %f1636, 0f00000000;
|
|
add.f32 %f1640, %f1637, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs167, %f1640;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f1639;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1638;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs172, 0;
|
|
st.global.v4.u16 [%rd20], {%rs165, %rs166, %rs167, %rs172};
|
|
bra.uni $L__BB0_183;
|
|
|
|
$L__BB0_182:
|
|
mov.f32 %f1643, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs175, %f1643;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs174, %f1643;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs173, %f1643;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs176, 0;
|
|
st.global.v4.u16 [%rd20], {%rs173, %rs174, %rs175, %rs176};
|
|
bra.uni $L__BB0_183;
|
|
|
|
$L__BB0_63:
|
|
mov.b32 %r319, %f1743;
|
|
xor.b32 %r320, %r319, -2147483648;
|
|
mov.b32 %f994, %r320;
|
|
selp.f32 %f1745, %f994, %f1743, %p4;
|
|
setp.geu.f32 %p88, %f231, 0f00000000;
|
|
@%p88 bra $L__BB0_67;
|
|
|
|
mov.f32 %f995, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f996, %f995;
|
|
setp.eq.f32 %p89, %f996, 0f3EE8BA2E;
|
|
@%p89 bra $L__BB0_67;
|
|
|
|
mov.f32 %f1745, 0f7FFFFFFF;
|
|
|
|
$L__BB0_67:
|
|
add.f32 %f999, %f233, 0f3EE8BA2E;
|
|
mov.b32 %r321, %f999;
|
|
setp.lt.s32 %p91, %r321, 2139095040;
|
|
@%p91 bra $L__BB0_72;
|
|
|
|
setp.gtu.f32 %p92, %f233, 0f7F800000;
|
|
@%p92 bra $L__BB0_71;
|
|
bra.uni $L__BB0_69;
|
|
|
|
$L__BB0_71:
|
|
add.f32 %f1745, %f231, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_69:
|
|
setp.neu.f32 %p93, %f233, 0f7F800000;
|
|
@%p93 bra $L__BB0_72;
|
|
|
|
selp.f32 %f1745, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_72:
|
|
mul.f32 %f1000, %f1745, 0f437F0000;
|
|
setp.eq.f32 %p94, %f231, 0f3F800000;
|
|
selp.f32 %f1001, 0f437F0000, %f1000, %p94;
|
|
cvt.rzi.u32.f32 %r322, %f1001;
|
|
shl.b64 %rd34, %rd8, 1;
|
|
add.s64 %rd35, %rd7, %rd34;
|
|
cvt.u16.u32 %rs18, %r322;
|
|
mov.u16 %rs19, 255;
|
|
st.global.v2.u8 [%rd35], {%rs18, %rs19};
|
|
|
|
$L__BB0_73:
|
|
and.b32 %r323, %r451, 1;
|
|
setp.eq.b32 %p95, %r323, 1;
|
|
mov.pred %p96, 0;
|
|
xor.pred %p97, %p95, %p96;
|
|
not.pred %p98, %p97;
|
|
@%p98 bra $L__BB0_147;
|
|
|
|
mov.f32 %f1003, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1004, %f1003;
|
|
add.f32 %f1005, %f1004, %f1004;
|
|
mov.f32 %f1006, 0f3EE66666;
|
|
sub.f32 %f1007, %f1006, %f1005;
|
|
abs.f32 %f244, %f1007;
|
|
abs.f32 %f245, %f1711;
|
|
setp.lt.f32 %p99, %f245, 0f00800000;
|
|
mul.f32 %f1008, %f245, 0f4B800000;
|
|
selp.f32 %f1009, %f1008, %f245, %p99;
|
|
selp.f32 %f1010, 0fC3170000, 0fC2FE0000, %p99;
|
|
mov.b32 %r324, %f1009;
|
|
and.b32 %r325, %r324, 8388607;
|
|
or.b32 %r326, %r325, 1065353216;
|
|
mov.b32 %f1011, %r326;
|
|
shr.u32 %r327, %r324, 23;
|
|
cvt.rn.f32.u32 %f1012, %r327;
|
|
add.f32 %f1013, %f1010, %f1012;
|
|
setp.gt.f32 %p100, %f1011, 0f3FB504F3;
|
|
mul.f32 %f1014, %f1011, 0f3F000000;
|
|
add.f32 %f1015, %f1013, 0f3F800000;
|
|
selp.f32 %f1016, %f1015, %f1013, %p100;
|
|
selp.f32 %f1017, %f1014, %f1011, %p100;
|
|
add.f32 %f1018, %f1017, 0fBF800000;
|
|
add.f32 %f1019, %f1017, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1020, %f1019;
|
|
add.f32 %f1021, %f1018, %f1018;
|
|
mul.f32 %f1022, %f1021, %f1020;
|
|
mul.f32 %f1023, %f1022, %f1022;
|
|
mov.f32 %f1024, 0f3C4CAF63;
|
|
mov.f32 %f1025, 0f3B18F0FE;
|
|
fma.rn.f32 %f1026, %f1025, %f1023, %f1024;
|
|
mov.f32 %f1027, 0f3DAAAABD;
|
|
fma.rn.f32 %f1028, %f1026, %f1023, %f1027;
|
|
mul.rn.f32 %f1029, %f1028, %f1023;
|
|
mul.rn.f32 %f1030, %f1029, %f1022;
|
|
sub.f32 %f1031, %f1018, %f1022;
|
|
add.f32 %f1032, %f1031, %f1031;
|
|
neg.f32 %f1033, %f1022;
|
|
fma.rn.f32 %f1034, %f1033, %f1018, %f1032;
|
|
mul.rn.f32 %f1035, %f1020, %f1034;
|
|
add.f32 %f1036, %f1030, %f1022;
|
|
sub.f32 %f1037, %f1022, %f1036;
|
|
add.f32 %f1038, %f1030, %f1037;
|
|
add.f32 %f1039, %f1035, %f1038;
|
|
add.f32 %f1040, %f1036, %f1039;
|
|
sub.f32 %f1041, %f1036, %f1040;
|
|
add.f32 %f1042, %f1039, %f1041;
|
|
mov.f32 %f1043, 0f3F317200;
|
|
mul.rn.f32 %f1044, %f1016, %f1043;
|
|
mov.f32 %f1045, 0f35BFBE8E;
|
|
mul.rn.f32 %f1046, %f1016, %f1045;
|
|
add.f32 %f1047, %f1044, %f1040;
|
|
sub.f32 %f1048, %f1044, %f1047;
|
|
add.f32 %f1049, %f1040, %f1048;
|
|
add.f32 %f1050, %f1042, %f1049;
|
|
add.f32 %f1051, %f1046, %f1050;
|
|
add.f32 %f1052, %f1047, %f1051;
|
|
sub.f32 %f1053, %f1047, %f1052;
|
|
add.f32 %f1054, %f1051, %f1053;
|
|
mul.rn.f32 %f1055, %f1006, %f1052;
|
|
neg.f32 %f1056, %f1055;
|
|
fma.rn.f32 %f1057, %f1006, %f1052, %f1056;
|
|
fma.rn.f32 %f1058, %f1006, %f1054, %f1057;
|
|
mov.f32 %f1059, 0f00000000;
|
|
fma.rn.f32 %f1060, %f1059, %f1052, %f1058;
|
|
add.rn.f32 %f1061, %f1055, %f1060;
|
|
neg.f32 %f1062, %f1061;
|
|
add.rn.f32 %f1063, %f1055, %f1062;
|
|
add.rn.f32 %f1064, %f1063, %f1060;
|
|
mov.b32 %r328, %f1061;
|
|
setp.eq.s32 %p101, %r328, 1118925336;
|
|
add.s32 %r329, %r328, -1;
|
|
mov.b32 %f1065, %r329;
|
|
add.f32 %f1066, %f1064, 0f37000000;
|
|
selp.f32 %f246, %f1066, %f1064, %p101;
|
|
selp.f32 %f1067, %f1065, %f1061, %p101;
|
|
mov.f32 %f1068, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1069, %f1067, %f1068;
|
|
cvt.rzi.f32.f32 %f1070, %f1069;
|
|
abs.f32 %f1071, %f1070;
|
|
setp.gt.f32 %p102, %f1071, 0f42FC0000;
|
|
mov.b32 %r330, %f1070;
|
|
and.b32 %r331, %r330, -2147483648;
|
|
or.b32 %r332, %r331, 1123811328;
|
|
mov.b32 %f1072, %r332;
|
|
selp.f32 %f1073, %f1072, %f1070, %p102;
|
|
mov.f32 %f1074, 0fBF317218;
|
|
fma.rn.f32 %f1075, %f1073, %f1074, %f1067;
|
|
mov.f32 %f1076, 0f3102E308;
|
|
fma.rn.f32 %f1077, %f1073, %f1076, %f1075;
|
|
mul.f32 %f1078, %f1077, 0f3FB8AA3B;
|
|
add.f32 %f1079, %f1073, 0f4B40007F;
|
|
mov.b32 %r333, %f1079;
|
|
shl.b32 %r334, %r333, 23;
|
|
mov.b32 %f1080, %r334;
|
|
ex2.approx.ftz.f32 %f1081, %f1078;
|
|
mul.f32 %f247, %f1081, %f1080;
|
|
setp.eq.f32 %p103, %f247, 0f7F800000;
|
|
mov.f32 %f1746, 0f7F800000;
|
|
@%p103 bra $L__BB0_76;
|
|
|
|
fma.rn.f32 %f1746, %f247, %f246, %f247;
|
|
|
|
$L__BB0_76:
|
|
setp.lt.f32 %p104, %f1711, 0f00000000;
|
|
setp.eq.f32 %p105, %f244, 0f3F800000;
|
|
and.pred %p5, %p104, %p105;
|
|
setp.eq.f32 %p106, %f1711, 0f00000000;
|
|
@%p106 bra $L__BB0_80;
|
|
bra.uni $L__BB0_77;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f1086, %f1711, %f1711;
|
|
selp.f32 %f1748, %f1086, 0f00000000, %p105;
|
|
bra.uni $L__BB0_81;
|
|
|
|
$L__BB0_77:
|
|
mov.b32 %r335, %f1746;
|
|
xor.b32 %r336, %r335, -2147483648;
|
|
mov.b32 %f1082, %r336;
|
|
selp.f32 %f1748, %f1082, %f1746, %p5;
|
|
setp.geu.f32 %p107, %f1711, 0f00000000;
|
|
@%p107 bra $L__BB0_81;
|
|
|
|
mov.f32 %f1083, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1084, %f1083;
|
|
setp.eq.f32 %p108, %f1084, 0f3EE66666;
|
|
@%p108 bra $L__BB0_81;
|
|
|
|
mov.f32 %f1748, 0f7FFFFFFF;
|
|
|
|
$L__BB0_81:
|
|
add.f32 %f1087, %f245, 0f3EE66666;
|
|
mov.b32 %r337, %f1087;
|
|
setp.lt.s32 %p110, %r337, 2139095040;
|
|
@%p110 bra $L__BB0_86;
|
|
|
|
setp.gtu.f32 %p111, %f245, 0f7F800000;
|
|
@%p111 bra $L__BB0_85;
|
|
bra.uni $L__BB0_83;
|
|
|
|
$L__BB0_85:
|
|
add.f32 %f1748, %f1711, 0f3EE66666;
|
|
bra.uni $L__BB0_86;
|
|
|
|
$L__BB0_83:
|
|
setp.neu.f32 %p112, %f245, 0f7F800000;
|
|
@%p112 bra $L__BB0_86;
|
|
|
|
selp.f32 %f1748, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_86:
|
|
setp.eq.f32 %p113, %f1711, 0f3F800000;
|
|
selp.f32 %f256, 0f3F800000, %f1748, %p113;
|
|
abs.f32 %f257, %f1712;
|
|
setp.lt.f32 %p114, %f257, 0f00800000;
|
|
mul.f32 %f1089, %f257, 0f4B800000;
|
|
selp.f32 %f1090, %f1089, %f257, %p114;
|
|
selp.f32 %f1091, 0fC3170000, 0fC2FE0000, %p114;
|
|
mov.b32 %r338, %f1090;
|
|
and.b32 %r339, %r338, 8388607;
|
|
or.b32 %r340, %r339, 1065353216;
|
|
mov.b32 %f1092, %r340;
|
|
shr.u32 %r341, %r338, 23;
|
|
cvt.rn.f32.u32 %f1093, %r341;
|
|
add.f32 %f1094, %f1091, %f1093;
|
|
setp.gt.f32 %p115, %f1092, 0f3FB504F3;
|
|
mul.f32 %f1095, %f1092, 0f3F000000;
|
|
add.f32 %f1096, %f1094, 0f3F800000;
|
|
selp.f32 %f1097, %f1096, %f1094, %p115;
|
|
selp.f32 %f1098, %f1095, %f1092, %p115;
|
|
add.f32 %f1099, %f1098, 0fBF800000;
|
|
add.f32 %f1100, %f1098, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1101, %f1100;
|
|
add.f32 %f1102, %f1099, %f1099;
|
|
mul.f32 %f1103, %f1102, %f1101;
|
|
mul.f32 %f1104, %f1103, %f1103;
|
|
mov.f32 %f1105, 0f3C4CAF63;
|
|
mov.f32 %f1106, 0f3B18F0FE;
|
|
fma.rn.f32 %f1107, %f1106, %f1104, %f1105;
|
|
mov.f32 %f1108, 0f3DAAAABD;
|
|
fma.rn.f32 %f1109, %f1107, %f1104, %f1108;
|
|
mul.rn.f32 %f1110, %f1109, %f1104;
|
|
mul.rn.f32 %f1111, %f1110, %f1103;
|
|
sub.f32 %f1112, %f1099, %f1103;
|
|
add.f32 %f1113, %f1112, %f1112;
|
|
neg.f32 %f1114, %f1103;
|
|
fma.rn.f32 %f1115, %f1114, %f1099, %f1113;
|
|
mul.rn.f32 %f1116, %f1101, %f1115;
|
|
add.f32 %f1117, %f1111, %f1103;
|
|
sub.f32 %f1118, %f1103, %f1117;
|
|
add.f32 %f1119, %f1111, %f1118;
|
|
add.f32 %f1120, %f1116, %f1119;
|
|
add.f32 %f1121, %f1117, %f1120;
|
|
sub.f32 %f1122, %f1117, %f1121;
|
|
add.f32 %f1123, %f1120, %f1122;
|
|
mov.f32 %f1124, 0f3F317200;
|
|
mul.rn.f32 %f1125, %f1097, %f1124;
|
|
mov.f32 %f1126, 0f35BFBE8E;
|
|
mul.rn.f32 %f1127, %f1097, %f1126;
|
|
add.f32 %f1128, %f1125, %f1121;
|
|
sub.f32 %f1129, %f1125, %f1128;
|
|
add.f32 %f1130, %f1121, %f1129;
|
|
add.f32 %f1131, %f1123, %f1130;
|
|
add.f32 %f1132, %f1127, %f1131;
|
|
add.f32 %f1133, %f1128, %f1132;
|
|
sub.f32 %f1134, %f1128, %f1133;
|
|
add.f32 %f1135, %f1132, %f1134;
|
|
mov.f32 %f1136, 0f3EE66666;
|
|
mul.rn.f32 %f1137, %f1136, %f1133;
|
|
neg.f32 %f1138, %f1137;
|
|
fma.rn.f32 %f1139, %f1136, %f1133, %f1138;
|
|
fma.rn.f32 %f1140, %f1136, %f1135, %f1139;
|
|
mov.f32 %f1141, 0f00000000;
|
|
fma.rn.f32 %f1142, %f1141, %f1133, %f1140;
|
|
add.rn.f32 %f1143, %f1137, %f1142;
|
|
neg.f32 %f1144, %f1143;
|
|
add.rn.f32 %f1145, %f1137, %f1144;
|
|
add.rn.f32 %f1146, %f1145, %f1142;
|
|
mov.b32 %r342, %f1143;
|
|
setp.eq.s32 %p116, %r342, 1118925336;
|
|
add.s32 %r343, %r342, -1;
|
|
mov.b32 %f1147, %r343;
|
|
add.f32 %f1148, %f1146, 0f37000000;
|
|
selp.f32 %f258, %f1148, %f1146, %p116;
|
|
selp.f32 %f1149, %f1147, %f1143, %p116;
|
|
mov.f32 %f1150, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1151, %f1149, %f1150;
|
|
cvt.rzi.f32.f32 %f1152, %f1151;
|
|
abs.f32 %f1153, %f1152;
|
|
setp.gt.f32 %p117, %f1153, 0f42FC0000;
|
|
mov.b32 %r344, %f1152;
|
|
and.b32 %r345, %r344, -2147483648;
|
|
or.b32 %r346, %r345, 1123811328;
|
|
mov.b32 %f1154, %r346;
|
|
selp.f32 %f1155, %f1154, %f1152, %p117;
|
|
mov.f32 %f1156, 0fBF317218;
|
|
fma.rn.f32 %f1157, %f1155, %f1156, %f1149;
|
|
mov.f32 %f1158, 0f3102E308;
|
|
fma.rn.f32 %f1159, %f1155, %f1158, %f1157;
|
|
mul.f32 %f1160, %f1159, 0f3FB8AA3B;
|
|
add.f32 %f1161, %f1155, 0f4B40007F;
|
|
mov.b32 %r347, %f1161;
|
|
shl.b32 %r348, %r347, 23;
|
|
mov.b32 %f1162, %r348;
|
|
ex2.approx.ftz.f32 %f1163, %f1160;
|
|
mul.f32 %f259, %f1163, %f1162;
|
|
setp.eq.f32 %p118, %f259, 0f7F800000;
|
|
mov.f32 %f1749, 0f7F800000;
|
|
@%p118 bra $L__BB0_88;
|
|
|
|
fma.rn.f32 %f1749, %f259, %f258, %f259;
|
|
|
|
$L__BB0_88:
|
|
setp.lt.f32 %p119, %f1712, 0f00000000;
|
|
and.pred %p6, %p119, %p105;
|
|
setp.eq.f32 %p121, %f1712, 0f00000000;
|
|
@%p121 bra $L__BB0_92;
|
|
bra.uni $L__BB0_89;
|
|
|
|
$L__BB0_92:
|
|
add.f32 %f1168, %f1712, %f1712;
|
|
selp.f32 %f1751, %f1168, 0f00000000, %p105;
|
|
bra.uni $L__BB0_93;
|
|
|
|
$L__BB0_89:
|
|
mov.b32 %r349, %f1749;
|
|
xor.b32 %r350, %r349, -2147483648;
|
|
mov.b32 %f1164, %r350;
|
|
selp.f32 %f1751, %f1164, %f1749, %p6;
|
|
setp.geu.f32 %p122, %f1712, 0f00000000;
|
|
@%p122 bra $L__BB0_93;
|
|
|
|
mov.f32 %f1165, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1166, %f1165;
|
|
setp.eq.f32 %p123, %f1166, 0f3EE66666;
|
|
@%p123 bra $L__BB0_93;
|
|
|
|
mov.f32 %f1751, 0f7FFFFFFF;
|
|
|
|
$L__BB0_93:
|
|
add.f32 %f1169, %f257, 0f3EE66666;
|
|
mov.b32 %r351, %f1169;
|
|
setp.lt.s32 %p125, %r351, 2139095040;
|
|
@%p125 bra $L__BB0_98;
|
|
|
|
setp.gtu.f32 %p126, %f257, 0f7F800000;
|
|
@%p126 bra $L__BB0_97;
|
|
bra.uni $L__BB0_95;
|
|
|
|
$L__BB0_97:
|
|
add.f32 %f1751, %f1712, 0f3EE66666;
|
|
bra.uni $L__BB0_98;
|
|
|
|
$L__BB0_95:
|
|
setp.neu.f32 %p127, %f257, 0f7F800000;
|
|
@%p127 bra $L__BB0_98;
|
|
|
|
selp.f32 %f1751, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_98:
|
|
setp.eq.f32 %p128, %f1712, 0f3F800000;
|
|
selp.f32 %f268, 0f3F800000, %f1751, %p128;
|
|
abs.f32 %f269, %f1713;
|
|
setp.lt.f32 %p129, %f269, 0f00800000;
|
|
mul.f32 %f1171, %f269, 0f4B800000;
|
|
selp.f32 %f1172, %f1171, %f269, %p129;
|
|
selp.f32 %f1173, 0fC3170000, 0fC2FE0000, %p129;
|
|
mov.b32 %r352, %f1172;
|
|
and.b32 %r353, %r352, 8388607;
|
|
or.b32 %r354, %r353, 1065353216;
|
|
mov.b32 %f1174, %r354;
|
|
shr.u32 %r355, %r352, 23;
|
|
cvt.rn.f32.u32 %f1175, %r355;
|
|
add.f32 %f1176, %f1173, %f1175;
|
|
setp.gt.f32 %p130, %f1174, 0f3FB504F3;
|
|
mul.f32 %f1177, %f1174, 0f3F000000;
|
|
add.f32 %f1178, %f1176, 0f3F800000;
|
|
selp.f32 %f1179, %f1178, %f1176, %p130;
|
|
selp.f32 %f1180, %f1177, %f1174, %p130;
|
|
add.f32 %f1181, %f1180, 0fBF800000;
|
|
add.f32 %f1182, %f1180, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1183, %f1182;
|
|
add.f32 %f1184, %f1181, %f1181;
|
|
mul.f32 %f1185, %f1184, %f1183;
|
|
mul.f32 %f1186, %f1185, %f1185;
|
|
mov.f32 %f1187, 0f3C4CAF63;
|
|
mov.f32 %f1188, 0f3B18F0FE;
|
|
fma.rn.f32 %f1189, %f1188, %f1186, %f1187;
|
|
mov.f32 %f1190, 0f3DAAAABD;
|
|
fma.rn.f32 %f1191, %f1189, %f1186, %f1190;
|
|
mul.rn.f32 %f1192, %f1191, %f1186;
|
|
mul.rn.f32 %f1193, %f1192, %f1185;
|
|
sub.f32 %f1194, %f1181, %f1185;
|
|
add.f32 %f1195, %f1194, %f1194;
|
|
neg.f32 %f1196, %f1185;
|
|
fma.rn.f32 %f1197, %f1196, %f1181, %f1195;
|
|
mul.rn.f32 %f1198, %f1183, %f1197;
|
|
add.f32 %f1199, %f1193, %f1185;
|
|
sub.f32 %f1200, %f1185, %f1199;
|
|
add.f32 %f1201, %f1193, %f1200;
|
|
add.f32 %f1202, %f1198, %f1201;
|
|
add.f32 %f1203, %f1199, %f1202;
|
|
sub.f32 %f1204, %f1199, %f1203;
|
|
add.f32 %f1205, %f1202, %f1204;
|
|
mov.f32 %f1206, 0f3F317200;
|
|
mul.rn.f32 %f1207, %f1179, %f1206;
|
|
mov.f32 %f1208, 0f35BFBE8E;
|
|
mul.rn.f32 %f1209, %f1179, %f1208;
|
|
add.f32 %f1210, %f1207, %f1203;
|
|
sub.f32 %f1211, %f1207, %f1210;
|
|
add.f32 %f1212, %f1203, %f1211;
|
|
add.f32 %f1213, %f1205, %f1212;
|
|
add.f32 %f1214, %f1209, %f1213;
|
|
add.f32 %f1215, %f1210, %f1214;
|
|
sub.f32 %f1216, %f1210, %f1215;
|
|
add.f32 %f1217, %f1214, %f1216;
|
|
mov.f32 %f1218, 0f3EE66666;
|
|
mul.rn.f32 %f1219, %f1218, %f1215;
|
|
neg.f32 %f1220, %f1219;
|
|
fma.rn.f32 %f1221, %f1218, %f1215, %f1220;
|
|
fma.rn.f32 %f1222, %f1218, %f1217, %f1221;
|
|
mov.f32 %f1223, 0f00000000;
|
|
fma.rn.f32 %f1224, %f1223, %f1215, %f1222;
|
|
add.rn.f32 %f1225, %f1219, %f1224;
|
|
neg.f32 %f1226, %f1225;
|
|
add.rn.f32 %f1227, %f1219, %f1226;
|
|
add.rn.f32 %f1228, %f1227, %f1224;
|
|
mov.b32 %r356, %f1225;
|
|
setp.eq.s32 %p131, %r356, 1118925336;
|
|
add.s32 %r357, %r356, -1;
|
|
mov.b32 %f1229, %r357;
|
|
add.f32 %f1230, %f1228, 0f37000000;
|
|
selp.f32 %f270, %f1230, %f1228, %p131;
|
|
selp.f32 %f1231, %f1229, %f1225, %p131;
|
|
mov.f32 %f1232, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1233, %f1231, %f1232;
|
|
cvt.rzi.f32.f32 %f1234, %f1233;
|
|
abs.f32 %f1235, %f1234;
|
|
setp.gt.f32 %p132, %f1235, 0f42FC0000;
|
|
mov.b32 %r358, %f1234;
|
|
and.b32 %r359, %r358, -2147483648;
|
|
or.b32 %r360, %r359, 1123811328;
|
|
mov.b32 %f1236, %r360;
|
|
selp.f32 %f1237, %f1236, %f1234, %p132;
|
|
mov.f32 %f1238, 0fBF317218;
|
|
fma.rn.f32 %f1239, %f1237, %f1238, %f1231;
|
|
mov.f32 %f1240, 0f3102E308;
|
|
fma.rn.f32 %f1241, %f1237, %f1240, %f1239;
|
|
mul.f32 %f1242, %f1241, 0f3FB8AA3B;
|
|
add.f32 %f1243, %f1237, 0f4B40007F;
|
|
mov.b32 %r361, %f1243;
|
|
shl.b32 %r362, %r361, 23;
|
|
mov.b32 %f1244, %r362;
|
|
ex2.approx.ftz.f32 %f1245, %f1242;
|
|
mul.f32 %f271, %f1245, %f1244;
|
|
setp.eq.f32 %p133, %f271, 0f7F800000;
|
|
mov.f32 %f1752, 0f7F800000;
|
|
@%p133 bra $L__BB0_100;
|
|
|
|
fma.rn.f32 %f1752, %f271, %f270, %f271;
|
|
|
|
$L__BB0_100:
|
|
setp.lt.f32 %p134, %f1713, 0f00000000;
|
|
and.pred %p7, %p134, %p105;
|
|
setp.eq.f32 %p136, %f1713, 0f00000000;
|
|
@%p136 bra $L__BB0_104;
|
|
bra.uni $L__BB0_101;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f1250, %f1713, %f1713;
|
|
selp.f32 %f1754, %f1250, 0f00000000, %p105;
|
|
bra.uni $L__BB0_105;
|
|
|
|
$L__BB0_101:
|
|
mov.b32 %r363, %f1752;
|
|
xor.b32 %r364, %r363, -2147483648;
|
|
mov.b32 %f1246, %r364;
|
|
selp.f32 %f1754, %f1246, %f1752, %p7;
|
|
setp.geu.f32 %p137, %f1713, 0f00000000;
|
|
@%p137 bra $L__BB0_105;
|
|
|
|
mov.f32 %f1247, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1248, %f1247;
|
|
setp.eq.f32 %p138, %f1248, 0f3EE66666;
|
|
@%p138 bra $L__BB0_105;
|
|
|
|
mov.f32 %f1754, 0f7FFFFFFF;
|
|
|
|
$L__BB0_105:
|
|
add.f32 %f1251, %f269, 0f3EE66666;
|
|
mov.b32 %r365, %f1251;
|
|
setp.lt.s32 %p140, %r365, 2139095040;
|
|
@%p140 bra $L__BB0_110;
|
|
|
|
setp.gtu.f32 %p141, %f269, 0f7F800000;
|
|
@%p141 bra $L__BB0_109;
|
|
bra.uni $L__BB0_107;
|
|
|
|
$L__BB0_109:
|
|
add.f32 %f1754, %f1713, 0f3EE66666;
|
|
bra.uni $L__BB0_110;
|
|
|
|
$L__BB0_107:
|
|
setp.neu.f32 %p142, %f269, 0f7F800000;
|
|
@%p142 bra $L__BB0_110;
|
|
|
|
selp.f32 %f1754, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_110:
|
|
setp.eq.f32 %p143, %f1713, 0f3F800000;
|
|
mov.f32 %f1253, 0f3F800000;
|
|
selp.f32 %f1254, 0f3F800000, %f1754, %p143;
|
|
ld.const.u64 %rd36, [params+144];
|
|
cvta.to.global.u64 %rd9, %rd36;
|
|
ld.const.u32 %r366, [params+136];
|
|
mad.lo.s32 %r367, %r366, %r4, %r3;
|
|
cvt.u64.u32 %rd10, %r367;
|
|
min.f32 %f1255, %f256, %f1253;
|
|
mov.f32 %f1256, 0f00000000;
|
|
max.f32 %f280, %f1256, %f1255;
|
|
min.f32 %f1257, %f268, %f1253;
|
|
max.f32 %f281, %f1256, %f1257;
|
|
min.f32 %f1258, %f1254, %f1253;
|
|
max.f32 %f282, %f1256, %f1258;
|
|
mov.f32 %f1259, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1260, %f1259;
|
|
add.f32 %f1261, %f1260, %f1260;
|
|
mov.f32 %f1262, 0f3ED55555;
|
|
sub.f32 %f1263, %f1262, %f1261;
|
|
abs.f32 %f283, %f1263;
|
|
abs.f32 %f284, %f280;
|
|
setp.lt.f32 %p144, %f284, 0f00800000;
|
|
mul.f32 %f1264, %f284, 0f4B800000;
|
|
selp.f32 %f1265, %f1264, %f284, %p144;
|
|
selp.f32 %f1266, 0fC3170000, 0fC2FE0000, %p144;
|
|
mov.b32 %r368, %f1265;
|
|
and.b32 %r369, %r368, 8388607;
|
|
or.b32 %r370, %r369, 1065353216;
|
|
mov.b32 %f1267, %r370;
|
|
shr.u32 %r371, %r368, 23;
|
|
cvt.rn.f32.u32 %f1268, %r371;
|
|
add.f32 %f1269, %f1266, %f1268;
|
|
setp.gt.f32 %p145, %f1267, 0f3FB504F3;
|
|
mul.f32 %f1270, %f1267, 0f3F000000;
|
|
add.f32 %f1271, %f1269, 0f3F800000;
|
|
selp.f32 %f1272, %f1271, %f1269, %p145;
|
|
selp.f32 %f1273, %f1270, %f1267, %p145;
|
|
add.f32 %f1274, %f1273, 0fBF800000;
|
|
add.f32 %f1275, %f1273, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1276, %f1275;
|
|
add.f32 %f1277, %f1274, %f1274;
|
|
mul.f32 %f1278, %f1277, %f1276;
|
|
mul.f32 %f1279, %f1278, %f1278;
|
|
mov.f32 %f1280, 0f3C4CAF63;
|
|
mov.f32 %f1281, 0f3B18F0FE;
|
|
fma.rn.f32 %f1282, %f1281, %f1279, %f1280;
|
|
mov.f32 %f1283, 0f3DAAAABD;
|
|
fma.rn.f32 %f1284, %f1282, %f1279, %f1283;
|
|
mul.rn.f32 %f1285, %f1284, %f1279;
|
|
mul.rn.f32 %f1286, %f1285, %f1278;
|
|
sub.f32 %f1287, %f1274, %f1278;
|
|
add.f32 %f1288, %f1287, %f1287;
|
|
neg.f32 %f1289, %f1278;
|
|
fma.rn.f32 %f1290, %f1289, %f1274, %f1288;
|
|
mul.rn.f32 %f1291, %f1276, %f1290;
|
|
add.f32 %f1292, %f1286, %f1278;
|
|
sub.f32 %f1293, %f1278, %f1292;
|
|
add.f32 %f1294, %f1286, %f1293;
|
|
add.f32 %f1295, %f1291, %f1294;
|
|
add.f32 %f1296, %f1292, %f1295;
|
|
sub.f32 %f1297, %f1292, %f1296;
|
|
add.f32 %f1298, %f1295, %f1297;
|
|
mov.f32 %f1299, 0f3F317200;
|
|
mul.rn.f32 %f1300, %f1272, %f1299;
|
|
mov.f32 %f1301, 0f35BFBE8E;
|
|
mul.rn.f32 %f1302, %f1272, %f1301;
|
|
add.f32 %f1303, %f1300, %f1296;
|
|
sub.f32 %f1304, %f1300, %f1303;
|
|
add.f32 %f1305, %f1296, %f1304;
|
|
add.f32 %f1306, %f1298, %f1305;
|
|
add.f32 %f1307, %f1302, %f1306;
|
|
add.f32 %f1308, %f1303, %f1307;
|
|
sub.f32 %f1309, %f1303, %f1308;
|
|
add.f32 %f1310, %f1307, %f1309;
|
|
mul.rn.f32 %f1311, %f1262, %f1308;
|
|
neg.f32 %f1312, %f1311;
|
|
fma.rn.f32 %f1313, %f1262, %f1308, %f1312;
|
|
fma.rn.f32 %f1314, %f1262, %f1310, %f1313;
|
|
fma.rn.f32 %f1315, %f1256, %f1308, %f1314;
|
|
add.rn.f32 %f1316, %f1311, %f1315;
|
|
neg.f32 %f1317, %f1316;
|
|
add.rn.f32 %f1318, %f1311, %f1317;
|
|
add.rn.f32 %f1319, %f1318, %f1315;
|
|
mov.b32 %r372, %f1316;
|
|
setp.eq.s32 %p146, %r372, 1118925336;
|
|
add.s32 %r373, %r372, -1;
|
|
mov.b32 %f1320, %r373;
|
|
add.f32 %f1321, %f1319, 0f37000000;
|
|
selp.f32 %f285, %f1321, %f1319, %p146;
|
|
selp.f32 %f1322, %f1320, %f1316, %p146;
|
|
mov.f32 %f1323, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1324, %f1322, %f1323;
|
|
cvt.rzi.f32.f32 %f1325, %f1324;
|
|
abs.f32 %f1326, %f1325;
|
|
setp.gt.f32 %p147, %f1326, 0f42FC0000;
|
|
mov.b32 %r374, %f1325;
|
|
and.b32 %r375, %r374, -2147483648;
|
|
or.b32 %r376, %r375, 1123811328;
|
|
mov.b32 %f1327, %r376;
|
|
selp.f32 %f1328, %f1327, %f1325, %p147;
|
|
mov.f32 %f1329, 0fBF317218;
|
|
fma.rn.f32 %f1330, %f1328, %f1329, %f1322;
|
|
mov.f32 %f1331, 0f3102E308;
|
|
fma.rn.f32 %f1332, %f1328, %f1331, %f1330;
|
|
mul.f32 %f1333, %f1332, 0f3FB8AA3B;
|
|
add.f32 %f1334, %f1328, 0f4B40007F;
|
|
mov.b32 %r377, %f1334;
|
|
shl.b32 %r378, %r377, 23;
|
|
mov.b32 %f1335, %r378;
|
|
ex2.approx.ftz.f32 %f1336, %f1333;
|
|
mul.f32 %f286, %f1336, %f1335;
|
|
setp.eq.f32 %p148, %f286, 0f7F800000;
|
|
mov.f32 %f1755, 0f7F800000;
|
|
@%p148 bra $L__BB0_112;
|
|
|
|
fma.rn.f32 %f1755, %f286, %f285, %f286;
|
|
|
|
$L__BB0_112:
|
|
setp.lt.f32 %p149, %f280, 0f00000000;
|
|
setp.eq.f32 %p150, %f283, 0f3F800000;
|
|
and.pred %p8, %p149, %p150;
|
|
setp.eq.f32 %p151, %f280, 0f00000000;
|
|
@%p151 bra $L__BB0_116;
|
|
bra.uni $L__BB0_113;
|
|
|
|
$L__BB0_116:
|
|
add.f32 %f1341, %f280, %f280;
|
|
selp.f32 %f1757, %f1341, 0f00000000, %p150;
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_113:
|
|
mov.b32 %r379, %f1755;
|
|
xor.b32 %r380, %r379, -2147483648;
|
|
mov.b32 %f1337, %r380;
|
|
selp.f32 %f1757, %f1337, %f1755, %p8;
|
|
setp.geu.f32 %p152, %f280, 0f00000000;
|
|
@%p152 bra $L__BB0_117;
|
|
|
|
mov.f32 %f1338, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1339, %f1338;
|
|
setp.eq.f32 %p153, %f1339, 0f3ED55555;
|
|
@%p153 bra $L__BB0_117;
|
|
|
|
mov.f32 %f1757, 0f7FFFFFFF;
|
|
|
|
$L__BB0_117:
|
|
add.f32 %f1342, %f284, 0f3ED55555;
|
|
mov.b32 %r381, %f1342;
|
|
setp.lt.s32 %p155, %r381, 2139095040;
|
|
@%p155 bra $L__BB0_122;
|
|
|
|
setp.gtu.f32 %p156, %f284, 0f7F800000;
|
|
@%p156 bra $L__BB0_121;
|
|
bra.uni $L__BB0_119;
|
|
|
|
$L__BB0_121:
|
|
add.f32 %f1757, %f280, 0f3ED55555;
|
|
bra.uni $L__BB0_122;
|
|
|
|
$L__BB0_119:
|
|
setp.neu.f32 %p157, %f284, 0f7F800000;
|
|
@%p157 bra $L__BB0_122;
|
|
|
|
selp.f32 %f1757, 0fFF800000, 0f7F800000, %p8;
|
|
|
|
$L__BB0_122:
|
|
abs.f32 %f295, %f281;
|
|
setp.lt.f32 %p158, %f295, 0f00800000;
|
|
mul.f32 %f1344, %f295, 0f4B800000;
|
|
selp.f32 %f1345, %f1344, %f295, %p158;
|
|
selp.f32 %f1346, 0fC3170000, 0fC2FE0000, %p158;
|
|
mov.b32 %r382, %f1345;
|
|
and.b32 %r383, %r382, 8388607;
|
|
or.b32 %r384, %r383, 1065353216;
|
|
mov.b32 %f1347, %r384;
|
|
shr.u32 %r385, %r382, 23;
|
|
cvt.rn.f32.u32 %f1348, %r385;
|
|
add.f32 %f1349, %f1346, %f1348;
|
|
setp.gt.f32 %p159, %f1347, 0f3FB504F3;
|
|
mul.f32 %f1350, %f1347, 0f3F000000;
|
|
add.f32 %f1351, %f1349, 0f3F800000;
|
|
selp.f32 %f1352, %f1351, %f1349, %p159;
|
|
selp.f32 %f1353, %f1350, %f1347, %p159;
|
|
add.f32 %f1354, %f1353, 0fBF800000;
|
|
add.f32 %f1355, %f1353, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1356, %f1355;
|
|
add.f32 %f1357, %f1354, %f1354;
|
|
mul.f32 %f1358, %f1357, %f1356;
|
|
mul.f32 %f1359, %f1358, %f1358;
|
|
mov.f32 %f1360, 0f3C4CAF63;
|
|
mov.f32 %f1361, 0f3B18F0FE;
|
|
fma.rn.f32 %f1362, %f1361, %f1359, %f1360;
|
|
mov.f32 %f1363, 0f3DAAAABD;
|
|
fma.rn.f32 %f1364, %f1362, %f1359, %f1363;
|
|
mul.rn.f32 %f1365, %f1364, %f1359;
|
|
mul.rn.f32 %f1366, %f1365, %f1358;
|
|
sub.f32 %f1367, %f1354, %f1358;
|
|
add.f32 %f1368, %f1367, %f1367;
|
|
neg.f32 %f1369, %f1358;
|
|
fma.rn.f32 %f1370, %f1369, %f1354, %f1368;
|
|
mul.rn.f32 %f1371, %f1356, %f1370;
|
|
add.f32 %f1372, %f1366, %f1358;
|
|
sub.f32 %f1373, %f1358, %f1372;
|
|
add.f32 %f1374, %f1366, %f1373;
|
|
add.f32 %f1375, %f1371, %f1374;
|
|
add.f32 %f1376, %f1372, %f1375;
|
|
sub.f32 %f1377, %f1372, %f1376;
|
|
add.f32 %f1378, %f1375, %f1377;
|
|
mov.f32 %f1379, 0f3F317200;
|
|
mul.rn.f32 %f1380, %f1352, %f1379;
|
|
mov.f32 %f1381, 0f35BFBE8E;
|
|
mul.rn.f32 %f1382, %f1352, %f1381;
|
|
add.f32 %f1383, %f1380, %f1376;
|
|
sub.f32 %f1384, %f1380, %f1383;
|
|
add.f32 %f1385, %f1376, %f1384;
|
|
add.f32 %f1386, %f1378, %f1385;
|
|
add.f32 %f1387, %f1382, %f1386;
|
|
add.f32 %f1388, %f1383, %f1387;
|
|
sub.f32 %f1389, %f1383, %f1388;
|
|
add.f32 %f1390, %f1387, %f1389;
|
|
mov.f32 %f1391, 0f3ED55555;
|
|
mul.rn.f32 %f1392, %f1391, %f1388;
|
|
neg.f32 %f1393, %f1392;
|
|
fma.rn.f32 %f1394, %f1391, %f1388, %f1393;
|
|
fma.rn.f32 %f1395, %f1391, %f1390, %f1394;
|
|
mov.f32 %f1396, 0f00000000;
|
|
fma.rn.f32 %f1397, %f1396, %f1388, %f1395;
|
|
add.rn.f32 %f1398, %f1392, %f1397;
|
|
neg.f32 %f1399, %f1398;
|
|
add.rn.f32 %f1400, %f1392, %f1399;
|
|
add.rn.f32 %f1401, %f1400, %f1397;
|
|
mov.b32 %r386, %f1398;
|
|
setp.eq.s32 %p160, %r386, 1118925336;
|
|
add.s32 %r387, %r386, -1;
|
|
mov.b32 %f1402, %r387;
|
|
add.f32 %f1403, %f1401, 0f37000000;
|
|
selp.f32 %f296, %f1403, %f1401, %p160;
|
|
selp.f32 %f1404, %f1402, %f1398, %p160;
|
|
mov.f32 %f1405, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1406, %f1404, %f1405;
|
|
cvt.rzi.f32.f32 %f1407, %f1406;
|
|
abs.f32 %f1408, %f1407;
|
|
setp.gt.f32 %p161, %f1408, 0f42FC0000;
|
|
mov.b32 %r388, %f1407;
|
|
and.b32 %r389, %r388, -2147483648;
|
|
or.b32 %r390, %r389, 1123811328;
|
|
mov.b32 %f1409, %r390;
|
|
selp.f32 %f1410, %f1409, %f1407, %p161;
|
|
mov.f32 %f1411, 0fBF317218;
|
|
fma.rn.f32 %f1412, %f1410, %f1411, %f1404;
|
|
mov.f32 %f1413, 0f3102E308;
|
|
fma.rn.f32 %f1414, %f1410, %f1413, %f1412;
|
|
mul.f32 %f1415, %f1414, 0f3FB8AA3B;
|
|
add.f32 %f1416, %f1410, 0f4B40007F;
|
|
mov.b32 %r391, %f1416;
|
|
shl.b32 %r392, %r391, 23;
|
|
mov.b32 %f1417, %r392;
|
|
ex2.approx.ftz.f32 %f1418, %f1415;
|
|
mul.f32 %f297, %f1418, %f1417;
|
|
setp.eq.f32 %p162, %f297, 0f7F800000;
|
|
mov.f32 %f1758, 0f7F800000;
|
|
@%p162 bra $L__BB0_124;
|
|
|
|
fma.rn.f32 %f1758, %f297, %f296, %f297;
|
|
|
|
$L__BB0_124:
|
|
setp.lt.f32 %p163, %f281, 0f00000000;
|
|
and.pred %p9, %p163, %p150;
|
|
setp.eq.f32 %p165, %f281, 0f00000000;
|
|
@%p165 bra $L__BB0_128;
|
|
bra.uni $L__BB0_125;
|
|
|
|
$L__BB0_128:
|
|
add.f32 %f1423, %f281, %f281;
|
|
selp.f32 %f1760, %f1423, 0f00000000, %p150;
|
|
bra.uni $L__BB0_129;
|
|
|
|
$L__BB0_125:
|
|
mov.b32 %r393, %f1758;
|
|
xor.b32 %r394, %r393, -2147483648;
|
|
mov.b32 %f1419, %r394;
|
|
selp.f32 %f1760, %f1419, %f1758, %p9;
|
|
setp.geu.f32 %p166, %f281, 0f00000000;
|
|
@%p166 bra $L__BB0_129;
|
|
|
|
mov.f32 %f1420, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1421, %f1420;
|
|
setp.eq.f32 %p167, %f1421, 0f3ED55555;
|
|
@%p167 bra $L__BB0_129;
|
|
|
|
mov.f32 %f1760, 0f7FFFFFFF;
|
|
|
|
$L__BB0_129:
|
|
add.f32 %f1424, %f295, 0f3ED55555;
|
|
mov.b32 %r395, %f1424;
|
|
setp.lt.s32 %p169, %r395, 2139095040;
|
|
@%p169 bra $L__BB0_134;
|
|
|
|
setp.gtu.f32 %p170, %f295, 0f7F800000;
|
|
@%p170 bra $L__BB0_133;
|
|
bra.uni $L__BB0_131;
|
|
|
|
$L__BB0_133:
|
|
add.f32 %f1760, %f281, 0f3ED55555;
|
|
bra.uni $L__BB0_134;
|
|
|
|
$L__BB0_131:
|
|
setp.neu.f32 %p171, %f295, 0f7F800000;
|
|
@%p171 bra $L__BB0_134;
|
|
|
|
selp.f32 %f1760, 0fFF800000, 0f7F800000, %p9;
|
|
|
|
$L__BB0_134:
|
|
abs.f32 %f306, %f282;
|
|
setp.lt.f32 %p172, %f306, 0f00800000;
|
|
mul.f32 %f1426, %f306, 0f4B800000;
|
|
selp.f32 %f1427, %f1426, %f306, %p172;
|
|
selp.f32 %f1428, 0fC3170000, 0fC2FE0000, %p172;
|
|
mov.b32 %r396, %f1427;
|
|
and.b32 %r397, %r396, 8388607;
|
|
or.b32 %r398, %r397, 1065353216;
|
|
mov.b32 %f1429, %r398;
|
|
shr.u32 %r399, %r396, 23;
|
|
cvt.rn.f32.u32 %f1430, %r399;
|
|
add.f32 %f1431, %f1428, %f1430;
|
|
setp.gt.f32 %p173, %f1429, 0f3FB504F3;
|
|
mul.f32 %f1432, %f1429, 0f3F000000;
|
|
add.f32 %f1433, %f1431, 0f3F800000;
|
|
selp.f32 %f1434, %f1433, %f1431, %p173;
|
|
selp.f32 %f1435, %f1432, %f1429, %p173;
|
|
add.f32 %f1436, %f1435, 0fBF800000;
|
|
add.f32 %f1437, %f1435, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1438, %f1437;
|
|
add.f32 %f1439, %f1436, %f1436;
|
|
mul.f32 %f1440, %f1439, %f1438;
|
|
mul.f32 %f1441, %f1440, %f1440;
|
|
mov.f32 %f1442, 0f3C4CAF63;
|
|
mov.f32 %f1443, 0f3B18F0FE;
|
|
fma.rn.f32 %f1444, %f1443, %f1441, %f1442;
|
|
mov.f32 %f1445, 0f3DAAAABD;
|
|
fma.rn.f32 %f1446, %f1444, %f1441, %f1445;
|
|
mul.rn.f32 %f1447, %f1446, %f1441;
|
|
mul.rn.f32 %f1448, %f1447, %f1440;
|
|
sub.f32 %f1449, %f1436, %f1440;
|
|
add.f32 %f1450, %f1449, %f1449;
|
|
neg.f32 %f1451, %f1440;
|
|
fma.rn.f32 %f1452, %f1451, %f1436, %f1450;
|
|
mul.rn.f32 %f1453, %f1438, %f1452;
|
|
add.f32 %f1454, %f1448, %f1440;
|
|
sub.f32 %f1455, %f1440, %f1454;
|
|
add.f32 %f1456, %f1448, %f1455;
|
|
add.f32 %f1457, %f1453, %f1456;
|
|
add.f32 %f1458, %f1454, %f1457;
|
|
sub.f32 %f1459, %f1454, %f1458;
|
|
add.f32 %f1460, %f1457, %f1459;
|
|
mov.f32 %f1461, 0f3F317200;
|
|
mul.rn.f32 %f1462, %f1434, %f1461;
|
|
mov.f32 %f1463, 0f35BFBE8E;
|
|
mul.rn.f32 %f1464, %f1434, %f1463;
|
|
add.f32 %f1465, %f1462, %f1458;
|
|
sub.f32 %f1466, %f1462, %f1465;
|
|
add.f32 %f1467, %f1458, %f1466;
|
|
add.f32 %f1468, %f1460, %f1467;
|
|
add.f32 %f1469, %f1464, %f1468;
|
|
add.f32 %f1470, %f1465, %f1469;
|
|
sub.f32 %f1471, %f1465, %f1470;
|
|
add.f32 %f1472, %f1469, %f1471;
|
|
mov.f32 %f1473, 0f3ED55555;
|
|
mul.rn.f32 %f1474, %f1473, %f1470;
|
|
neg.f32 %f1475, %f1474;
|
|
fma.rn.f32 %f1476, %f1473, %f1470, %f1475;
|
|
fma.rn.f32 %f1477, %f1473, %f1472, %f1476;
|
|
mov.f32 %f1478, 0f00000000;
|
|
fma.rn.f32 %f1479, %f1478, %f1470, %f1477;
|
|
add.rn.f32 %f1480, %f1474, %f1479;
|
|
neg.f32 %f1481, %f1480;
|
|
add.rn.f32 %f1482, %f1474, %f1481;
|
|
add.rn.f32 %f1483, %f1482, %f1479;
|
|
mov.b32 %r400, %f1480;
|
|
setp.eq.s32 %p174, %r400, 1118925336;
|
|
add.s32 %r401, %r400, -1;
|
|
mov.b32 %f1484, %r401;
|
|
add.f32 %f1485, %f1483, 0f37000000;
|
|
selp.f32 %f307, %f1485, %f1483, %p174;
|
|
selp.f32 %f1486, %f1484, %f1480, %p174;
|
|
mov.f32 %f1487, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1488, %f1486, %f1487;
|
|
cvt.rzi.f32.f32 %f1489, %f1488;
|
|
abs.f32 %f1490, %f1489;
|
|
setp.gt.f32 %p175, %f1490, 0f42FC0000;
|
|
mov.b32 %r402, %f1489;
|
|
and.b32 %r403, %r402, -2147483648;
|
|
or.b32 %r404, %r403, 1123811328;
|
|
mov.b32 %f1491, %r404;
|
|
selp.f32 %f1492, %f1491, %f1489, %p175;
|
|
mov.f32 %f1493, 0fBF317218;
|
|
fma.rn.f32 %f1494, %f1492, %f1493, %f1486;
|
|
mov.f32 %f1495, 0f3102E308;
|
|
fma.rn.f32 %f1496, %f1492, %f1495, %f1494;
|
|
mul.f32 %f1497, %f1496, 0f3FB8AA3B;
|
|
add.f32 %f1498, %f1492, 0f4B40007F;
|
|
mov.b32 %r405, %f1498;
|
|
shl.b32 %r406, %r405, 23;
|
|
mov.b32 %f1499, %r406;
|
|
ex2.approx.ftz.f32 %f1500, %f1497;
|
|
mul.f32 %f308, %f1500, %f1499;
|
|
setp.eq.f32 %p176, %f308, 0f7F800000;
|
|
mov.f32 %f1761, 0f7F800000;
|
|
@%p176 bra $L__BB0_136;
|
|
|
|
fma.rn.f32 %f1761, %f308, %f307, %f308;
|
|
|
|
$L__BB0_136:
|
|
setp.lt.f32 %p177, %f282, 0f00000000;
|
|
and.pred %p10, %p177, %p150;
|
|
setp.eq.f32 %p179, %f282, 0f00000000;
|
|
@%p179 bra $L__BB0_140;
|
|
bra.uni $L__BB0_137;
|
|
|
|
$L__BB0_140:
|
|
add.f32 %f1505, %f282, %f282;
|
|
selp.f32 %f1763, %f1505, 0f00000000, %p150;
|
|
bra.uni $L__BB0_141;
|
|
|
|
$L__BB0_137:
|
|
mov.b32 %r407, %f1761;
|
|
xor.b32 %r408, %r407, -2147483648;
|
|
mov.b32 %f1501, %r408;
|
|
selp.f32 %f1763, %f1501, %f1761, %p10;
|
|
setp.geu.f32 %p180, %f282, 0f00000000;
|
|
@%p180 bra $L__BB0_141;
|
|
|
|
mov.f32 %f1502, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1503, %f1502;
|
|
setp.eq.f32 %p181, %f1503, 0f3ED55555;
|
|
@%p181 bra $L__BB0_141;
|
|
|
|
mov.f32 %f1763, 0f7FFFFFFF;
|
|
|
|
$L__BB0_141:
|
|
add.f32 %f1506, %f306, 0f3ED55555;
|
|
mov.b32 %r409, %f1506;
|
|
setp.lt.s32 %p183, %r409, 2139095040;
|
|
@%p183 bra $L__BB0_146;
|
|
|
|
setp.gtu.f32 %p184, %f306, 0f7F800000;
|
|
@%p184 bra $L__BB0_145;
|
|
bra.uni $L__BB0_143;
|
|
|
|
$L__BB0_145:
|
|
add.f32 %f1763, %f282, 0f3ED55555;
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_143:
|
|
setp.neu.f32 %p185, %f306, 0f7F800000;
|
|
@%p185 bra $L__BB0_146;
|
|
|
|
selp.f32 %f1763, 0fFF800000, 0f7F800000, %p10;
|
|
|
|
$L__BB0_146:
|
|
fma.rn.f32 %f1507, %f1757, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p186, %f280, 0f3F800000;
|
|
mov.f32 %f1508, 0f3F800000;
|
|
selp.f32 %f1509, 0f3F7FFFFF, %f1507, %p186;
|
|
mul.f32 %f1510, %f280, 0f414EB852;
|
|
setp.lt.f32 %p187, %f280, 0f3B4D2E1C;
|
|
selp.f32 %f1511, %f1510, %f1509, %p187;
|
|
fma.rn.f32 %f1512, %f1760, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p188, %f281, 0f3F800000;
|
|
selp.f32 %f1513, 0f3F7FFFFF, %f1512, %p188;
|
|
mul.f32 %f1514, %f281, 0f414EB852;
|
|
setp.lt.f32 %p189, %f281, 0f3B4D2E1C;
|
|
selp.f32 %f1515, %f1514, %f1513, %p189;
|
|
fma.rn.f32 %f1516, %f1763, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p190, %f282, 0f3F800000;
|
|
selp.f32 %f1517, 0f3F7FFFFF, %f1516, %p190;
|
|
mul.f32 %f1518, %f282, 0f414EB852;
|
|
setp.lt.f32 %p191, %f282, 0f3B4D2E1C;
|
|
selp.f32 %f1519, %f1518, %f1517, %p191;
|
|
min.f32 %f1520, %f1511, %f1508;
|
|
mov.f32 %f1521, 0f00000000;
|
|
max.f32 %f1522, %f1521, %f1520;
|
|
mul.f32 %f1523, %f1522, 0f43800000;
|
|
cvt.rzi.u32.f32 %r410, %f1523;
|
|
min.u32 %r411, %r410, 255;
|
|
min.f32 %f1524, %f1515, %f1508;
|
|
max.f32 %f1525, %f1521, %f1524;
|
|
mul.f32 %f1526, %f1525, 0f43800000;
|
|
cvt.rzi.u32.f32 %r412, %f1526;
|
|
min.u32 %r413, %r412, 255;
|
|
min.f32 %f1527, %f1519, %f1508;
|
|
max.f32 %f1528, %f1521, %f1527;
|
|
mul.f32 %f1529, %f1528, 0f43800000;
|
|
cvt.rzi.u32.f32 %r414, %f1529;
|
|
min.u32 %r415, %r414, 255;
|
|
shl.b64 %rd37, %rd10, 2;
|
|
add.s64 %rd38, %rd9, %rd37;
|
|
cvt.u16.u32 %rs20, %r415;
|
|
cvt.u16.u32 %rs21, %r413;
|
|
cvt.u16.u32 %rs22, %r411;
|
|
mov.u16 %rs23, 255;
|
|
st.global.v4.u8 [%rd38], {%rs22, %rs21, %rs20, %rs23};
|
|
|
|
$L__BB0_147:
|
|
and.b32 %r416, %r451, 4;
|
|
setp.eq.s32 %p192, %r416, 0;
|
|
ld.const.u32 %r452, [params+108];
|
|
@%p192 bra $L__BB0_151;
|
|
|
|
setp.eq.s32 %p193, %r452, 0;
|
|
ld.const.u64 %rd39, [params+224];
|
|
cvta.to.global.u64 %rd40, %rd39;
|
|
ld.const.u32 %r417, [params+216];
|
|
mad.lo.s32 %r418, %r417, %r4, %r3;
|
|
mul.wide.u32 %rd41, %r418, 8;
|
|
add.s64 %rd11, %rd40, %rd41;
|
|
@%p193 bra $L__BB0_150;
|
|
|
|
ld.global.v4.u16 {%rs31, %rs32, %rs33, %rs34}, [%rd11];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1530, %rs31;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1531, %rs32;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1532, %rs33;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1533, %f1711, %f1530;
|
|
add.f32 %f1534, %f1712, %f1531;
|
|
add.f32 %f1535, %f1713, %f1532;
|
|
mov.f32 %f1536, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f1535;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f1534;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f1533;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f1536;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd11], {%rs27, %rs28, %rs29, %rs30};
|
|
bra.uni $L__BB0_151;
|
|
|
|
$L__BB0_150:
|
|
mov.f32 %f1540, 0f3F800000;
|
|
mov.u32 %r452, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f1540;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f1713;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f1712;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f1711;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd11], {%rs35, %rs36, %rs37, %rs38};
|
|
|
|
$L__BB0_151:
|
|
mov.f32 %f1541, 0f34000000;
|
|
max.f32 %f1542, %f1714, %f1541;
|
|
div.rn.f32 %f1543, %f1717, %f1542;
|
|
max.f32 %f1544, %f1715, %f1541;
|
|
div.rn.f32 %f1545, %f1718, %f1544;
|
|
max.f32 %f1546, %f1716, %f1541;
|
|
div.rn.f32 %f1547, %f1719, %f1546;
|
|
fma.rn.f32 %f317, %f1543, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f318, %f1545, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f319, %f1547, 0f3F000000, 0f3F000000;
|
|
div.rn.f32 %f1548, %f1720, %f1542;
|
|
div.rn.f32 %f1549, %f1721, %f1544;
|
|
div.rn.f32 %f1550, %f1722, %f1546;
|
|
fma.rn.f32 %f320, %f1548, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f321, %f1549, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f322, %f1550, 0f3F000000, 0f3F000000;
|
|
div.rn.f32 %f1551, %f1723, %f1542;
|
|
div.rn.f32 %f1552, %f1724, %f1544;
|
|
div.rn.f32 %f1553, %f1725, %f1546;
|
|
fma.rn.f32 %f323, %f1551, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f324, %f1552, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f325, %f1553, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd42, [params+256];
|
|
cvta.to.global.u64 %rd43, %rd42;
|
|
ld.const.u32 %r420, [params+248];
|
|
mad.lo.s32 %r421, %r420, %r4, %r3;
|
|
mul.wide.u32 %rd44, %r421, 8;
|
|
add.s64 %rd12, %rd43, %rd44;
|
|
setp.eq.s32 %p194, %r452, 0;
|
|
@%p194 bra $L__BB0_153;
|
|
|
|
ld.global.v4.u16 {%rs46, %rs47, %rs48, %rs49}, [%rd12];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1554, %rs46;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1555, %rs47;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1556, %rs48;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1557, %f1714, %f1554;
|
|
add.f32 %f1558, %f1715, %f1555;
|
|
add.f32 %f1559, %f1716, %f1556;
|
|
mov.f32 %f1560, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs44, %f1559;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f1558;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f1557;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs45, %f1560;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd12], {%rs42, %rs43, %rs44, %rs45};
|
|
bra.uni $L__BB0_154;
|
|
|
|
$L__BB0_153:
|
|
mov.f32 %f1564, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f1564;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f1716;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f1715;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f1714;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd12], {%rs50, %rs51, %rs52, %rs53};
|
|
|
|
$L__BB0_154:
|
|
ld.const.u64 %rd45, [params+272];
|
|
cvta.to.global.u64 %rd46, %rd45;
|
|
ld.const.u32 %r422, [params+264];
|
|
mad.lo.s32 %r423, %r422, %r4, %r3;
|
|
mul.wide.u32 %rd47, %r423, 8;
|
|
add.s64 %rd13, %rd46, %rd47;
|
|
@%p194 bra $L__BB0_156;
|
|
|
|
ld.global.v4.u16 {%rs61, %rs62, %rs63, %rs64}, [%rd13];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1565, %rs61;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1566, %rs62;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1567, %rs63;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1568, %f317, %f1565;
|
|
add.f32 %f1569, %f318, %f1566;
|
|
add.f32 %f1570, %f319, %f1567;
|
|
mov.f32 %f1571, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f1570;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f1569;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1568;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f1571;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd13], {%rs57, %rs58, %rs59, %rs60};
|
|
bra.uni $L__BB0_157;
|
|
|
|
$L__BB0_156:
|
|
mov.f32 %f1575, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1575;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f319;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f318;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f317;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd13], {%rs65, %rs66, %rs67, %rs68};
|
|
|
|
$L__BB0_157:
|
|
ld.const.u64 %rd48, [params+288];
|
|
cvta.to.global.u64 %rd49, %rd48;
|
|
ld.const.u32 %r424, [params+280];
|
|
mad.lo.s32 %r425, %r424, %r4, %r3;
|
|
mul.wide.u32 %rd50, %r425, 8;
|
|
add.s64 %rd14, %rd49, %rd50;
|
|
@%p194 bra $L__BB0_159;
|
|
|
|
ld.global.v4.u16 {%rs76, %rs77, %rs78, %rs79}, [%rd14];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1576, %rs76;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1577, %rs77;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1578, %rs78;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1579, %f320, %f1576;
|
|
add.f32 %f1580, %f321, %f1577;
|
|
add.f32 %f1581, %f322, %f1578;
|
|
mov.f32 %f1582, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs74, %f1581;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1580;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1579;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f1582;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd14], {%rs72, %rs73, %rs74, %rs75};
|
|
bra.uni $L__BB0_160;
|
|
|
|
$L__BB0_159:
|
|
mov.f32 %f1586, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1586;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f322;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f321;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f320;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd14], {%rs80, %rs81, %rs82, %rs83};
|
|
|
|
$L__BB0_160:
|
|
ld.const.u64 %rd51, [params+304];
|
|
cvta.to.global.u64 %rd52, %rd51;
|
|
ld.const.u32 %r426, [params+296];
|
|
mad.lo.s32 %r427, %r426, %r4, %r3;
|
|
mul.wide.u32 %rd53, %r427, 8;
|
|
add.s64 %rd15, %rd52, %rd53;
|
|
@%p194 bra $L__BB0_162;
|
|
|
|
ld.global.v4.u16 {%rs91, %rs92, %rs93, %rs94}, [%rd15];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1587, %rs91;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1588, %rs92;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1589, %rs93;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1590, %f323, %f1587;
|
|
add.f32 %f1591, %f324, %f1588;
|
|
add.f32 %f1592, %f325, %f1589;
|
|
mov.f32 %f1593, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs89, %f1592;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1591;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1590;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f1593;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd15], {%rs87, %rs88, %rs89, %rs90};
|
|
bra.uni $L__BB0_183;
|
|
|
|
$L__BB0_162:
|
|
mov.f32 %f1597, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs98, %f1597;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f325;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f324;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f323;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd15], {%rs95, %rs96, %rs97, %rs98};
|
|
|
|
$L__BB0_183:
|
|
ret;
|
|
|
|
}
|
|
|