2311 lines
63 KiB
Plaintext
2311 lines
63 KiB
Plaintext
//
|
|
// Generated by NVIDIA NVVM Compiler
|
|
//
|
|
// Compiler Build ID: CL-31968024
|
|
// Cuda compilation tools, release 12.0, V12.0.76
|
|
// Based on NVVM 7.0.1
|
|
//
|
|
|
|
.version 8.0
|
|
.target sm_52
|
|
.address_size 64
|
|
|
|
// .globl __raygen__oxMain
|
|
.const .align 16 .b8 params[1184];
|
|
.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
|
|
|
|
.visible .entry __raygen__oxMain()
|
|
{
|
|
.local .align 4 .b8 __local_depot0[28];
|
|
.reg .b64 %SP;
|
|
.reg .b64 %SPL;
|
|
.reg .pred %p<161>;
|
|
.reg .b16 %rs<175>;
|
|
.reg .f32 %f<1290>;
|
|
.reg .b32 %r<359>;
|
|
.reg .f64 %fd<5>;
|
|
.reg .b64 %rd<105>;
|
|
|
|
|
|
mov.u64 %SPL, __local_depot0;
|
|
add.u64 %rd1, %SPL, 0;
|
|
// begin inline asm
|
|
call (%r55), _optix_get_launch_index_x, ();
|
|
// end inline asm
|
|
// begin inline asm
|
|
call (%r56), _optix_get_launch_index_y, ();
|
|
// end inline asm
|
|
ld.const.u32 %r3, [params+540];
|
|
ld.const.u64 %rd27, [params+400];
|
|
cvta.to.global.u64 %rd28, %rd27;
|
|
ld.const.u32 %r61, [params+392];
|
|
mad.lo.s32 %r62, %r61, %r56, %r55;
|
|
mul.wide.u32 %rd29, %r62, 4;
|
|
add.s64 %rd2, %rd28, %rd29;
|
|
ld.global.v2.u8 {%rs16, %rs170}, [%rd2];
|
|
or.b16 %rs18, %rs16, %rs170;
|
|
and.b16 %rs19, %rs18, 255;
|
|
setp.eq.s16 %p7, %rs19, 0;
|
|
@%p7 bra $L__BB0_2;
|
|
|
|
ld.global.u8 %rs169, [%rd2+2];
|
|
bra.uni $L__BB0_3;
|
|
|
|
$L__BB0_2:
|
|
ld.global.u8 %rs169, [%rd2+2];
|
|
setp.eq.s16 %p8, %rs169, 0;
|
|
mov.f32 %f1206, 0f00000000;
|
|
mov.u16 %rs170, 0;
|
|
mov.f32 %f1207, %f1206;
|
|
mov.f32 %f1208, %f1206;
|
|
@%p8 bra $L__BB0_4;
|
|
|
|
$L__BB0_3:
|
|
cvt.rn.f32.u16 %f247, %rs16;
|
|
div.rn.f32 %f248, %f247, 0f437F0000;
|
|
fma.rn.f32 %f249, %f248, 0f40000000, 0fBF800000;
|
|
and.b16 %rs22, %rs170, 255;
|
|
cvt.rn.f32.u16 %f250, %rs22;
|
|
div.rn.f32 %f251, %f250, 0f437F0000;
|
|
fma.rn.f32 %f252, %f251, 0f40000000, 0fBF800000;
|
|
cvt.rn.f32.u16 %f253, %rs169;
|
|
div.rn.f32 %f254, %f253, 0f437F0000;
|
|
fma.rn.f32 %f255, %f254, 0f40000000, 0fBF800000;
|
|
mul.f32 %f256, %f252, %f252;
|
|
fma.rn.f32 %f257, %f249, %f249, %f256;
|
|
fma.rn.f32 %f258, %f255, %f255, %f257;
|
|
sqrt.rn.f32 %f259, %f258;
|
|
rcp.rn.f32 %f260, %f259;
|
|
mul.f32 %f1208, %f260, %f255;
|
|
mul.f32 %f1207, %f260, %f252;
|
|
mul.f32 %f1206, %f249, %f260;
|
|
|
|
$L__BB0_4:
|
|
ld.const.v2.u32 {%r63, %r64}, [params];
|
|
add.s32 %r4, %r63, %r55;
|
|
add.s32 %r5, %r64, %r56;
|
|
setp.eq.f32 %p9, %f1206, 0f00000000;
|
|
setp.eq.f32 %p10, %f1207, 0f00000000;
|
|
and.pred %p11, %p9, %p10;
|
|
setp.eq.f32 %p12, %f1208, 0f00000000;
|
|
and.pred %p13, %p12, %p11;
|
|
@%p13 bra $L__BB0_131;
|
|
bra.uni $L__BB0_5;
|
|
|
|
$L__BB0_131:
|
|
ld.const.u32 %r52, [params+104];
|
|
and.b32 %r314, %r52, 1;
|
|
setp.eq.b32 %p151, %r314, 1;
|
|
mov.pred %p152, 0;
|
|
xor.pred %p153, %p151, %p152;
|
|
not.pred %p154, %p153;
|
|
@%p154 bra $L__BB0_133;
|
|
|
|
ld.const.u64 %rd81, [params+144];
|
|
cvta.to.global.u64 %rd82, %rd81;
|
|
ld.const.u32 %r315, [params+136];
|
|
mad.lo.s32 %r316, %r315, %r5, %r4;
|
|
mul.wide.u32 %rd83, %r316, 4;
|
|
add.s64 %rd84, %rd82, %rd83;
|
|
mov.u16 %rs108, 0;
|
|
st.global.v4.u8 [%rd84], {%rs108, %rs108, %rs108, %rs108};
|
|
|
|
$L__BB0_133:
|
|
and.b32 %r317, %r52, 4;
|
|
setp.eq.s32 %p155, %r317, 0;
|
|
ld.const.u32 %r358, [params+108];
|
|
@%p155 bra $L__BB0_137;
|
|
|
|
setp.eq.s32 %p156, %r358, 0;
|
|
ld.const.u64 %rd85, [params+224];
|
|
cvta.to.global.u64 %rd86, %rd85;
|
|
ld.const.u32 %r318, [params+216];
|
|
mad.lo.s32 %r319, %r318, %r5, %r4;
|
|
mul.wide.u32 %rd87, %r319, 8;
|
|
add.s64 %rd22, %rd86, %rd87;
|
|
@%p156 bra $L__BB0_136;
|
|
|
|
ld.global.v4.u16 {%rs115, %rs116, %rs117, %rs118}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1124, %rs115;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1125, %rs116;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1126, %rs117;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1127, %f1124, 0f00000000;
|
|
add.f32 %f1128, %f1125, 0f00000000;
|
|
add.f32 %f1129, %f1126, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f1129;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1128;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs112, %f1127;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs119, 0;
|
|
st.global.v4.u16 [%rd22], {%rs112, %rs113, %rs114, %rs119};
|
|
bra.uni $L__BB0_137;
|
|
|
|
$L__BB0_5:
|
|
ld.const.u64 %rd30, [params+432];
|
|
cvta.to.global.u64 %rd31, %rd30;
|
|
ld.const.u32 %r67, [params+424];
|
|
mad.lo.s32 %r68, %r67, %r56, %r55;
|
|
mul.wide.u32 %rd32, %r68, 12;
|
|
add.s64 %rd33, %rd31, %rd32;
|
|
ld.global.f32 %f261, [%rd33];
|
|
mul.f32 %f262, %f261, 0f3456BF95;
|
|
ld.global.f32 %f263, [%rd33+4];
|
|
mul.f32 %f264, %f263, 0f3456BF95;
|
|
ld.global.f32 %f265, [%rd33+8];
|
|
mul.f32 %f266, %f265, 0f3456BF95;
|
|
abs.f32 %f267, %f1206;
|
|
div.rn.f32 %f268, %f262, %f267;
|
|
abs.f32 %f269, %f1207;
|
|
div.rn.f32 %f270, %f264, %f269;
|
|
abs.f32 %f271, %f1208;
|
|
div.rn.f32 %f272, %f266, %f271;
|
|
abs.f32 %f273, %f268;
|
|
abs.f32 %f274, %f270;
|
|
abs.f32 %f275, %f272;
|
|
mov.f32 %f276, 0f38D1B717;
|
|
max.f32 %f277, %f273, %f276;
|
|
max.f32 %f278, %f274, %f276;
|
|
max.f32 %f279, %f275, %f276;
|
|
fma.rn.f32 %f10, %f1206, %f277, %f261;
|
|
fma.rn.f32 %f11, %f1207, %f278, %f263;
|
|
fma.rn.f32 %f12, %f1208, %f279, %f265;
|
|
ld.const.u32 %r6, [params+588];
|
|
setp.gt.f32 %p14, %f267, %f271;
|
|
neg.f32 %f280, %f1207;
|
|
selp.f32 %f281, %f280, 0f00000000, %p14;
|
|
neg.f32 %f282, %f1208;
|
|
selp.f32 %f283, %f1206, %f282, %p14;
|
|
selp.f32 %f284, 0f00000000, %f1207, %p14;
|
|
mul.f32 %f285, %f283, %f283;
|
|
fma.rn.f32 %f286, %f281, %f281, %f285;
|
|
fma.rn.f32 %f287, %f284, %f284, %f286;
|
|
sqrt.rn.f32 %f288, %f287;
|
|
rcp.rn.f32 %f289, %f288;
|
|
mul.f32 %f13, %f281, %f289;
|
|
mul.f32 %f14, %f283, %f289;
|
|
mul.f32 %f15, %f284, %f289;
|
|
ld.const.u64 %rd34, [params+128];
|
|
cvta.to.global.u64 %rd35, %rd34;
|
|
ld.const.u32 %r69, [params+120];
|
|
mad.lo.s32 %r70, %r69, %r56, %r55;
|
|
mul.wide.u32 %rd36, %r70, 4;
|
|
add.s64 %rd37, %rd35, %rd36;
|
|
ld.global.u32 %r349, [%rd37];
|
|
ld.const.u64 %rd38, [params+464];
|
|
cvta.to.global.u64 %rd39, %rd38;
|
|
ld.const.u32 %r71, [params+456];
|
|
mad.lo.s32 %r72, %r71, %r56, %r55;
|
|
mul.wide.u32 %rd40, %r72, 4;
|
|
add.s64 %rd3, %rd39, %rd40;
|
|
ld.global.v2.u8 {%rs24, %rs173}, [%rd3];
|
|
or.b16 %rs26, %rs24, %rs173;
|
|
and.b16 %rs27, %rs26, 255;
|
|
setp.eq.s16 %p15, %rs27, 0;
|
|
@%p15 bra $L__BB0_7;
|
|
|
|
ld.global.u8 %rs171, [%rd3+2];
|
|
bra.uni $L__BB0_8;
|
|
|
|
$L__BB0_7:
|
|
ld.global.u8 %rs171, [%rd3+2];
|
|
setp.eq.s16 %p16, %rs171, 0;
|
|
mov.f32 %f1209, 0f00000000;
|
|
mov.u16 %rs173, 0;
|
|
mov.u16 %rs174, %rs173;
|
|
mov.f32 %f1210, %f1209;
|
|
mov.f32 %f1211, %f1209;
|
|
@%p16 bra $L__BB0_9;
|
|
|
|
$L__BB0_8:
|
|
mov.u16 %rs174, %rs173;
|
|
cvt.rn.f32.u16 %f293, %rs24;
|
|
div.rn.f32 %f294, %f293, 0f437F0000;
|
|
fma.rn.f32 %f295, %f294, 0f40000000, 0fBF800000;
|
|
and.b16 %rs32, %rs174, 255;
|
|
cvt.rn.f32.u16 %f296, %rs32;
|
|
div.rn.f32 %f297, %f296, 0f437F0000;
|
|
fma.rn.f32 %f298, %f297, 0f40000000, 0fBF800000;
|
|
cvt.rn.f32.u16 %f299, %rs171;
|
|
div.rn.f32 %f300, %f299, 0f437F0000;
|
|
fma.rn.f32 %f301, %f300, 0f40000000, 0fBF800000;
|
|
mul.f32 %f302, %f298, %f298;
|
|
fma.rn.f32 %f303, %f295, %f295, %f302;
|
|
fma.rn.f32 %f304, %f301, %f301, %f303;
|
|
sqrt.rn.f32 %f305, %f304;
|
|
rcp.rn.f32 %f306, %f305;
|
|
mul.f32 %f1211, %f306, %f301;
|
|
mul.f32 %f1210, %f306, %f298;
|
|
mul.f32 %f1209, %f295, %f306;
|
|
mov.u16 %rs173, %rs171;
|
|
|
|
$L__BB0_9:
|
|
mul.f32 %f310, %f1207, %f1211;
|
|
mul.f32 %f311, %f1208, %f1210;
|
|
sub.f32 %f312, %f310, %f311;
|
|
mul.f32 %f313, %f1208, %f1209;
|
|
mul.f32 %f314, %f1206, %f1211;
|
|
sub.f32 %f315, %f313, %f314;
|
|
mul.f32 %f316, %f1206, %f1210;
|
|
mul.f32 %f317, %f1207, %f1209;
|
|
sub.f32 %f318, %f316, %f317;
|
|
ld.global.u8 %rs34, [%rd3+3];
|
|
setp.eq.s16 %p17, %rs34, 0;
|
|
selp.f32 %f22, 0fBF800000, 0f3F800000, %p17;
|
|
mul.f32 %f319, %f312, %f22;
|
|
mul.f32 %f320, %f315, %f22;
|
|
mul.f32 %f321, %f318, %f22;
|
|
mul.f32 %f322, %f319, 0f00000000;
|
|
mul.f32 %f323, %f320, 0f00000000;
|
|
mul.f32 %f324, %f321, 0f00000000;
|
|
fma.rn.f32 %f325, %f1209, 0f3F5105EC, %f322;
|
|
fma.rn.f32 %f326, %f1210, 0f3F5105EC, %f323;
|
|
fma.rn.f32 %f327, %f1211, 0f3F5105EC, %f324;
|
|
mul.f32 %f23, %f1206, 0f3F13CD3A;
|
|
add.f32 %f24, %f23, %f325;
|
|
mul.f32 %f25, %f1207, 0f3F13CD3A;
|
|
add.f32 %f26, %f25, %f326;
|
|
mul.f32 %f27, %f1208, 0f3F13CD3A;
|
|
add.f32 %f28, %f27, %f327;
|
|
or.b16 %rs35, %rs24, %rs174;
|
|
or.b16 %rs15, %rs35, %rs173;
|
|
and.b16 %rs36, %rs15, 255;
|
|
setp.eq.s16 %p18, %rs36, 0;
|
|
mov.f32 %f1215, 0f00000000;
|
|
mov.f32 %f1212, %f1215;
|
|
mov.f32 %f1213, %f1215;
|
|
mov.f32 %f1214, %f1215;
|
|
@%p18 bra $L__BB0_11;
|
|
|
|
cvt.rn.f32.u16 %f328, %rs24;
|
|
div.rn.f32 %f329, %f328, 0f437F0000;
|
|
fma.rn.f32 %f330, %f329, 0f40000000, 0fBF800000;
|
|
and.b16 %rs38, %rs174, 255;
|
|
cvt.rn.f32.u16 %f331, %rs38;
|
|
div.rn.f32 %f332, %f331, 0f437F0000;
|
|
fma.rn.f32 %f333, %f332, 0f40000000, 0fBF800000;
|
|
and.b16 %rs39, %rs173, 255;
|
|
cvt.rn.f32.u16 %f334, %rs39;
|
|
div.rn.f32 %f335, %f334, 0f437F0000;
|
|
fma.rn.f32 %f336, %f335, 0f40000000, 0fBF800000;
|
|
mul.f32 %f337, %f333, %f333;
|
|
fma.rn.f32 %f338, %f330, %f330, %f337;
|
|
fma.rn.f32 %f339, %f336, %f336, %f338;
|
|
sqrt.rn.f32 %f340, %f339;
|
|
rcp.rn.f32 %f341, %f340;
|
|
mul.f32 %f1214, %f341, %f336;
|
|
mul.f32 %f1213, %f341, %f333;
|
|
mul.f32 %f1212, %f330, %f341;
|
|
|
|
$L__BB0_11:
|
|
mul.f32 %f345, %f1207, %f1214;
|
|
mul.f32 %f346, %f1208, %f1213;
|
|
sub.f32 %f347, %f345, %f346;
|
|
mul.f32 %f348, %f1208, %f1212;
|
|
mul.f32 %f349, %f1206, %f1214;
|
|
sub.f32 %f350, %f348, %f349;
|
|
mul.f32 %f351, %f1206, %f1213;
|
|
mul.f32 %f352, %f1207, %f1212;
|
|
sub.f32 %f353, %f351, %f352;
|
|
mul.f32 %f354, %f347, %f22;
|
|
mul.f32 %f355, %f350, %f22;
|
|
mul.f32 %f356, %f353, %f22;
|
|
mul.f32 %f357, %f1212, 0f3ED105EC;
|
|
mul.f32 %f358, %f1213, 0f3ED105EC;
|
|
mul.f32 %f359, %f1214, 0f3ED105EC;
|
|
mul.f32 %f360, %f354, 0f3F3504F3;
|
|
mul.f32 %f361, %f355, 0f3F3504F3;
|
|
mul.f32 %f362, %f356, 0f3F3504F3;
|
|
sub.f32 %f363, %f360, %f357;
|
|
sub.f32 %f364, %f361, %f358;
|
|
sub.f32 %f365, %f362, %f359;
|
|
add.f32 %f35, %f23, %f363;
|
|
add.f32 %f36, %f25, %f364;
|
|
add.f32 %f37, %f27, %f365;
|
|
mov.f32 %f1216, %f1215;
|
|
mov.f32 %f1217, %f1215;
|
|
@%p18 bra $L__BB0_13;
|
|
|
|
cvt.rn.f32.u16 %f366, %rs24;
|
|
div.rn.f32 %f367, %f366, 0f437F0000;
|
|
fma.rn.f32 %f368, %f367, 0f40000000, 0fBF800000;
|
|
and.b16 %rs42, %rs174, 255;
|
|
cvt.rn.f32.u16 %f369, %rs42;
|
|
div.rn.f32 %f370, %f369, 0f437F0000;
|
|
fma.rn.f32 %f371, %f370, 0f40000000, 0fBF800000;
|
|
and.b16 %rs43, %rs173, 255;
|
|
cvt.rn.f32.u16 %f372, %rs43;
|
|
div.rn.f32 %f373, %f372, 0f437F0000;
|
|
fma.rn.f32 %f374, %f373, 0f40000000, 0fBF800000;
|
|
mul.f32 %f375, %f371, %f371;
|
|
fma.rn.f32 %f376, %f368, %f368, %f375;
|
|
fma.rn.f32 %f377, %f374, %f374, %f376;
|
|
sqrt.rn.f32 %f378, %f377;
|
|
rcp.rn.f32 %f379, %f378;
|
|
mul.f32 %f1217, %f379, %f374;
|
|
mul.f32 %f1216, %f379, %f371;
|
|
mul.f32 %f1215, %f368, %f379;
|
|
|
|
$L__BB0_13:
|
|
mul.f32 %f392, %f1207, %f1217;
|
|
mul.f32 %f393, %f1208, %f1216;
|
|
sub.f32 %f394, %f392, %f393;
|
|
mul.f32 %f395, %f1208, %f1215;
|
|
mul.f32 %f396, %f1206, %f1217;
|
|
sub.f32 %f397, %f395, %f396;
|
|
mul.f32 %f398, %f1206, %f1216;
|
|
mul.f32 %f399, %f1207, %f1215;
|
|
sub.f32 %f400, %f398, %f399;
|
|
mul.f32 %f401, %f394, %f22;
|
|
mul.f32 %f402, %f397, %f22;
|
|
mul.f32 %f403, %f400, %f22;
|
|
mul.f32 %f404, %f1215, 0f3ED105EC;
|
|
mul.f32 %f405, %f1216, 0f3ED105EC;
|
|
mul.f32 %f406, %f1217, 0f3ED105EC;
|
|
mul.f32 %f407, %f401, 0fBF3504F3;
|
|
mul.f32 %f408, %f402, 0fBF3504F3;
|
|
mul.f32 %f409, %f403, 0fBF3504F3;
|
|
sub.f32 %f410, %f407, %f404;
|
|
sub.f32 %f411, %f408, %f405;
|
|
sub.f32 %f412, %f409, %f406;
|
|
add.f32 %f44, %f23, %f410;
|
|
add.f32 %f45, %f25, %f411;
|
|
add.f32 %f46, %f27, %f412;
|
|
setp.lt.s32 %p20, %r3, 1;
|
|
mov.f32 %f1248, 0f00000000;
|
|
mov.f32 %f1249, %f1248;
|
|
mov.f32 %f1250, %f1248;
|
|
mov.f32 %f1251, %f1248;
|
|
mov.f32 %f1252, %f1248;
|
|
mov.f32 %f1253, %f1248;
|
|
mov.f32 %f1254, %f1248;
|
|
mov.f32 %f1255, %f1248;
|
|
mov.f32 %f1256, %f1248;
|
|
mov.f32 %f1257, %f1248;
|
|
mov.f32 %f1258, %f1248;
|
|
mov.f32 %f1259, %f1248;
|
|
@%p20 bra $L__BB0_44;
|
|
|
|
cvt.rn.f32.s32 %f425, %r3;
|
|
rcp.rn.f32 %f47, %f425;
|
|
mul.f32 %f48, %f10, 0f3456BF95;
|
|
mul.f32 %f49, %f11, 0f3456BF95;
|
|
mul.f32 %f50, %f12, 0f3456BF95;
|
|
ld.const.u64 %rd4, [params+96];
|
|
mul.f32 %f426, %f1208, %f14;
|
|
mul.f32 %f427, %f1207, %f15;
|
|
sub.f32 %f51, %f426, %f427;
|
|
mul.f32 %f428, %f1206, %f15;
|
|
mul.f32 %f429, %f1208, %f13;
|
|
sub.f32 %f52, %f428, %f429;
|
|
mul.f32 %f430, %f1207, %f13;
|
|
mul.f32 %f431, %f1206, %f14;
|
|
sub.f32 %f53, %f430, %f431;
|
|
mov.u32 %r73, 0;
|
|
add.s64 %rd5, %rd1, 24;
|
|
mov.u64 %rd41, __cudart_i2opi_f;
|
|
abs.f32 %f494, %f48;
|
|
abs.f32 %f495, %f49;
|
|
max.f32 %f496, %f494, %f495;
|
|
abs.f32 %f497, %f50;
|
|
max.f32 %f498, %f496, %f497;
|
|
mov.u32 %r346, %r73;
|
|
|
|
$L__BB0_15:
|
|
mov.u32 %r348, %r73;
|
|
|
|
$L__BB0_16:
|
|
cvt.rn.f32.s32 %f1161, %r346;
|
|
mad.lo.s32 %r75, %r349, 1664525, 1013904223;
|
|
and.b32 %r76, %r75, 16777215;
|
|
cvt.rn.f32.u32 %f432, %r76;
|
|
fma.rn.f32 %f433, %f432, 0f33800000, %f1161;
|
|
mul.f32 %f79, %f47, %f433;
|
|
mad.lo.s32 %r349, %r75, 1664525, 1013904223;
|
|
and.b32 %r77, %r349, 16777215;
|
|
cvt.rn.f32.u32 %f434, %r77;
|
|
cvt.rn.f32.s32 %f435, %r348;
|
|
fma.rn.f32 %f436, %f434, 0f33800000, %f435;
|
|
mul.f32 %f437, %f47, %f436;
|
|
mul.f32 %f438, %f79, %f79;
|
|
mov.f32 %f439, 0f3F800000;
|
|
sub.f32 %f440, %f439, %f438;
|
|
mov.f32 %f441, 0f00000000;
|
|
max.f32 %f442, %f441, %f440;
|
|
sqrt.rn.f32 %f80, %f442;
|
|
mul.f32 %f81, %f437, 0f40C90FDB;
|
|
mul.f32 %f443, %f81, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r353, %f443;
|
|
cvt.rn.f32.s32 %f444, %r353;
|
|
mov.f32 %f445, 0fBFC90FDA;
|
|
fma.rn.f32 %f446, %f444, %f445, %f81;
|
|
mov.f32 %f447, 0fB3A22168;
|
|
fma.rn.f32 %f448, %f444, %f447, %f446;
|
|
mov.f32 %f449, 0fA7C234C5;
|
|
fma.rn.f32 %f1245, %f444, %f449, %f448;
|
|
abs.f32 %f83, %f81;
|
|
setp.ltu.f32 %p21, %f83, 0f47CE4780;
|
|
mov.f32 %f1242, %f1245;
|
|
@%p21 bra $L__BB0_24;
|
|
|
|
setp.eq.f32 %p22, %f83, 0f7F800000;
|
|
@%p22 bra $L__BB0_23;
|
|
bra.uni $L__BB0_18;
|
|
|
|
$L__BB0_23:
|
|
mov.f32 %f452, 0f00000000;
|
|
mul.rn.f32 %f1242, %f81, %f452;
|
|
mov.u32 %r353, 0;
|
|
bra.uni $L__BB0_24;
|
|
|
|
$L__BB0_18:
|
|
mov.b32 %r14, %f81;
|
|
bfe.u32 %r79, %r14, 23, 8;
|
|
mov.u64 %rd102, 0;
|
|
mov.u32 %r350, 0;
|
|
mov.u64 %rd100, %rd1;
|
|
mov.u64 %rd101, %rd41;
|
|
|
|
$L__BB0_19:
|
|
.pragma "nounroll";
|
|
mov.b32 %r329, %f81;
|
|
shl.b32 %r328, %r329, 8;
|
|
or.b32 %r327, %r328, -2147483648;
|
|
ld.global.nc.u32 %r81, [%rd101];
|
|
mad.wide.u32 %rd43, %r81, %r327, %rd102;
|
|
shr.u64 %rd102, %rd43, 32;
|
|
st.local.u32 [%rd100], %rd43;
|
|
add.s64 %rd101, %rd101, 4;
|
|
add.s64 %rd100, %rd100, 4;
|
|
add.s32 %r350, %r350, 1;
|
|
setp.ne.s32 %p23, %r350, 6;
|
|
@%p23 bra $L__BB0_19;
|
|
|
|
add.s32 %r334, %r79, -128;
|
|
mov.b32 %r333, %f81;
|
|
bfe.u32 %r332, %r333, 23, 8;
|
|
add.s32 %r331, %r332, -128;
|
|
shr.u32 %r330, %r331, 5;
|
|
st.local.u32 [%rd5], %rd102;
|
|
mov.u32 %r83, 6;
|
|
sub.s32 %r84, %r83, %r330;
|
|
mul.wide.s32 %rd44, %r84, 4;
|
|
add.s64 %rd45, %rd1, %rd44;
|
|
ld.local.u32 %r351, [%rd45];
|
|
ld.local.u32 %r352, [%rd45+-4];
|
|
and.b32 %r23, %r331, 31;
|
|
setp.eq.s32 %p24, %r23, 0;
|
|
@%p24 bra $L__BB0_22;
|
|
|
|
mov.b32 %r342, %f81;
|
|
bfe.u32 %r341, %r342, 23, 8;
|
|
add.s32 %r340, %r341, -128;
|
|
shr.u32 %r339, %r340, 5;
|
|
mov.u32 %r338, 4;
|
|
sub.s32 %r337, %r338, %r339;
|
|
mov.u32 %r85, 32;
|
|
sub.s32 %r86, %r85, %r23;
|
|
shr.u32 %r87, %r352, %r86;
|
|
shl.b32 %r88, %r351, %r23;
|
|
add.s32 %r351, %r87, %r88;
|
|
mul.wide.s32 %rd46, %r337, 4;
|
|
add.s64 %rd47, %rd1, %rd46;
|
|
ld.local.u32 %r89, [%rd47];
|
|
shr.u32 %r90, %r89, %r86;
|
|
shl.b32 %r91, %r352, %r23;
|
|
add.s32 %r352, %r90, %r91;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r335, %f81;
|
|
and.b32 %r92, %r335, -2147483648;
|
|
shr.u32 %r93, %r352, 30;
|
|
shl.b32 %r94, %r351, 2;
|
|
or.b32 %r95, %r93, %r94;
|
|
shr.u32 %r96, %r95, 31;
|
|
shr.u32 %r97, %r351, 30;
|
|
add.s32 %r98, %r96, %r97;
|
|
neg.s32 %r99, %r98;
|
|
setp.eq.s32 %p25, %r92, 0;
|
|
selp.b32 %r353, %r98, %r99, %p25;
|
|
setp.ne.s32 %p26, %r96, 0;
|
|
xor.b32 %r100, %r92, -2147483648;
|
|
selp.b32 %r101, %r100, %r92, %p26;
|
|
selp.b32 %r102, -1, 0, %p26;
|
|
xor.b32 %r103, %r95, %r102;
|
|
shl.b32 %r104, %r352, 2;
|
|
xor.b32 %r105, %r104, %r102;
|
|
cvt.u64.u32 %rd48, %r103;
|
|
cvt.u64.u32 %rd49, %r105;
|
|
bfi.b64 %rd50, %rd48, %rd49, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd50;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f450, %fd2;
|
|
setp.eq.s32 %p27, %r101, 0;
|
|
neg.f32 %f451, %f450;
|
|
selp.f32 %f1242, %f450, %f451, %p27;
|
|
|
|
$L__BB0_24:
|
|
add.s32 %r30, %r353, 1;
|
|
and.b32 %r31, %r30, 1;
|
|
setp.eq.s32 %p28, %r31, 0;
|
|
selp.f32 %f87, %f1242, 0f3F800000, %p28;
|
|
mul.rn.f32 %f88, %f1242, %f1242;
|
|
mov.f32 %f1243, 0fB94D4153;
|
|
@%p28 bra $L__BB0_26;
|
|
|
|
mov.f32 %f454, 0fBAB607ED;
|
|
mov.f32 %f455, 0f37CBAC00;
|
|
fma.rn.f32 %f1243, %f455, %f88, %f454;
|
|
|
|
$L__BB0_26:
|
|
selp.f32 %f456, 0f3C0885E4, 0f3D2AAABB, %p28;
|
|
fma.rn.f32 %f457, %f1243, %f88, %f456;
|
|
selp.f32 %f458, 0fBE2AAAA8, 0fBEFFFFFF, %p28;
|
|
fma.rn.f32 %f459, %f457, %f88, %f458;
|
|
mov.f32 %f460, 0f00000000;
|
|
fma.rn.f32 %f461, %f88, %f87, %f460;
|
|
fma.rn.f32 %f1244, %f459, %f461, %f87;
|
|
and.b32 %r107, %r30, 2;
|
|
setp.eq.s32 %p30, %r107, 0;
|
|
@%p30 bra $L__BB0_28;
|
|
|
|
mov.f32 %f463, 0fBF800000;
|
|
fma.rn.f32 %f1244, %f1244, %f463, %f460;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f1160, %f81, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r356, %f1160;
|
|
setp.ltu.f32 %p160, %f83, 0f47CE4780;
|
|
@%p160 bra $L__BB0_36;
|
|
|
|
setp.eq.f32 %p32, %f83, 0f7F800000;
|
|
@%p32 bra $L__BB0_35;
|
|
bra.uni $L__BB0_30;
|
|
|
|
$L__BB0_35:
|
|
mov.f32 %f466, 0f00000000;
|
|
mul.rn.f32 %f1245, %f81, %f466;
|
|
mov.u32 %r356, 0;
|
|
bra.uni $L__BB0_36;
|
|
|
|
$L__BB0_30:
|
|
mov.b32 %r32, %f81;
|
|
bfe.u32 %r108, %r32, 23, 8;
|
|
add.s32 %r33, %r108, -128;
|
|
shl.b32 %r109, %r32, 8;
|
|
or.b32 %r34, %r109, -2147483648;
|
|
shr.u32 %r35, %r33, 5;
|
|
mov.u64 %rd103, 0;
|
|
mov.u64 %rd104, %rd103;
|
|
|
|
$L__BB0_31:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd53, %rd103, 2;
|
|
mov.u64 %rd54, __cudart_i2opi_f;
|
|
add.s64 %rd55, %rd54, %rd53;
|
|
ld.global.nc.u32 %r110, [%rd55];
|
|
mad.wide.u32 %rd56, %r110, %r34, %rd104;
|
|
shr.u64 %rd104, %rd56, 32;
|
|
add.s64 %rd57, %rd1, %rd53;
|
|
st.local.u32 [%rd57], %rd56;
|
|
cvt.u32.u64 %r111, %rd103;
|
|
add.s32 %r112, %r111, 1;
|
|
cvt.s64.s32 %rd103, %r112;
|
|
setp.ne.s32 %p33, %r112, 6;
|
|
@%p33 bra $L__BB0_31;
|
|
|
|
st.local.u32 [%rd5], %rd104;
|
|
mov.u32 %r113, 4;
|
|
sub.s32 %r36, %r113, %r35;
|
|
mov.u32 %r114, 6;
|
|
sub.s32 %r115, %r114, %r35;
|
|
mul.wide.s32 %rd58, %r115, 4;
|
|
add.s64 %rd59, %rd1, %rd58;
|
|
ld.local.u32 %r354, [%rd59];
|
|
ld.local.u32 %r355, [%rd59+-4];
|
|
and.b32 %r39, %r33, 31;
|
|
setp.eq.s32 %p34, %r39, 0;
|
|
@%p34 bra $L__BB0_34;
|
|
|
|
mov.u32 %r116, 32;
|
|
sub.s32 %r117, %r116, %r39;
|
|
shr.u32 %r118, %r355, %r117;
|
|
shl.b32 %r119, %r354, %r39;
|
|
add.s32 %r354, %r118, %r119;
|
|
mul.wide.s32 %rd60, %r36, 4;
|
|
add.s64 %rd61, %rd1, %rd60;
|
|
ld.local.u32 %r120, [%rd61];
|
|
shr.u32 %r121, %r120, %r117;
|
|
shl.b32 %r122, %r355, %r39;
|
|
add.s32 %r355, %r121, %r122;
|
|
|
|
$L__BB0_34:
|
|
and.b32 %r123, %r32, -2147483648;
|
|
shr.u32 %r124, %r355, 30;
|
|
shl.b32 %r125, %r354, 2;
|
|
or.b32 %r126, %r124, %r125;
|
|
shr.u32 %r127, %r126, 31;
|
|
shr.u32 %r128, %r354, 30;
|
|
add.s32 %r129, %r127, %r128;
|
|
neg.s32 %r130, %r129;
|
|
setp.eq.s32 %p35, %r123, 0;
|
|
selp.b32 %r356, %r129, %r130, %p35;
|
|
setp.ne.s32 %p36, %r127, 0;
|
|
xor.b32 %r131, %r123, -2147483648;
|
|
selp.b32 %r132, %r131, %r123, %p36;
|
|
selp.b32 %r133, -1, 0, %p36;
|
|
xor.b32 %r134, %r126, %r133;
|
|
shl.b32 %r135, %r355, 2;
|
|
xor.b32 %r136, %r135, %r133;
|
|
cvt.u64.u32 %rd62, %r134;
|
|
cvt.u64.u32 %rd63, %r136;
|
|
bfi.b64 %rd64, %rd62, %rd63, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd64;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f464, %fd4;
|
|
setp.eq.s32 %p37, %r132, 0;
|
|
neg.f32 %f465, %f464;
|
|
selp.f32 %f1245, %f464, %f465, %p37;
|
|
|
|
$L__BB0_36:
|
|
mul.f32 %f97, %f80, %f1244;
|
|
and.b32 %r46, %r356, 1;
|
|
setp.eq.s32 %p38, %r46, 0;
|
|
mul.rn.f32 %f99, %f1245, %f1245;
|
|
mov.f32 %f1246, 0fB94D4153;
|
|
@%p38 bra $L__BB0_38;
|
|
|
|
mov.f32 %f468, 0fBAB607ED;
|
|
mov.f32 %f469, 0f37CBAC00;
|
|
fma.rn.f32 %f1246, %f469, %f99, %f468;
|
|
|
|
$L__BB0_38:
|
|
selp.f32 %f1162, %f1245, 0f3F800000, %p38;
|
|
selp.f32 %f470, 0f3C0885E4, 0f3D2AAABB, %p38;
|
|
fma.rn.f32 %f471, %f1246, %f99, %f470;
|
|
selp.f32 %f472, 0fBE2AAAA8, 0fBEFFFFFF, %p38;
|
|
fma.rn.f32 %f473, %f471, %f99, %f472;
|
|
mov.f32 %f474, 0f00000000;
|
|
fma.rn.f32 %f475, %f99, %f1162, %f474;
|
|
fma.rn.f32 %f1247, %f473, %f475, %f1162;
|
|
and.b32 %r138, %r356, 2;
|
|
setp.eq.s32 %p40, %r138, 0;
|
|
@%p40 bra $L__BB0_40;
|
|
|
|
mov.f32 %f477, 0fBF800000;
|
|
fma.rn.f32 %f1247, %f1247, %f477, %f474;
|
|
|
|
$L__BB0_40:
|
|
mul.f32 %f478, %f80, %f1247;
|
|
mul.f32 %f479, %f13, %f478;
|
|
mul.f32 %f480, %f14, %f478;
|
|
mul.f32 %f481, %f15, %f478;
|
|
fma.rn.f32 %f482, %f51, %f97, %f479;
|
|
fma.rn.f32 %f483, %f52, %f97, %f480;
|
|
fma.rn.f32 %f484, %f53, %f97, %f481;
|
|
fma.rn.f32 %f105, %f1206, %f79, %f482;
|
|
fma.rn.f32 %f106, %f1207, %f79, %f483;
|
|
fma.rn.f32 %f107, %f1208, %f79, %f484;
|
|
setp.leu.f32 %p41, %f106, 0f00000000;
|
|
setp.ne.s32 %p42, %r6, 0;
|
|
and.pred %p43, %p42, %p41;
|
|
@%p43 bra $L__BB0_42;
|
|
|
|
mov.f32 %f499, 0f38D1B717;
|
|
max.f32 %f491, %f498, %f499;
|
|
mov.f32 %f492, 0f6C4ECB8F;
|
|
mov.f32 %f493, 0f00000000;
|
|
mov.u32 %r175, 2;
|
|
mov.u32 %r176, 1;
|
|
mov.u32 %r177, 3;
|
|
mov.u32 %r180, 1065353216;
|
|
mov.u32 %r209, 0;
|
|
// begin inline asm
|
|
call(%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169,%r170),_optix_trace_typed_32,(%r209,%rd4,%f10,%f11,%f12,%f105,%f106,%f107,%f491,%f492,%f493,%r176,%r209,%r176,%r175,%r176,%r177,%r180,%r180,%r180,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209);
|
|
// end inline asm
|
|
mov.b32 %f500, %r139;
|
|
mov.b32 %f501, %r140;
|
|
mov.b32 %f502, %r141;
|
|
mul.f32 %f503, %f26, %f106;
|
|
fma.rn.f32 %f504, %f24, %f105, %f503;
|
|
fma.rn.f32 %f505, %f28, %f107, %f504;
|
|
cvt.sat.f32.f32 %f506, %f505;
|
|
fma.rn.f32 %f1254, %f506, %f500, %f1254;
|
|
fma.rn.f32 %f1255, %f506, %f501, %f1255;
|
|
fma.rn.f32 %f1256, %f506, %f502, %f1256;
|
|
mul.f32 %f507, %f36, %f106;
|
|
fma.rn.f32 %f508, %f35, %f105, %f507;
|
|
fma.rn.f32 %f509, %f37, %f107, %f508;
|
|
cvt.sat.f32.f32 %f510, %f509;
|
|
fma.rn.f32 %f1251, %f510, %f500, %f1251;
|
|
fma.rn.f32 %f1252, %f510, %f501, %f1252;
|
|
fma.rn.f32 %f1253, %f510, %f502, %f1253;
|
|
mul.f32 %f511, %f45, %f106;
|
|
fma.rn.f32 %f512, %f44, %f105, %f511;
|
|
fma.rn.f32 %f513, %f46, %f107, %f512;
|
|
cvt.sat.f32.f32 %f514, %f513;
|
|
fma.rn.f32 %f1248, %f514, %f500, %f1248;
|
|
fma.rn.f32 %f1249, %f514, %f501, %f1249;
|
|
fma.rn.f32 %f1250, %f514, %f502, %f1250;
|
|
mul.f32 %f515, %f1207, %f106;
|
|
fma.rn.f32 %f516, %f1206, %f105, %f515;
|
|
fma.rn.f32 %f517, %f1208, %f107, %f516;
|
|
cvt.sat.f32.f32 %f518, %f517;
|
|
fma.rn.f32 %f1257, %f518, %f500, %f1257;
|
|
fma.rn.f32 %f1258, %f518, %f501, %f1258;
|
|
fma.rn.f32 %f1259, %f518, %f502, %f1259;
|
|
|
|
$L__BB0_42:
|
|
add.s32 %r348, %r348, 1;
|
|
setp.lt.s32 %p44, %r348, %r3;
|
|
@%p44 bra $L__BB0_16;
|
|
|
|
add.s32 %r346, %r346, 1;
|
|
setp.lt.s32 %p45, %r346, %r3;
|
|
@%p45 bra $L__BB0_15;
|
|
|
|
$L__BB0_44:
|
|
mul.lo.s32 %r210, %r3, %r3;
|
|
cvt.rn.f32.s32 %f519, %r210;
|
|
rcp.rn.f32 %f520, %f519;
|
|
mul.f32 %f521, %f520, %f1257;
|
|
mul.f32 %f522, %f520, %f1258;
|
|
mul.f32 %f523, %f520, %f1259;
|
|
mul.f32 %f144, %f520, %f1254;
|
|
mul.f32 %f145, %f520, %f1255;
|
|
mul.f32 %f146, %f520, %f1256;
|
|
mul.f32 %f147, %f520, %f1251;
|
|
mul.f32 %f148, %f520, %f1252;
|
|
mul.f32 %f149, %f520, %f1253;
|
|
mul.f32 %f150, %f520, %f1248;
|
|
mul.f32 %f151, %f520, %f1249;
|
|
mul.f32 %f152, %f520, %f1250;
|
|
fma.rn.f32 %f153, %f520, %f1257, %f521;
|
|
fma.rn.f32 %f154, %f520, %f1258, %f522;
|
|
fma.rn.f32 %f155, %f520, %f1259, %f523;
|
|
ld.const.v4.f32 {%f524, %f525, %f526, %f527}, [params+576];
|
|
mul.f32 %f159, %f153, %f524;
|
|
mul.f32 %f160, %f154, %f525;
|
|
mul.f32 %f161, %f155, %f526;
|
|
ld.const.u32 %r49, [params+104];
|
|
and.b32 %r211, %r49, 1;
|
|
setp.eq.b32 %p46, %r211, 1;
|
|
mov.pred %p47, 0;
|
|
xor.pred %p48, %p46, %p47;
|
|
not.pred %p49, %p48;
|
|
@%p49 bra $L__BB0_118;
|
|
|
|
mov.f32 %f529, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f530, %f529;
|
|
add.f32 %f531, %f530, %f530;
|
|
mov.f32 %f532, 0f3EE66666;
|
|
sub.f32 %f533, %f532, %f531;
|
|
abs.f32 %f162, %f533;
|
|
abs.f32 %f163, %f159;
|
|
setp.lt.f32 %p50, %f163, 0f00800000;
|
|
mul.f32 %f534, %f163, 0f4B800000;
|
|
selp.f32 %f535, %f534, %f163, %p50;
|
|
selp.f32 %f536, 0fC3170000, 0fC2FE0000, %p50;
|
|
mov.b32 %r212, %f535;
|
|
and.b32 %r213, %r212, 8388607;
|
|
or.b32 %r214, %r213, 1065353216;
|
|
mov.b32 %f537, %r214;
|
|
shr.u32 %r215, %r212, 23;
|
|
cvt.rn.f32.u32 %f538, %r215;
|
|
add.f32 %f539, %f536, %f538;
|
|
setp.gt.f32 %p51, %f537, 0f3FB504F3;
|
|
mul.f32 %f540, %f537, 0f3F000000;
|
|
add.f32 %f541, %f539, 0f3F800000;
|
|
selp.f32 %f542, %f541, %f539, %p51;
|
|
selp.f32 %f543, %f540, %f537, %p51;
|
|
add.f32 %f544, %f543, 0fBF800000;
|
|
add.f32 %f545, %f543, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f546, %f545;
|
|
add.f32 %f547, %f544, %f544;
|
|
mul.f32 %f548, %f547, %f546;
|
|
mul.f32 %f549, %f548, %f548;
|
|
mov.f32 %f550, 0f3C4CAF63;
|
|
mov.f32 %f551, 0f3B18F0FE;
|
|
fma.rn.f32 %f552, %f551, %f549, %f550;
|
|
mov.f32 %f553, 0f3DAAAABD;
|
|
fma.rn.f32 %f554, %f552, %f549, %f553;
|
|
mul.rn.f32 %f555, %f554, %f549;
|
|
mul.rn.f32 %f556, %f555, %f548;
|
|
sub.f32 %f557, %f544, %f548;
|
|
add.f32 %f558, %f557, %f557;
|
|
neg.f32 %f559, %f548;
|
|
fma.rn.f32 %f560, %f559, %f544, %f558;
|
|
mul.rn.f32 %f561, %f546, %f560;
|
|
add.f32 %f562, %f556, %f548;
|
|
sub.f32 %f563, %f548, %f562;
|
|
add.f32 %f564, %f556, %f563;
|
|
add.f32 %f565, %f561, %f564;
|
|
add.f32 %f566, %f562, %f565;
|
|
sub.f32 %f567, %f562, %f566;
|
|
add.f32 %f568, %f565, %f567;
|
|
mov.f32 %f569, 0f3F317200;
|
|
mul.rn.f32 %f570, %f542, %f569;
|
|
mov.f32 %f571, 0f35BFBE8E;
|
|
mul.rn.f32 %f572, %f542, %f571;
|
|
add.f32 %f573, %f570, %f566;
|
|
sub.f32 %f574, %f570, %f573;
|
|
add.f32 %f575, %f566, %f574;
|
|
add.f32 %f576, %f568, %f575;
|
|
add.f32 %f577, %f572, %f576;
|
|
add.f32 %f578, %f573, %f577;
|
|
sub.f32 %f579, %f573, %f578;
|
|
add.f32 %f580, %f577, %f579;
|
|
mul.rn.f32 %f581, %f532, %f578;
|
|
neg.f32 %f582, %f581;
|
|
fma.rn.f32 %f583, %f532, %f578, %f582;
|
|
fma.rn.f32 %f584, %f532, %f580, %f583;
|
|
mov.f32 %f585, 0f00000000;
|
|
fma.rn.f32 %f586, %f585, %f578, %f584;
|
|
add.rn.f32 %f587, %f581, %f586;
|
|
neg.f32 %f588, %f587;
|
|
add.rn.f32 %f589, %f581, %f588;
|
|
add.rn.f32 %f590, %f589, %f586;
|
|
mov.b32 %r216, %f587;
|
|
setp.eq.s32 %p52, %r216, 1118925336;
|
|
add.s32 %r217, %r216, -1;
|
|
mov.b32 %f591, %r217;
|
|
add.f32 %f592, %f590, 0f37000000;
|
|
selp.f32 %f164, %f592, %f590, %p52;
|
|
selp.f32 %f593, %f591, %f587, %p52;
|
|
mov.f32 %f594, 0f3FB8AA3B;
|
|
mul.rn.f32 %f595, %f593, %f594;
|
|
cvt.rzi.f32.f32 %f596, %f595;
|
|
abs.f32 %f597, %f596;
|
|
setp.gt.f32 %p53, %f597, 0f42FC0000;
|
|
mov.b32 %r218, %f596;
|
|
and.b32 %r219, %r218, -2147483648;
|
|
or.b32 %r220, %r219, 1123811328;
|
|
mov.b32 %f598, %r220;
|
|
selp.f32 %f599, %f598, %f596, %p53;
|
|
mov.f32 %f600, 0fBF317218;
|
|
fma.rn.f32 %f601, %f599, %f600, %f593;
|
|
mov.f32 %f602, 0f3102E308;
|
|
fma.rn.f32 %f603, %f599, %f602, %f601;
|
|
mul.f32 %f604, %f603, 0f3FB8AA3B;
|
|
add.f32 %f605, %f599, 0f4B40007F;
|
|
mov.b32 %r221, %f605;
|
|
shl.b32 %r222, %r221, 23;
|
|
mov.b32 %f606, %r222;
|
|
ex2.approx.ftz.f32 %f607, %f604;
|
|
mul.f32 %f165, %f607, %f606;
|
|
setp.eq.f32 %p54, %f165, 0f7F800000;
|
|
mov.f32 %f1272, 0f7F800000;
|
|
@%p54 bra $L__BB0_47;
|
|
|
|
fma.rn.f32 %f1272, %f165, %f164, %f165;
|
|
|
|
$L__BB0_47:
|
|
setp.lt.f32 %p55, %f159, 0f00000000;
|
|
setp.eq.f32 %p56, %f162, 0f3F800000;
|
|
and.pred %p1, %p55, %p56;
|
|
setp.eq.f32 %p57, %f159, 0f00000000;
|
|
@%p57 bra $L__BB0_51;
|
|
bra.uni $L__BB0_48;
|
|
|
|
$L__BB0_51:
|
|
add.f32 %f612, %f159, %f159;
|
|
selp.f32 %f1274, %f612, 0f00000000, %p56;
|
|
bra.uni $L__BB0_52;
|
|
|
|
$L__BB0_136:
|
|
mov.f32 %f1132, 0f00000000;
|
|
mov.u32 %r358, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f1132;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f1132;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f1132;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs123, 0;
|
|
st.global.v4.u16 [%rd22], {%rs120, %rs121, %rs122, %rs123};
|
|
|
|
$L__BB0_137:
|
|
ld.const.u64 %rd88, [params+256];
|
|
cvta.to.global.u64 %rd89, %rd88;
|
|
ld.const.u32 %r321, [params+248];
|
|
mad.lo.s32 %r322, %r321, %r5, %r4;
|
|
mul.wide.u32 %rd90, %r322, 8;
|
|
add.s64 %rd23, %rd89, %rd90;
|
|
setp.eq.s32 %p157, %r358, 0;
|
|
@%p157 bra $L__BB0_139;
|
|
|
|
ld.global.v4.u16 {%rs130, %rs131, %rs132, %rs133}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1133, %rs130;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1134, %rs131;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1135, %rs132;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1136, %f1133, 0f00000000;
|
|
add.f32 %f1137, %f1134, 0f00000000;
|
|
add.f32 %f1138, %f1135, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1138;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1137;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1136;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs134, 0;
|
|
st.global.v4.u16 [%rd23], {%rs127, %rs128, %rs129, %rs134};
|
|
bra.uni $L__BB0_140;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f1141, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f1141;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f1141;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1141;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs138, 0;
|
|
st.global.v4.u16 [%rd23], {%rs135, %rs136, %rs137, %rs138};
|
|
|
|
$L__BB0_140:
|
|
ld.const.u64 %rd91, [params+272];
|
|
cvta.to.global.u64 %rd92, %rd91;
|
|
ld.const.u32 %r323, [params+264];
|
|
mad.lo.s32 %r324, %r323, %r5, %r4;
|
|
mul.wide.u32 %rd93, %r324, 8;
|
|
add.s64 %rd24, %rd92, %rd93;
|
|
@%p157 bra $L__BB0_142;
|
|
|
|
ld.global.v4.u16 {%rs145, %rs146, %rs147, %rs148}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1142, %rs145;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1143, %rs146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1144, %rs147;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1145, %f1142, 0f00000000;
|
|
add.f32 %f1146, %f1143, 0f00000000;
|
|
add.f32 %f1147, %f1144, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1147;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1145;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs149, 0;
|
|
st.global.v4.u16 [%rd24], {%rs142, %rs143, %rs144, %rs149};
|
|
bra.uni $L__BB0_143;
|
|
|
|
$L__BB0_142:
|
|
mov.f32 %f1150, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f1150;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f1150;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1150;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs153, 0;
|
|
st.global.v4.u16 [%rd24], {%rs150, %rs151, %rs152, %rs153};
|
|
|
|
$L__BB0_143:
|
|
ld.const.u64 %rd94, [params+288];
|
|
cvta.to.global.u64 %rd95, %rd94;
|
|
ld.const.u32 %r325, [params+280];
|
|
mad.lo.s32 %r326, %r325, %r5, %r4;
|
|
mul.wide.u32 %rd96, %r326, 8;
|
|
add.s64 %rd25, %rd95, %rd96;
|
|
@%p157 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs160, %rs161, %rs162, %rs163}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1151, %rs160;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1152, %rs161;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1153, %rs162;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1154, %f1151, 0f00000000;
|
|
add.f32 %f1155, %f1152, 0f00000000;
|
|
add.f32 %f1156, %f1153, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1156;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1155;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1154;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs164, 0;
|
|
st.global.v4.u16 [%rd25], {%rs157, %rs158, %rs159, %rs164};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1159, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs167, %f1159;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f1159;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1159;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs168, 0;
|
|
st.global.v4.u16 [%rd25], {%rs165, %rs166, %rs167, %rs168};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_48:
|
|
mov.b32 %r223, %f1272;
|
|
xor.b32 %r224, %r223, -2147483648;
|
|
mov.b32 %f608, %r224;
|
|
selp.f32 %f1274, %f608, %f1272, %p1;
|
|
setp.geu.f32 %p58, %f159, 0f00000000;
|
|
@%p58 bra $L__BB0_52;
|
|
|
|
mov.f32 %f609, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f610, %f609;
|
|
setp.eq.f32 %p59, %f610, 0f3EE66666;
|
|
@%p59 bra $L__BB0_52;
|
|
|
|
mov.f32 %f1274, 0f7FFFFFFF;
|
|
|
|
$L__BB0_52:
|
|
add.f32 %f613, %f163, 0f3EE66666;
|
|
mov.b32 %r225, %f613;
|
|
setp.lt.s32 %p61, %r225, 2139095040;
|
|
@%p61 bra $L__BB0_57;
|
|
|
|
setp.gtu.f32 %p62, %f163, 0f7F800000;
|
|
@%p62 bra $L__BB0_56;
|
|
bra.uni $L__BB0_54;
|
|
|
|
$L__BB0_56:
|
|
add.f32 %f1274, %f159, 0f3EE66666;
|
|
bra.uni $L__BB0_57;
|
|
|
|
$L__BB0_54:
|
|
setp.neu.f32 %p63, %f163, 0f7F800000;
|
|
@%p63 bra $L__BB0_57;
|
|
|
|
selp.f32 %f1274, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_57:
|
|
setp.eq.f32 %p64, %f159, 0f3F800000;
|
|
selp.f32 %f174, 0f3F800000, %f1274, %p64;
|
|
abs.f32 %f175, %f160;
|
|
setp.lt.f32 %p65, %f175, 0f00800000;
|
|
mul.f32 %f615, %f175, 0f4B800000;
|
|
selp.f32 %f616, %f615, %f175, %p65;
|
|
selp.f32 %f617, 0fC3170000, 0fC2FE0000, %p65;
|
|
mov.b32 %r226, %f616;
|
|
and.b32 %r227, %r226, 8388607;
|
|
or.b32 %r228, %r227, 1065353216;
|
|
mov.b32 %f618, %r228;
|
|
shr.u32 %r229, %r226, 23;
|
|
cvt.rn.f32.u32 %f619, %r229;
|
|
add.f32 %f620, %f617, %f619;
|
|
setp.gt.f32 %p66, %f618, 0f3FB504F3;
|
|
mul.f32 %f621, %f618, 0f3F000000;
|
|
add.f32 %f622, %f620, 0f3F800000;
|
|
selp.f32 %f623, %f622, %f620, %p66;
|
|
selp.f32 %f624, %f621, %f618, %p66;
|
|
add.f32 %f625, %f624, 0fBF800000;
|
|
add.f32 %f626, %f624, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f627, %f626;
|
|
add.f32 %f628, %f625, %f625;
|
|
mul.f32 %f629, %f628, %f627;
|
|
mul.f32 %f630, %f629, %f629;
|
|
mov.f32 %f631, 0f3C4CAF63;
|
|
mov.f32 %f632, 0f3B18F0FE;
|
|
fma.rn.f32 %f633, %f632, %f630, %f631;
|
|
mov.f32 %f634, 0f3DAAAABD;
|
|
fma.rn.f32 %f635, %f633, %f630, %f634;
|
|
mul.rn.f32 %f636, %f635, %f630;
|
|
mul.rn.f32 %f637, %f636, %f629;
|
|
sub.f32 %f638, %f625, %f629;
|
|
add.f32 %f639, %f638, %f638;
|
|
neg.f32 %f640, %f629;
|
|
fma.rn.f32 %f641, %f640, %f625, %f639;
|
|
mul.rn.f32 %f642, %f627, %f641;
|
|
add.f32 %f643, %f637, %f629;
|
|
sub.f32 %f644, %f629, %f643;
|
|
add.f32 %f645, %f637, %f644;
|
|
add.f32 %f646, %f642, %f645;
|
|
add.f32 %f647, %f643, %f646;
|
|
sub.f32 %f648, %f643, %f647;
|
|
add.f32 %f649, %f646, %f648;
|
|
mov.f32 %f650, 0f3F317200;
|
|
mul.rn.f32 %f651, %f623, %f650;
|
|
mov.f32 %f652, 0f35BFBE8E;
|
|
mul.rn.f32 %f653, %f623, %f652;
|
|
add.f32 %f654, %f651, %f647;
|
|
sub.f32 %f655, %f651, %f654;
|
|
add.f32 %f656, %f647, %f655;
|
|
add.f32 %f657, %f649, %f656;
|
|
add.f32 %f658, %f653, %f657;
|
|
add.f32 %f659, %f654, %f658;
|
|
sub.f32 %f660, %f654, %f659;
|
|
add.f32 %f661, %f658, %f660;
|
|
mov.f32 %f662, 0f3EE66666;
|
|
mul.rn.f32 %f663, %f662, %f659;
|
|
neg.f32 %f664, %f663;
|
|
fma.rn.f32 %f665, %f662, %f659, %f664;
|
|
fma.rn.f32 %f666, %f662, %f661, %f665;
|
|
mov.f32 %f667, 0f00000000;
|
|
fma.rn.f32 %f668, %f667, %f659, %f666;
|
|
add.rn.f32 %f669, %f663, %f668;
|
|
neg.f32 %f670, %f669;
|
|
add.rn.f32 %f671, %f663, %f670;
|
|
add.rn.f32 %f672, %f671, %f668;
|
|
mov.b32 %r230, %f669;
|
|
setp.eq.s32 %p67, %r230, 1118925336;
|
|
add.s32 %r231, %r230, -1;
|
|
mov.b32 %f673, %r231;
|
|
add.f32 %f674, %f672, 0f37000000;
|
|
selp.f32 %f176, %f674, %f672, %p67;
|
|
selp.f32 %f675, %f673, %f669, %p67;
|
|
mov.f32 %f676, 0f3FB8AA3B;
|
|
mul.rn.f32 %f677, %f675, %f676;
|
|
cvt.rzi.f32.f32 %f678, %f677;
|
|
abs.f32 %f679, %f678;
|
|
setp.gt.f32 %p68, %f679, 0f42FC0000;
|
|
mov.b32 %r232, %f678;
|
|
and.b32 %r233, %r232, -2147483648;
|
|
or.b32 %r234, %r233, 1123811328;
|
|
mov.b32 %f680, %r234;
|
|
selp.f32 %f681, %f680, %f678, %p68;
|
|
mov.f32 %f682, 0fBF317218;
|
|
fma.rn.f32 %f683, %f681, %f682, %f675;
|
|
mov.f32 %f684, 0f3102E308;
|
|
fma.rn.f32 %f685, %f681, %f684, %f683;
|
|
mul.f32 %f686, %f685, 0f3FB8AA3B;
|
|
add.f32 %f687, %f681, 0f4B40007F;
|
|
mov.b32 %r235, %f687;
|
|
shl.b32 %r236, %r235, 23;
|
|
mov.b32 %f688, %r236;
|
|
ex2.approx.ftz.f32 %f689, %f686;
|
|
mul.f32 %f177, %f689, %f688;
|
|
setp.eq.f32 %p69, %f177, 0f7F800000;
|
|
mov.f32 %f1275, 0f7F800000;
|
|
@%p69 bra $L__BB0_59;
|
|
|
|
fma.rn.f32 %f1275, %f177, %f176, %f177;
|
|
|
|
$L__BB0_59:
|
|
setp.lt.f32 %p70, %f160, 0f00000000;
|
|
and.pred %p2, %p70, %p56;
|
|
setp.eq.f32 %p72, %f160, 0f00000000;
|
|
@%p72 bra $L__BB0_63;
|
|
bra.uni $L__BB0_60;
|
|
|
|
$L__BB0_63:
|
|
add.f32 %f694, %f160, %f160;
|
|
selp.f32 %f1277, %f694, 0f00000000, %p56;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_60:
|
|
mov.b32 %r237, %f1275;
|
|
xor.b32 %r238, %r237, -2147483648;
|
|
mov.b32 %f690, %r238;
|
|
selp.f32 %f1277, %f690, %f1275, %p2;
|
|
setp.geu.f32 %p73, %f160, 0f00000000;
|
|
@%p73 bra $L__BB0_64;
|
|
|
|
mov.f32 %f691, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f692, %f691;
|
|
setp.eq.f32 %p74, %f692, 0f3EE66666;
|
|
@%p74 bra $L__BB0_64;
|
|
|
|
mov.f32 %f1277, 0f7FFFFFFF;
|
|
|
|
$L__BB0_64:
|
|
add.f32 %f695, %f175, 0f3EE66666;
|
|
mov.b32 %r239, %f695;
|
|
setp.lt.s32 %p76, %r239, 2139095040;
|
|
@%p76 bra $L__BB0_69;
|
|
|
|
setp.gtu.f32 %p77, %f175, 0f7F800000;
|
|
@%p77 bra $L__BB0_68;
|
|
bra.uni $L__BB0_66;
|
|
|
|
$L__BB0_68:
|
|
add.f32 %f1277, %f160, 0f3EE66666;
|
|
bra.uni $L__BB0_69;
|
|
|
|
$L__BB0_66:
|
|
setp.neu.f32 %p78, %f175, 0f7F800000;
|
|
@%p78 bra $L__BB0_69;
|
|
|
|
selp.f32 %f1277, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_69:
|
|
setp.eq.f32 %p79, %f160, 0f3F800000;
|
|
selp.f32 %f186, 0f3F800000, %f1277, %p79;
|
|
abs.f32 %f187, %f161;
|
|
setp.lt.f32 %p80, %f187, 0f00800000;
|
|
mul.f32 %f697, %f187, 0f4B800000;
|
|
selp.f32 %f698, %f697, %f187, %p80;
|
|
selp.f32 %f699, 0fC3170000, 0fC2FE0000, %p80;
|
|
mov.b32 %r240, %f698;
|
|
and.b32 %r241, %r240, 8388607;
|
|
or.b32 %r242, %r241, 1065353216;
|
|
mov.b32 %f700, %r242;
|
|
shr.u32 %r243, %r240, 23;
|
|
cvt.rn.f32.u32 %f701, %r243;
|
|
add.f32 %f702, %f699, %f701;
|
|
setp.gt.f32 %p81, %f700, 0f3FB504F3;
|
|
mul.f32 %f703, %f700, 0f3F000000;
|
|
add.f32 %f704, %f702, 0f3F800000;
|
|
selp.f32 %f705, %f704, %f702, %p81;
|
|
selp.f32 %f706, %f703, %f700, %p81;
|
|
add.f32 %f707, %f706, 0fBF800000;
|
|
add.f32 %f708, %f706, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f709, %f708;
|
|
add.f32 %f710, %f707, %f707;
|
|
mul.f32 %f711, %f710, %f709;
|
|
mul.f32 %f712, %f711, %f711;
|
|
mov.f32 %f713, 0f3C4CAF63;
|
|
mov.f32 %f714, 0f3B18F0FE;
|
|
fma.rn.f32 %f715, %f714, %f712, %f713;
|
|
mov.f32 %f716, 0f3DAAAABD;
|
|
fma.rn.f32 %f717, %f715, %f712, %f716;
|
|
mul.rn.f32 %f718, %f717, %f712;
|
|
mul.rn.f32 %f719, %f718, %f711;
|
|
sub.f32 %f720, %f707, %f711;
|
|
add.f32 %f721, %f720, %f720;
|
|
neg.f32 %f722, %f711;
|
|
fma.rn.f32 %f723, %f722, %f707, %f721;
|
|
mul.rn.f32 %f724, %f709, %f723;
|
|
add.f32 %f725, %f719, %f711;
|
|
sub.f32 %f726, %f711, %f725;
|
|
add.f32 %f727, %f719, %f726;
|
|
add.f32 %f728, %f724, %f727;
|
|
add.f32 %f729, %f725, %f728;
|
|
sub.f32 %f730, %f725, %f729;
|
|
add.f32 %f731, %f728, %f730;
|
|
mov.f32 %f732, 0f3F317200;
|
|
mul.rn.f32 %f733, %f705, %f732;
|
|
mov.f32 %f734, 0f35BFBE8E;
|
|
mul.rn.f32 %f735, %f705, %f734;
|
|
add.f32 %f736, %f733, %f729;
|
|
sub.f32 %f737, %f733, %f736;
|
|
add.f32 %f738, %f729, %f737;
|
|
add.f32 %f739, %f731, %f738;
|
|
add.f32 %f740, %f735, %f739;
|
|
add.f32 %f741, %f736, %f740;
|
|
sub.f32 %f742, %f736, %f741;
|
|
add.f32 %f743, %f740, %f742;
|
|
mov.f32 %f744, 0f3EE66666;
|
|
mul.rn.f32 %f745, %f744, %f741;
|
|
neg.f32 %f746, %f745;
|
|
fma.rn.f32 %f747, %f744, %f741, %f746;
|
|
fma.rn.f32 %f748, %f744, %f743, %f747;
|
|
mov.f32 %f749, 0f00000000;
|
|
fma.rn.f32 %f750, %f749, %f741, %f748;
|
|
add.rn.f32 %f751, %f745, %f750;
|
|
neg.f32 %f752, %f751;
|
|
add.rn.f32 %f753, %f745, %f752;
|
|
add.rn.f32 %f754, %f753, %f750;
|
|
mov.b32 %r244, %f751;
|
|
setp.eq.s32 %p82, %r244, 1118925336;
|
|
add.s32 %r245, %r244, -1;
|
|
mov.b32 %f755, %r245;
|
|
add.f32 %f756, %f754, 0f37000000;
|
|
selp.f32 %f188, %f756, %f754, %p82;
|
|
selp.f32 %f757, %f755, %f751, %p82;
|
|
mov.f32 %f758, 0f3FB8AA3B;
|
|
mul.rn.f32 %f759, %f757, %f758;
|
|
cvt.rzi.f32.f32 %f760, %f759;
|
|
abs.f32 %f761, %f760;
|
|
setp.gt.f32 %p83, %f761, 0f42FC0000;
|
|
mov.b32 %r246, %f760;
|
|
and.b32 %r247, %r246, -2147483648;
|
|
or.b32 %r248, %r247, 1123811328;
|
|
mov.b32 %f762, %r248;
|
|
selp.f32 %f763, %f762, %f760, %p83;
|
|
mov.f32 %f764, 0fBF317218;
|
|
fma.rn.f32 %f765, %f763, %f764, %f757;
|
|
mov.f32 %f766, 0f3102E308;
|
|
fma.rn.f32 %f767, %f763, %f766, %f765;
|
|
mul.f32 %f768, %f767, 0f3FB8AA3B;
|
|
add.f32 %f769, %f763, 0f4B40007F;
|
|
mov.b32 %r249, %f769;
|
|
shl.b32 %r250, %r249, 23;
|
|
mov.b32 %f770, %r250;
|
|
ex2.approx.ftz.f32 %f771, %f768;
|
|
mul.f32 %f189, %f771, %f770;
|
|
setp.eq.f32 %p84, %f189, 0f7F800000;
|
|
mov.f32 %f1278, 0f7F800000;
|
|
@%p84 bra $L__BB0_71;
|
|
|
|
fma.rn.f32 %f1278, %f189, %f188, %f189;
|
|
|
|
$L__BB0_71:
|
|
setp.lt.f32 %p85, %f161, 0f00000000;
|
|
and.pred %p3, %p85, %p56;
|
|
setp.eq.f32 %p87, %f161, 0f00000000;
|
|
@%p87 bra $L__BB0_75;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_75:
|
|
add.f32 %f776, %f161, %f161;
|
|
selp.f32 %f1280, %f776, 0f00000000, %p56;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_72:
|
|
mov.b32 %r251, %f1278;
|
|
xor.b32 %r252, %r251, -2147483648;
|
|
mov.b32 %f772, %r252;
|
|
selp.f32 %f1280, %f772, %f1278, %p3;
|
|
setp.geu.f32 %p88, %f161, 0f00000000;
|
|
@%p88 bra $L__BB0_76;
|
|
|
|
mov.f32 %f773, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f774, %f773;
|
|
setp.eq.f32 %p89, %f774, 0f3EE66666;
|
|
@%p89 bra $L__BB0_76;
|
|
|
|
mov.f32 %f1280, 0f7FFFFFFF;
|
|
|
|
$L__BB0_76:
|
|
add.f32 %f777, %f187, 0f3EE66666;
|
|
mov.b32 %r253, %f777;
|
|
setp.lt.s32 %p91, %r253, 2139095040;
|
|
@%p91 bra $L__BB0_81;
|
|
|
|
setp.gtu.f32 %p92, %f187, 0f7F800000;
|
|
@%p92 bra $L__BB0_80;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f1280, %f161, 0f3EE66666;
|
|
bra.uni $L__BB0_81;
|
|
|
|
$L__BB0_78:
|
|
setp.neu.f32 %p93, %f187, 0f7F800000;
|
|
@%p93 bra $L__BB0_81;
|
|
|
|
selp.f32 %f1280, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_81:
|
|
setp.eq.f32 %p94, %f161, 0f3F800000;
|
|
mov.f32 %f779, 0f3F800000;
|
|
selp.f32 %f780, 0f3F800000, %f1280, %p94;
|
|
min.f32 %f781, %f174, %f779;
|
|
mov.f32 %f782, 0f00000000;
|
|
max.f32 %f198, %f782, %f781;
|
|
min.f32 %f783, %f186, %f779;
|
|
max.f32 %f199, %f782, %f783;
|
|
min.f32 %f784, %f780, %f779;
|
|
max.f32 %f200, %f782, %f784;
|
|
mov.f32 %f788, 0f3ED55555;
|
|
abs.f32 %f202, %f198;
|
|
setp.lt.f32 %p95, %f202, 0f00800000;
|
|
mul.f32 %f790, %f202, 0f4B800000;
|
|
selp.f32 %f791, %f790, %f202, %p95;
|
|
selp.f32 %f792, 0fC3170000, 0fC2FE0000, %p95;
|
|
mov.b32 %r256, %f791;
|
|
and.b32 %r257, %r256, 8388607;
|
|
or.b32 %r258, %r257, 1065353216;
|
|
mov.b32 %f793, %r258;
|
|
shr.u32 %r259, %r256, 23;
|
|
cvt.rn.f32.u32 %f794, %r259;
|
|
add.f32 %f795, %f792, %f794;
|
|
setp.gt.f32 %p96, %f793, 0f3FB504F3;
|
|
mul.f32 %f796, %f793, 0f3F000000;
|
|
add.f32 %f797, %f795, 0f3F800000;
|
|
selp.f32 %f798, %f797, %f795, %p96;
|
|
selp.f32 %f799, %f796, %f793, %p96;
|
|
add.f32 %f800, %f799, 0fBF800000;
|
|
add.f32 %f801, %f799, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f802, %f801;
|
|
add.f32 %f803, %f800, %f800;
|
|
mul.f32 %f804, %f803, %f802;
|
|
mul.f32 %f805, %f804, %f804;
|
|
mov.f32 %f806, 0f3C4CAF63;
|
|
mov.f32 %f807, 0f3B18F0FE;
|
|
fma.rn.f32 %f808, %f807, %f805, %f806;
|
|
mov.f32 %f809, 0f3DAAAABD;
|
|
fma.rn.f32 %f810, %f808, %f805, %f809;
|
|
mul.rn.f32 %f811, %f810, %f805;
|
|
mul.rn.f32 %f812, %f811, %f804;
|
|
sub.f32 %f813, %f800, %f804;
|
|
add.f32 %f814, %f813, %f813;
|
|
neg.f32 %f815, %f804;
|
|
fma.rn.f32 %f816, %f815, %f800, %f814;
|
|
mul.rn.f32 %f817, %f802, %f816;
|
|
add.f32 %f818, %f812, %f804;
|
|
sub.f32 %f819, %f804, %f818;
|
|
add.f32 %f820, %f812, %f819;
|
|
add.f32 %f821, %f817, %f820;
|
|
add.f32 %f822, %f818, %f821;
|
|
sub.f32 %f823, %f818, %f822;
|
|
add.f32 %f824, %f821, %f823;
|
|
mov.f32 %f825, 0f3F317200;
|
|
mul.rn.f32 %f826, %f798, %f825;
|
|
mov.f32 %f827, 0f35BFBE8E;
|
|
mul.rn.f32 %f828, %f798, %f827;
|
|
add.f32 %f829, %f826, %f822;
|
|
sub.f32 %f830, %f826, %f829;
|
|
add.f32 %f831, %f822, %f830;
|
|
add.f32 %f832, %f824, %f831;
|
|
add.f32 %f833, %f828, %f832;
|
|
add.f32 %f834, %f829, %f833;
|
|
sub.f32 %f835, %f829, %f834;
|
|
add.f32 %f836, %f833, %f835;
|
|
mul.rn.f32 %f837, %f788, %f834;
|
|
neg.f32 %f838, %f837;
|
|
fma.rn.f32 %f839, %f788, %f834, %f838;
|
|
fma.rn.f32 %f840, %f788, %f836, %f839;
|
|
fma.rn.f32 %f841, %f782, %f834, %f840;
|
|
add.rn.f32 %f842, %f837, %f841;
|
|
neg.f32 %f843, %f842;
|
|
add.rn.f32 %f844, %f837, %f843;
|
|
add.rn.f32 %f845, %f844, %f841;
|
|
mov.b32 %r260, %f842;
|
|
setp.eq.s32 %p97, %r260, 1118925336;
|
|
add.s32 %r261, %r260, -1;
|
|
mov.b32 %f846, %r261;
|
|
add.f32 %f847, %f845, 0f37000000;
|
|
selp.f32 %f203, %f847, %f845, %p97;
|
|
selp.f32 %f848, %f846, %f842, %p97;
|
|
mov.f32 %f849, 0f3FB8AA3B;
|
|
mul.rn.f32 %f850, %f848, %f849;
|
|
cvt.rzi.f32.f32 %f851, %f850;
|
|
abs.f32 %f852, %f851;
|
|
setp.gt.f32 %p98, %f852, 0f42FC0000;
|
|
mov.b32 %r262, %f851;
|
|
and.b32 %r263, %r262, -2147483648;
|
|
or.b32 %r264, %r263, 1123811328;
|
|
mov.b32 %f853, %r264;
|
|
selp.f32 %f854, %f853, %f851, %p98;
|
|
mov.f32 %f855, 0fBF317218;
|
|
fma.rn.f32 %f856, %f854, %f855, %f848;
|
|
mov.f32 %f857, 0f3102E308;
|
|
fma.rn.f32 %f858, %f854, %f857, %f856;
|
|
mul.f32 %f859, %f858, 0f3FB8AA3B;
|
|
add.f32 %f860, %f854, 0f4B40007F;
|
|
mov.b32 %r265, %f860;
|
|
shl.b32 %r266, %r265, 23;
|
|
mov.b32 %f861, %r266;
|
|
ex2.approx.ftz.f32 %f862, %f859;
|
|
mul.f32 %f204, %f862, %f861;
|
|
setp.eq.f32 %p99, %f204, 0f7F800000;
|
|
mov.f32 %f1281, 0f7F800000;
|
|
@%p99 bra $L__BB0_83;
|
|
|
|
fma.rn.f32 %f1281, %f204, %f203, %f204;
|
|
|
|
$L__BB0_83:
|
|
mov.f32 %f1188, 0f00000000;
|
|
max.f32 %f1187, %f1188, %f781;
|
|
mov.f32 %f1168, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1167, %f1168;
|
|
add.f32 %f1166, %f1167, %f1167;
|
|
mov.f32 %f1165, 0f3ED55555;
|
|
sub.f32 %f1164, %f1165, %f1166;
|
|
abs.f32 %f1163, %f1164;
|
|
setp.lt.f32 %p100, %f1187, 0f00000000;
|
|
setp.eq.f32 %p101, %f1163, 0f3F800000;
|
|
and.pred %p4, %p100, %p101;
|
|
setp.eq.f32 %p102, %f1187, 0f00000000;
|
|
@%p102 bra $L__BB0_87;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_87:
|
|
mov.f32 %f1205, 0f00000000;
|
|
max.f32 %f1204, %f1205, %f781;
|
|
add.f32 %f867, %f1204, %f1204;
|
|
selp.f32 %f1283, %f867, 0f00000000, %p101;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_84:
|
|
mov.f32 %f1190, 0f00000000;
|
|
max.f32 %f1189, %f1190, %f781;
|
|
mov.b32 %r267, %f1281;
|
|
xor.b32 %r268, %r267, -2147483648;
|
|
mov.b32 %f863, %r268;
|
|
selp.f32 %f1283, %f863, %f1281, %p4;
|
|
setp.geu.f32 %p103, %f1189, 0f00000000;
|
|
@%p103 bra $L__BB0_88;
|
|
|
|
mov.f32 %f864, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f865, %f864;
|
|
setp.eq.f32 %p104, %f865, 0f3ED55555;
|
|
@%p104 bra $L__BB0_88;
|
|
|
|
mov.f32 %f1283, 0f7FFFFFFF;
|
|
|
|
$L__BB0_88:
|
|
mov.f32 %f1193, 0f00000000;
|
|
max.f32 %f1192, %f1193, %f781;
|
|
abs.f32 %f1191, %f1192;
|
|
add.f32 %f868, %f1191, 0f3ED55555;
|
|
mov.b32 %r269, %f868;
|
|
setp.lt.s32 %p106, %r269, 2139095040;
|
|
@%p106 bra $L__BB0_93;
|
|
|
|
mov.f32 %f1198, 0f00000000;
|
|
max.f32 %f1197, %f1198, %f781;
|
|
abs.f32 %f1196, %f1197;
|
|
setp.gtu.f32 %p107, %f1196, 0f7F800000;
|
|
@%p107 bra $L__BB0_92;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_92:
|
|
mov.f32 %f1203, 0f00000000;
|
|
max.f32 %f1202, %f1203, %f781;
|
|
add.f32 %f1283, %f1202, 0f3ED55555;
|
|
bra.uni $L__BB0_93;
|
|
|
|
$L__BB0_90:
|
|
mov.f32 %f1201, 0f00000000;
|
|
max.f32 %f1200, %f1201, %f781;
|
|
abs.f32 %f1199, %f1200;
|
|
setp.neu.f32 %p108, %f1199, 0f7F800000;
|
|
@%p108 bra $L__BB0_93;
|
|
|
|
selp.f32 %f1283, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_93:
|
|
abs.f32 %f213, %f199;
|
|
setp.lt.f32 %p109, %f213, 0f00800000;
|
|
mul.f32 %f870, %f213, 0f4B800000;
|
|
selp.f32 %f871, %f870, %f213, %p109;
|
|
selp.f32 %f872, 0fC3170000, 0fC2FE0000, %p109;
|
|
mov.b32 %r270, %f871;
|
|
and.b32 %r271, %r270, 8388607;
|
|
or.b32 %r272, %r271, 1065353216;
|
|
mov.b32 %f873, %r272;
|
|
shr.u32 %r273, %r270, 23;
|
|
cvt.rn.f32.u32 %f874, %r273;
|
|
add.f32 %f875, %f872, %f874;
|
|
setp.gt.f32 %p110, %f873, 0f3FB504F3;
|
|
mul.f32 %f876, %f873, 0f3F000000;
|
|
add.f32 %f877, %f875, 0f3F800000;
|
|
selp.f32 %f878, %f877, %f875, %p110;
|
|
selp.f32 %f879, %f876, %f873, %p110;
|
|
add.f32 %f880, %f879, 0fBF800000;
|
|
add.f32 %f881, %f879, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f882, %f881;
|
|
add.f32 %f883, %f880, %f880;
|
|
mul.f32 %f884, %f883, %f882;
|
|
mul.f32 %f885, %f884, %f884;
|
|
mov.f32 %f886, 0f3C4CAF63;
|
|
mov.f32 %f887, 0f3B18F0FE;
|
|
fma.rn.f32 %f888, %f887, %f885, %f886;
|
|
mov.f32 %f889, 0f3DAAAABD;
|
|
fma.rn.f32 %f890, %f888, %f885, %f889;
|
|
mul.rn.f32 %f891, %f890, %f885;
|
|
mul.rn.f32 %f892, %f891, %f884;
|
|
sub.f32 %f893, %f880, %f884;
|
|
add.f32 %f894, %f893, %f893;
|
|
neg.f32 %f895, %f884;
|
|
fma.rn.f32 %f896, %f895, %f880, %f894;
|
|
mul.rn.f32 %f897, %f882, %f896;
|
|
add.f32 %f898, %f892, %f884;
|
|
sub.f32 %f899, %f884, %f898;
|
|
add.f32 %f900, %f892, %f899;
|
|
add.f32 %f901, %f897, %f900;
|
|
add.f32 %f902, %f898, %f901;
|
|
sub.f32 %f903, %f898, %f902;
|
|
add.f32 %f904, %f901, %f903;
|
|
mov.f32 %f905, 0f3F317200;
|
|
mul.rn.f32 %f906, %f878, %f905;
|
|
mov.f32 %f907, 0f35BFBE8E;
|
|
mul.rn.f32 %f908, %f878, %f907;
|
|
add.f32 %f909, %f906, %f902;
|
|
sub.f32 %f910, %f906, %f909;
|
|
add.f32 %f911, %f902, %f910;
|
|
add.f32 %f912, %f904, %f911;
|
|
add.f32 %f913, %f908, %f912;
|
|
add.f32 %f914, %f909, %f913;
|
|
sub.f32 %f915, %f909, %f914;
|
|
add.f32 %f916, %f913, %f915;
|
|
mov.f32 %f917, 0f3ED55555;
|
|
mul.rn.f32 %f918, %f917, %f914;
|
|
neg.f32 %f919, %f918;
|
|
fma.rn.f32 %f920, %f917, %f914, %f919;
|
|
fma.rn.f32 %f921, %f917, %f916, %f920;
|
|
mov.f32 %f922, 0f00000000;
|
|
fma.rn.f32 %f923, %f922, %f914, %f921;
|
|
add.rn.f32 %f924, %f918, %f923;
|
|
neg.f32 %f925, %f924;
|
|
add.rn.f32 %f926, %f918, %f925;
|
|
add.rn.f32 %f927, %f926, %f923;
|
|
mov.b32 %r274, %f924;
|
|
setp.eq.s32 %p111, %r274, 1118925336;
|
|
add.s32 %r275, %r274, -1;
|
|
mov.b32 %f928, %r275;
|
|
add.f32 %f929, %f927, 0f37000000;
|
|
selp.f32 %f214, %f929, %f927, %p111;
|
|
selp.f32 %f930, %f928, %f924, %p111;
|
|
mov.f32 %f931, 0f3FB8AA3B;
|
|
mul.rn.f32 %f932, %f930, %f931;
|
|
cvt.rzi.f32.f32 %f933, %f932;
|
|
abs.f32 %f934, %f933;
|
|
setp.gt.f32 %p112, %f934, 0f42FC0000;
|
|
mov.b32 %r276, %f933;
|
|
and.b32 %r277, %r276, -2147483648;
|
|
or.b32 %r278, %r277, 1123811328;
|
|
mov.b32 %f935, %r278;
|
|
selp.f32 %f936, %f935, %f933, %p112;
|
|
mov.f32 %f937, 0fBF317218;
|
|
fma.rn.f32 %f938, %f936, %f937, %f930;
|
|
mov.f32 %f939, 0f3102E308;
|
|
fma.rn.f32 %f940, %f936, %f939, %f938;
|
|
mul.f32 %f941, %f940, 0f3FB8AA3B;
|
|
add.f32 %f942, %f936, 0f4B40007F;
|
|
mov.b32 %r279, %f942;
|
|
shl.b32 %r280, %r279, 23;
|
|
mov.b32 %f943, %r280;
|
|
ex2.approx.ftz.f32 %f944, %f941;
|
|
mul.f32 %f215, %f944, %f943;
|
|
setp.eq.f32 %p113, %f215, 0f7F800000;
|
|
mov.f32 %f1284, 0f7F800000;
|
|
@%p113 bra $L__BB0_95;
|
|
|
|
fma.rn.f32 %f1284, %f215, %f214, %f215;
|
|
|
|
$L__BB0_95:
|
|
setp.lt.f32 %p114, %f199, 0f00000000;
|
|
and.pred %p5, %p114, %p101;
|
|
setp.eq.f32 %p116, %f199, 0f00000000;
|
|
@%p116 bra $L__BB0_99;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_99:
|
|
add.f32 %f949, %f199, %f199;
|
|
selp.f32 %f1286, %f949, 0f00000000, %p101;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_96:
|
|
mov.b32 %r281, %f1284;
|
|
xor.b32 %r282, %r281, -2147483648;
|
|
mov.b32 %f945, %r282;
|
|
selp.f32 %f1286, %f945, %f1284, %p5;
|
|
setp.geu.f32 %p117, %f199, 0f00000000;
|
|
@%p117 bra $L__BB0_100;
|
|
|
|
mov.f32 %f946, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f947, %f946;
|
|
setp.eq.f32 %p118, %f947, 0f3ED55555;
|
|
@%p118 bra $L__BB0_100;
|
|
|
|
mov.f32 %f1286, 0f7FFFFFFF;
|
|
|
|
$L__BB0_100:
|
|
mov.f32 %f1171, 0f00000000;
|
|
max.f32 %f1170, %f1171, %f783;
|
|
abs.f32 %f1169, %f1170;
|
|
add.f32 %f950, %f1169, 0f3ED55555;
|
|
mov.b32 %r283, %f950;
|
|
setp.lt.s32 %p120, %r283, 2139095040;
|
|
@%p120 bra $L__BB0_105;
|
|
|
|
mov.f32 %f1174, 0f00000000;
|
|
max.f32 %f1173, %f1174, %f783;
|
|
abs.f32 %f1172, %f1173;
|
|
setp.gtu.f32 %p121, %f1172, 0f7F800000;
|
|
@%p121 bra $L__BB0_104;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f1286, %f199, 0f3ED55555;
|
|
bra.uni $L__BB0_105;
|
|
|
|
$L__BB0_102:
|
|
mov.f32 %f1177, 0f00000000;
|
|
max.f32 %f1176, %f1177, %f783;
|
|
abs.f32 %f1175, %f1176;
|
|
setp.neu.f32 %p122, %f1175, 0f7F800000;
|
|
@%p122 bra $L__BB0_105;
|
|
|
|
selp.f32 %f1286, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_105:
|
|
abs.f32 %f224, %f200;
|
|
setp.lt.f32 %p123, %f224, 0f00800000;
|
|
mul.f32 %f952, %f224, 0f4B800000;
|
|
selp.f32 %f953, %f952, %f224, %p123;
|
|
selp.f32 %f954, 0fC3170000, 0fC2FE0000, %p123;
|
|
mov.b32 %r284, %f953;
|
|
and.b32 %r285, %r284, 8388607;
|
|
or.b32 %r286, %r285, 1065353216;
|
|
mov.b32 %f955, %r286;
|
|
shr.u32 %r287, %r284, 23;
|
|
cvt.rn.f32.u32 %f956, %r287;
|
|
add.f32 %f957, %f954, %f956;
|
|
setp.gt.f32 %p124, %f955, 0f3FB504F3;
|
|
mul.f32 %f958, %f955, 0f3F000000;
|
|
add.f32 %f959, %f957, 0f3F800000;
|
|
selp.f32 %f960, %f959, %f957, %p124;
|
|
selp.f32 %f961, %f958, %f955, %p124;
|
|
add.f32 %f962, %f961, 0fBF800000;
|
|
add.f32 %f963, %f961, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f964, %f963;
|
|
add.f32 %f965, %f962, %f962;
|
|
mul.f32 %f966, %f965, %f964;
|
|
mul.f32 %f967, %f966, %f966;
|
|
mov.f32 %f968, 0f3C4CAF63;
|
|
mov.f32 %f969, 0f3B18F0FE;
|
|
fma.rn.f32 %f970, %f969, %f967, %f968;
|
|
mov.f32 %f971, 0f3DAAAABD;
|
|
fma.rn.f32 %f972, %f970, %f967, %f971;
|
|
mul.rn.f32 %f973, %f972, %f967;
|
|
mul.rn.f32 %f974, %f973, %f966;
|
|
sub.f32 %f975, %f962, %f966;
|
|
add.f32 %f976, %f975, %f975;
|
|
neg.f32 %f977, %f966;
|
|
fma.rn.f32 %f978, %f977, %f962, %f976;
|
|
mul.rn.f32 %f979, %f964, %f978;
|
|
add.f32 %f980, %f974, %f966;
|
|
sub.f32 %f981, %f966, %f980;
|
|
add.f32 %f982, %f974, %f981;
|
|
add.f32 %f983, %f979, %f982;
|
|
add.f32 %f984, %f980, %f983;
|
|
sub.f32 %f985, %f980, %f984;
|
|
add.f32 %f986, %f983, %f985;
|
|
mov.f32 %f987, 0f3F317200;
|
|
mul.rn.f32 %f988, %f960, %f987;
|
|
mov.f32 %f989, 0f35BFBE8E;
|
|
mul.rn.f32 %f990, %f960, %f989;
|
|
add.f32 %f991, %f988, %f984;
|
|
sub.f32 %f992, %f988, %f991;
|
|
add.f32 %f993, %f984, %f992;
|
|
add.f32 %f994, %f986, %f993;
|
|
add.f32 %f995, %f990, %f994;
|
|
add.f32 %f996, %f991, %f995;
|
|
sub.f32 %f997, %f991, %f996;
|
|
add.f32 %f998, %f995, %f997;
|
|
mov.f32 %f999, 0f3ED55555;
|
|
mul.rn.f32 %f1000, %f999, %f996;
|
|
neg.f32 %f1001, %f1000;
|
|
fma.rn.f32 %f1002, %f999, %f996, %f1001;
|
|
fma.rn.f32 %f1003, %f999, %f998, %f1002;
|
|
mov.f32 %f1004, 0f00000000;
|
|
fma.rn.f32 %f1005, %f1004, %f996, %f1003;
|
|
add.rn.f32 %f1006, %f1000, %f1005;
|
|
neg.f32 %f1007, %f1006;
|
|
add.rn.f32 %f1008, %f1000, %f1007;
|
|
add.rn.f32 %f1009, %f1008, %f1005;
|
|
mov.b32 %r288, %f1006;
|
|
setp.eq.s32 %p125, %r288, 1118925336;
|
|
add.s32 %r289, %r288, -1;
|
|
mov.b32 %f1010, %r289;
|
|
add.f32 %f1011, %f1009, 0f37000000;
|
|
selp.f32 %f225, %f1011, %f1009, %p125;
|
|
selp.f32 %f1012, %f1010, %f1006, %p125;
|
|
mov.f32 %f1013, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1014, %f1012, %f1013;
|
|
cvt.rzi.f32.f32 %f1015, %f1014;
|
|
abs.f32 %f1016, %f1015;
|
|
setp.gt.f32 %p126, %f1016, 0f42FC0000;
|
|
mov.b32 %r290, %f1015;
|
|
and.b32 %r291, %r290, -2147483648;
|
|
or.b32 %r292, %r291, 1123811328;
|
|
mov.b32 %f1017, %r292;
|
|
selp.f32 %f1018, %f1017, %f1015, %p126;
|
|
mov.f32 %f1019, 0fBF317218;
|
|
fma.rn.f32 %f1020, %f1018, %f1019, %f1012;
|
|
mov.f32 %f1021, 0f3102E308;
|
|
fma.rn.f32 %f1022, %f1018, %f1021, %f1020;
|
|
mul.f32 %f1023, %f1022, 0f3FB8AA3B;
|
|
add.f32 %f1024, %f1018, 0f4B40007F;
|
|
mov.b32 %r293, %f1024;
|
|
shl.b32 %r294, %r293, 23;
|
|
mov.b32 %f1025, %r294;
|
|
ex2.approx.ftz.f32 %f1026, %f1023;
|
|
mul.f32 %f226, %f1026, %f1025;
|
|
setp.eq.f32 %p127, %f226, 0f7F800000;
|
|
mov.f32 %f1287, 0f7F800000;
|
|
@%p127 bra $L__BB0_107;
|
|
|
|
fma.rn.f32 %f1287, %f226, %f225, %f226;
|
|
|
|
$L__BB0_107:
|
|
setp.lt.f32 %p128, %f200, 0f00000000;
|
|
and.pred %p6, %p128, %p101;
|
|
setp.eq.f32 %p130, %f200, 0f00000000;
|
|
@%p130 bra $L__BB0_111;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_111:
|
|
add.f32 %f1031, %f200, %f200;
|
|
selp.f32 %f1289, %f1031, 0f00000000, %p101;
|
|
bra.uni $L__BB0_112;
|
|
|
|
$L__BB0_108:
|
|
mov.b32 %r295, %f1287;
|
|
xor.b32 %r296, %r295, -2147483648;
|
|
mov.b32 %f1027, %r296;
|
|
selp.f32 %f1289, %f1027, %f1287, %p6;
|
|
setp.geu.f32 %p131, %f200, 0f00000000;
|
|
@%p131 bra $L__BB0_112;
|
|
|
|
mov.f32 %f1028, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1029, %f1028;
|
|
setp.eq.f32 %p132, %f1029, 0f3ED55555;
|
|
@%p132 bra $L__BB0_112;
|
|
|
|
mov.f32 %f1289, 0f7FFFFFFF;
|
|
|
|
$L__BB0_112:
|
|
mov.f32 %f1180, 0f00000000;
|
|
max.f32 %f1179, %f1180, %f784;
|
|
abs.f32 %f1178, %f1179;
|
|
add.f32 %f1032, %f1178, 0f3ED55555;
|
|
mov.b32 %r297, %f1032;
|
|
setp.lt.s32 %p134, %r297, 2139095040;
|
|
@%p134 bra $L__BB0_117;
|
|
|
|
mov.f32 %f1183, 0f00000000;
|
|
max.f32 %f1182, %f1183, %f784;
|
|
abs.f32 %f1181, %f1182;
|
|
setp.gtu.f32 %p135, %f1181, 0f7F800000;
|
|
@%p135 bra $L__BB0_116;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_116:
|
|
add.f32 %f1289, %f200, 0f3ED55555;
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_114:
|
|
mov.f32 %f1186, 0f00000000;
|
|
max.f32 %f1185, %f1186, %f784;
|
|
abs.f32 %f1184, %f1185;
|
|
setp.neu.f32 %p136, %f1184, 0f7F800000;
|
|
@%p136 bra $L__BB0_117;
|
|
|
|
selp.f32 %f1289, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_117:
|
|
mov.f32 %f1195, 0f00000000;
|
|
max.f32 %f1194, %f1195, %f781;
|
|
ld.const.u64 %rd99, [params+144];
|
|
cvta.to.global.u64 %rd98, %rd99;
|
|
ld.const.u32 %r344, [params+136];
|
|
mad.lo.s32 %r343, %r344, %r5, %r4;
|
|
cvt.u64.u32 %rd97, %r343;
|
|
fma.rn.f32 %f1033, %f1283, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p137, %f1194, 0f3F800000;
|
|
mov.f32 %f1034, 0f3F800000;
|
|
selp.f32 %f1035, 0f3F7FFFFF, %f1033, %p137;
|
|
mul.f32 %f1036, %f1194, 0f414EB852;
|
|
setp.lt.f32 %p138, %f1194, 0f3B4D2E1C;
|
|
selp.f32 %f1037, %f1036, %f1035, %p138;
|
|
fma.rn.f32 %f1038, %f1286, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p139, %f199, 0f3F800000;
|
|
selp.f32 %f1039, 0f3F7FFFFF, %f1038, %p139;
|
|
mul.f32 %f1040, %f199, 0f414EB852;
|
|
setp.lt.f32 %p140, %f199, 0f3B4D2E1C;
|
|
selp.f32 %f1041, %f1040, %f1039, %p140;
|
|
fma.rn.f32 %f1042, %f1289, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p141, %f200, 0f3F800000;
|
|
selp.f32 %f1043, 0f3F7FFFFF, %f1042, %p141;
|
|
mul.f32 %f1044, %f200, 0f414EB852;
|
|
setp.lt.f32 %p142, %f200, 0f3B4D2E1C;
|
|
selp.f32 %f1045, %f1044, %f1043, %p142;
|
|
min.f32 %f1046, %f1037, %f1034;
|
|
mov.f32 %f1047, 0f00000000;
|
|
max.f32 %f1048, %f1047, %f1046;
|
|
mul.f32 %f1049, %f1048, 0f43800000;
|
|
cvt.rzi.u32.f32 %r298, %f1049;
|
|
min.u32 %r299, %r298, 255;
|
|
min.f32 %f1050, %f1041, %f1034;
|
|
max.f32 %f1051, %f1047, %f1050;
|
|
mul.f32 %f1052, %f1051, 0f43800000;
|
|
cvt.rzi.u32.f32 %r300, %f1052;
|
|
min.u32 %r301, %r300, 255;
|
|
min.f32 %f1053, %f1045, %f1034;
|
|
max.f32 %f1054, %f1047, %f1053;
|
|
mul.f32 %f1055, %f1054, 0f43800000;
|
|
cvt.rzi.u32.f32 %r302, %f1055;
|
|
min.u32 %r303, %r302, 255;
|
|
shl.b64 %rd67, %rd97, 2;
|
|
add.s64 %rd68, %rd98, %rd67;
|
|
cvt.u16.u32 %rs44, %r303;
|
|
cvt.u16.u32 %rs45, %r301;
|
|
cvt.u16.u32 %rs46, %r299;
|
|
mov.u16 %rs47, 255;
|
|
st.global.v4.u8 [%rd68], {%rs46, %rs45, %rs44, %rs47};
|
|
|
|
$L__BB0_118:
|
|
ld.const.u32 %r345, [params+104];
|
|
and.b32 %r304, %r345, 4;
|
|
setp.eq.s32 %p143, %r304, 0;
|
|
ld.const.u32 %r357, [params+108];
|
|
@%p143 bra $L__BB0_122;
|
|
|
|
setp.eq.s32 %p144, %r357, 0;
|
|
ld.const.u64 %rd69, [params+224];
|
|
cvta.to.global.u64 %rd70, %rd69;
|
|
ld.const.u32 %r305, [params+216];
|
|
mad.lo.s32 %r306, %r305, %r5, %r4;
|
|
mul.wide.u32 %rd71, %r306, 8;
|
|
add.s64 %rd18, %rd70, %rd71;
|
|
@%p144 bra $L__BB0_121;
|
|
|
|
ld.global.v4.u16 {%rs55, %rs56, %rs57, %rs58}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1056, %rs55;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1057, %rs56;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1058, %rs57;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1059, %f159, %f1056;
|
|
add.f32 %f1060, %f160, %f1057;
|
|
add.f32 %f1061, %f161, %f1058;
|
|
mov.f32 %f1062, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f1061;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f1060;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f1059;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f1062;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs51, %rs52, %rs53, %rs54};
|
|
bra.uni $L__BB0_122;
|
|
|
|
$L__BB0_121:
|
|
mov.f32 %f1066, 0f3F800000;
|
|
mov.u32 %r357, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f1066;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f161;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f160;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f159;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs59, %rs60, %rs61, %rs62};
|
|
|
|
$L__BB0_122:
|
|
add.f32 %f1067, %f147, %f144;
|
|
add.f32 %f1068, %f150, %f1067;
|
|
add.f32 %f1069, %f148, %f145;
|
|
add.f32 %f1070, %f151, %f1069;
|
|
add.f32 %f1071, %f149, %f146;
|
|
add.f32 %f1072, %f152, %f1071;
|
|
mul.f32 %f1073, %f1068, 0f3F13CD3A;
|
|
mul.f32 %f1074, %f1070, 0f3F13CD3A;
|
|
mul.f32 %f1075, %f1072, 0f3F13CD3A;
|
|
div.rn.f32 %f1076, %f153, %f1073;
|
|
div.rn.f32 %f1077, %f154, %f1074;
|
|
div.rn.f32 %f1078, %f155, %f1075;
|
|
setp.eq.f32 %p145, %f153, 0f00000000;
|
|
selp.f32 %f1079, 0f00000000, %f1076, %p145;
|
|
setp.eq.f32 %p146, %f154, 0f00000000;
|
|
selp.f32 %f1080, 0f00000000, %f1077, %p146;
|
|
setp.eq.f32 %p147, %f155, 0f00000000;
|
|
selp.f32 %f1081, 0f00000000, %f1078, %p147;
|
|
mul.f32 %f1082, %f144, %f1079;
|
|
mul.f32 %f1083, %f145, %f1080;
|
|
mul.f32 %f1084, %f146, %f1081;
|
|
mul.f32 %f1085, %f147, %f1079;
|
|
mul.f32 %f1086, %f148, %f1080;
|
|
mul.f32 %f1087, %f149, %f1081;
|
|
mul.f32 %f1088, %f150, %f1079;
|
|
mul.f32 %f1089, %f151, %f1080;
|
|
mul.f32 %f1090, %f152, %f1081;
|
|
mul.f32 %f235, %f1082, %f524;
|
|
mul.f32 %f236, %f1083, %f525;
|
|
mul.f32 %f237, %f1084, %f526;
|
|
mul.f32 %f238, %f1085, %f524;
|
|
mul.f32 %f239, %f1086, %f525;
|
|
mul.f32 %f240, %f1087, %f526;
|
|
mul.f32 %f241, %f1088, %f524;
|
|
mul.f32 %f242, %f1089, %f525;
|
|
mul.f32 %f243, %f1090, %f526;
|
|
ld.const.u64 %rd72, [params+256];
|
|
cvta.to.global.u64 %rd73, %rd72;
|
|
ld.const.u32 %r308, [params+248];
|
|
mad.lo.s32 %r309, %r308, %r5, %r4;
|
|
mul.wide.u32 %rd74, %r309, 8;
|
|
add.s64 %rd19, %rd73, %rd74;
|
|
setp.eq.s32 %p148, %r357, 0;
|
|
@%p148 bra $L__BB0_124;
|
|
|
|
ld.global.v4.u16 {%rs70, %rs71, %rs72, %rs73}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1091, %rs70;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1092, %rs71;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1093, %rs72;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1094, %f235, %f1091;
|
|
add.f32 %f1095, %f236, %f1092;
|
|
add.f32 %f1096, %f237, %f1093;
|
|
mov.f32 %f1097, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1096;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f1095;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f1094;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f1097;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs66, %rs67, %rs68, %rs69};
|
|
bra.uni $L__BB0_125;
|
|
|
|
$L__BB0_124:
|
|
mov.f32 %f1101, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f1101;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f237;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f236;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs74, %f235;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs74, %rs75, %rs76, %rs77};
|
|
|
|
$L__BB0_125:
|
|
ld.const.u64 %rd75, [params+272];
|
|
cvta.to.global.u64 %rd76, %rd75;
|
|
ld.const.u32 %r310, [params+264];
|
|
mad.lo.s32 %r311, %r310, %r5, %r4;
|
|
mul.wide.u32 %rd77, %r311, 8;
|
|
add.s64 %rd20, %rd76, %rd77;
|
|
@%p148 bra $L__BB0_127;
|
|
|
|
ld.global.v4.u16 {%rs85, %rs86, %rs87, %rs88}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1102, %rs85;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1103, %rs86;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1104, %rs87;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1105, %f238, %f1102;
|
|
add.f32 %f1106, %f239, %f1103;
|
|
add.f32 %f1107, %f240, %f1104;
|
|
mov.f32 %f1108, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1107;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f1106;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f1105;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1108;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs81, %rs82, %rs83, %rs84};
|
|
bra.uni $L__BB0_128;
|
|
|
|
$L__BB0_127:
|
|
mov.f32 %f1112, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f1112;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f240;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f239;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs89, %f238;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs89, %rs90, %rs91, %rs92};
|
|
|
|
$L__BB0_128:
|
|
ld.const.u64 %rd78, [params+288];
|
|
cvta.to.global.u64 %rd79, %rd78;
|
|
ld.const.u32 %r312, [params+280];
|
|
mad.lo.s32 %r313, %r312, %r5, %r4;
|
|
mul.wide.u32 %rd80, %r313, 8;
|
|
add.s64 %rd21, %rd79, %rd80;
|
|
@%p148 bra $L__BB0_130;
|
|
|
|
ld.global.v4.u16 {%rs100, %rs101, %rs102, %rs103}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1113, %rs100;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1114, %rs101;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1115, %rs102;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1116, %f241, %f1113;
|
|
add.f32 %f1117, %f242, %f1114;
|
|
add.f32 %f1118, %f243, %f1115;
|
|
mov.f32 %f1119, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs98, %f1118;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f1117;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f1116;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs99, %f1119;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs96, %rs97, %rs98, %rs99};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_130:
|
|
mov.f32 %f1123, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f1123;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f243;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs105, %f242;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs104, %f241;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs104, %rs105, %rs106, %rs107};
|
|
|
|
$L__BB0_146:
|
|
ret;
|
|
|
|
}
|
|
|