2904 lines
76 KiB
Plaintext
2904 lines
76 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<165>;
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.reg .b16 %rs<322>;
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.reg .f32 %f<1453>;
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.reg .b32 %r<381>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<147>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r58), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r59), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+540];
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shl.b32 %r4, %r3, 1;
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ld.const.u64 %rd37, [params+400];
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cvta.to.global.u64 %rd38, %rd37;
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ld.const.u32 %r64, [params+392];
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mad.lo.s32 %r65, %r64, %r59, %r58;
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mul.wide.u32 %rd39, %r65, 4;
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add.s64 %rd2, %rd38, %rd39;
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ld.global.v2.u8 {%rs7, %rs321}, [%rd2];
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or.b16 %rs9, %rs7, %rs321;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p7, %rs10, 0;
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@%p7 bra $L__BB0_2;
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ld.global.u8 %rs320, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs320, [%rd2+2];
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setp.eq.s16 %p8, %rs320, 0;
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mov.f32 %f1306, 0f00000000;
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mov.u16 %rs321, 0;
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mov.f32 %f1307, %f1306;
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mov.f32 %f1308, %f1306;
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@%p8 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f342, %rs7;
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div.rn.f32 %f343, %f342, 0f437F0000;
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fma.rn.f32 %f344, %f343, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs321, 255;
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cvt.rn.f32.u16 %f345, %rs13;
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div.rn.f32 %f346, %f345, 0f437F0000;
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fma.rn.f32 %f347, %f346, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f348, %rs320;
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div.rn.f32 %f349, %f348, 0f437F0000;
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fma.rn.f32 %f350, %f349, 0f40000000, 0fBF800000;
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mul.f32 %f351, %f347, %f347;
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fma.rn.f32 %f352, %f344, %f344, %f351;
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fma.rn.f32 %f353, %f350, %f350, %f352;
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sqrt.rn.f32 %f354, %f353;
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rcp.rn.f32 %f355, %f354;
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mul.f32 %f1308, %f355, %f350;
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mul.f32 %f1307, %f355, %f347;
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mul.f32 %f1306, %f344, %f355;
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$L__BB0_4:
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ld.const.v2.u32 {%r66, %r67}, [params];
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add.s32 %r5, %r66, %r58;
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add.s32 %r6, %r67, %r59;
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setp.eq.f32 %p9, %f1306, 0f00000000;
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setp.eq.f32 %p10, %f1307, 0f00000000;
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and.pred %p11, %p9, %p10;
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setp.eq.f32 %p12, %f1308, 0f00000000;
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and.pred %p13, %p12, %p11;
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@%p13 bra $L__BB0_141;
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bra.uni $L__BB0_5;
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$L__BB0_141:
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ld.const.u32 %r55, [params+104];
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and.b32 %r326, %r55, 1;
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setp.eq.b32 %p149, %r326, 1;
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mov.pred %p150, 0;
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xor.pred %p151, %p149, %p150;
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not.pred %p152, %p151;
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@%p152 bra $L__BB0_143;
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ld.const.u64 %rd109, [params+144];
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cvta.to.global.u64 %rd110, %rd109;
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ld.const.u32 %r327, [params+136];
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mad.lo.s32 %r328, %r327, %r6, %r5;
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mul.wide.u32 %rd111, %r328, 4;
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add.s64 %rd112, %rd110, %rd111;
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mov.u16 %rs169, 0;
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st.global.v4.u8 [%rd112], {%rs169, %rs169, %rs169, %rs169};
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$L__BB0_143:
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and.b32 %r329, %r55, 4;
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setp.eq.s32 %p153, %r329, 0;
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ld.const.u32 %r380, [params+108];
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@%p153 bra $L__BB0_147;
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setp.eq.s32 %p154, %r380, 0;
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ld.const.u64 %rd113, [params+224];
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cvta.to.global.u64 %rd114, %rd113;
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ld.const.u32 %r330, [params+216];
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mad.lo.s32 %r331, %r330, %r6, %r5;
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mul.wide.u32 %rd115, %r331, 8;
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add.s64 %rd26, %rd114, %rd115;
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@%p154 bra $L__BB0_146;
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ld.global.v4.u16 {%rs176, %rs177, %rs178, %rs179}, [%rd26];
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// begin inline asm
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{ cvt.f32.f16 %f1213, %rs176;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1214, %rs177;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1215, %rs178;}
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// end inline asm
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add.f32 %f1216, %f1213, 0f00000000;
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add.f32 %f1217, %f1214, 0f00000000;
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add.f32 %f1218, %f1215, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs175, %f1218;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs174, %f1217;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs173, %f1216;}
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// end inline asm
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mov.u16 %rs180, 0;
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st.global.v4.u16 [%rd26], {%rs173, %rs174, %rs175, %rs180};
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bra.uni $L__BB0_147;
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$L__BB0_5:
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ld.const.u64 %rd40, [params+432];
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cvta.to.global.u64 %rd41, %rd40;
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ld.const.u32 %r70, [params+424];
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mad.lo.s32 %r71, %r70, %r59, %r58;
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mul.wide.u32 %rd42, %r71, 12;
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add.s64 %rd43, %rd41, %rd42;
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ld.global.f32 %f386, [%rd43];
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mul.f32 %f387, %f386, 0f3456BF95;
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ld.global.f32 %f388, [%rd43+4];
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mul.f32 %f389, %f388, 0f3456BF95;
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ld.global.f32 %f390, [%rd43+8];
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mul.f32 %f391, %f390, 0f3456BF95;
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abs.f32 %f392, %f1306;
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div.rn.f32 %f393, %f387, %f392;
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abs.f32 %f394, %f1307;
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div.rn.f32 %f395, %f389, %f394;
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abs.f32 %f396, %f1308;
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div.rn.f32 %f397, %f391, %f396;
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abs.f32 %f398, %f393;
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abs.f32 %f399, %f395;
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abs.f32 %f400, %f397;
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mov.f32 %f401, 0f38D1B717;
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max.f32 %f402, %f398, %f401;
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max.f32 %f403, %f399, %f401;
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max.f32 %f404, %f400, %f401;
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fma.rn.f32 %f10, %f1306, %f402, %f386;
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fma.rn.f32 %f11, %f1307, %f403, %f388;
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fma.rn.f32 %f12, %f1308, %f404, %f390;
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setp.gt.f32 %p14, %f392, %f396;
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neg.f32 %f405, %f1307;
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selp.f32 %f406, %f405, 0f00000000, %p14;
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mov.f32 %f1375, 0f00000000;
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neg.f32 %f407, %f1308;
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selp.f32 %f408, %f1306, %f407, %p14;
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selp.f32 %f409, 0f00000000, %f1307, %p14;
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mul.f32 %f410, %f408, %f408;
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fma.rn.f32 %f411, %f406, %f406, %f410;
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fma.rn.f32 %f412, %f409, %f409, %f411;
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sqrt.rn.f32 %f413, %f412;
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rcp.rn.f32 %f414, %f413;
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mul.f32 %f13, %f406, %f414;
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mul.f32 %f14, %f408, %f414;
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mul.f32 %f15, %f409, %f414;
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ld.const.u64 %rd44, [params+128];
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cvta.to.global.u64 %rd45, %rd44;
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ld.const.u32 %r72, [params+120];
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mad.lo.s32 %r73, %r72, %r59, %r58;
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mul.wide.u32 %rd46, %r73, 4;
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add.s64 %rd3, %rd45, %rd46;
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setp.lt.s32 %p15, %r3, 1;
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mov.f32 %f1376, %f1375;
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mov.f32 %f1377, %f1375;
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mov.f32 %f1378, %f1375;
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mov.f32 %f1379, %f1375;
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mov.f32 %f1380, %f1375;
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mov.f32 %f1381, %f1375;
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mov.f32 %f1382, %f1375;
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mov.f32 %f1383, %f1375;
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mov.f32 %f1384, %f1375;
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mov.f32 %f1385, %f1375;
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mov.f32 %f1386, %f1375;
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mov.f32 %f1387, %f1375;
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mov.f32 %f1388, %f1375;
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mov.f32 %f1389, %f1375;
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mov.f32 %f1390, %f1375;
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mov.f32 %f1391, %f1375;
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mov.f32 %f1392, %f1375;
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mov.f32 %f1393, %f1375;
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mov.f32 %f1394, %f1375;
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mov.f32 %f1395, %f1375;
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mov.f32 %f1396, %f1375;
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mov.f32 %f1397, %f1375;
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mov.f32 %f1398, %f1375;
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mov.f32 %f1399, %f1375;
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mov.f32 %f1400, %f1375;
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mov.f32 %f1401, %f1375;
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mov.f32 %f1402, %f1375;
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mov.f32 %f1403, %f1375;
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mov.f32 %f1404, %f1375;
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@%p15 bra $L__BB0_36;
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ld.const.u32 %r7, [params+588];
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cvt.rn.f32.s32 %f445, %r4;
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rcp.rn.f32 %f16, %f445;
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ld.global.u32 %r370, [%rd3];
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mul.f32 %f17, %f10, 0f3456BF95;
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mul.f32 %f18, %f11, 0f3456BF95;
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mul.f32 %f19, %f12, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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mul.f32 %f446, %f1306, %f14;
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mul.f32 %f447, %f1307, %f13;
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sub.f32 %f20, %f447, %f446;
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mul.f32 %f448, %f1308, %f13;
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mul.f32 %f449, %f1306, %f15;
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sub.f32 %f21, %f449, %f448;
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mul.f32 %f450, %f1307, %f15;
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mul.f32 %f451, %f1308, %f14;
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sub.f32 %f22, %f451, %f450;
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mov.u32 %r74, 0;
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add.s64 %rd5, %rd1, 24;
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mov.u64 %rd50, __cudart_i2opi_f;
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abs.f32 %f516, %f17;
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abs.f32 %f517, %f18;
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max.f32 %f518, %f516, %f517;
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abs.f32 %f519, %f19;
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max.f32 %f520, %f518, %f519;
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mov.u32 %r367, %r74;
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$L__BB0_7:
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mov.u32 %r369, %r74;
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$L__BB0_8:
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cvt.rn.f32.s32 %f1304, %r367;
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mad.lo.s32 %r76, %r370, 1664525, 1013904223;
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and.b32 %r77, %r76, 16777215;
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cvt.rn.f32.u32 %f452, %r77;
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fma.rn.f32 %f453, %f452, 0f33800000, %f1304;
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mul.f32 %f454, %f16, %f453;
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mad.lo.s32 %r370, %r76, 1664525, 1013904223;
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and.b32 %r78, %r370, 16777215;
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cvt.rn.f32.u32 %f455, %r78;
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cvt.rn.f32.s32 %f456, %r369;
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fma.rn.f32 %f457, %f455, 0f33800000, %f456;
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mul.f32 %f458, %f16, %f457;
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fma.rn.f32 %f459, %f16, %f453, %f454;
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mov.f32 %f460, 0f3F800000;
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sub.f32 %f84, %f460, %f459;
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mul.f32 %f461, %f84, %f84;
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sub.f32 %f462, %f460, %f461;
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mov.f32 %f463, 0f00000000;
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max.f32 %f464, %f463, %f462;
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sqrt.rn.f32 %f85, %f464;
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mul.f32 %f86, %f458, 0f40C90FDB;
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mul.f32 %f465, %f86, 0f3F22F983;
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cvt.rni.s32.f32 %r374, %f465;
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cvt.rn.f32.s32 %f466, %r374;
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mov.f32 %f467, 0fBFC90FDA;
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fma.rn.f32 %f468, %f466, %f467, %f86;
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mov.f32 %f469, 0fB3A22168;
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fma.rn.f32 %f470, %f466, %f469, %f468;
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mov.f32 %f471, 0fA7C234C5;
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fma.rn.f32 %f1372, %f466, %f471, %f470;
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abs.f32 %f88, %f86;
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setp.ltu.f32 %p16, %f88, 0f47CE4780;
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mov.f32 %f1369, %f1372;
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@%p16 bra $L__BB0_16;
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setp.eq.f32 %p17, %f88, 0f7F800000;
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@%p17 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f474, 0f00000000;
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mul.rn.f32 %f1369, %f86, %f474;
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mov.u32 %r374, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r15, %f86;
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bfe.u32 %r80, %r15, 23, 8;
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mov.u64 %rd143, 0;
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mov.u32 %r371, 0;
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mov.u64 %rd144, %rd143;
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$L__BB0_11:
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.pragma "nounroll";
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mov.b32 %r353, %f86;
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shl.b32 %r352, %r353, 8;
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or.b32 %r351, %r352, -2147483648;
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shl.b64 %rd49, %rd143, 2;
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add.s64 %rd51, %rd50, %rd49;
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ld.global.nc.u32 %r82, [%rd51];
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mad.wide.u32 %rd52, %r82, %r351, %rd144;
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shr.u64 %rd144, %rd52, 32;
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add.s64 %rd53, %rd1, %rd49;
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st.local.u32 [%rd53], %rd52;
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add.s32 %r371, %r371, 1;
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cvt.s64.s32 %rd143, %r371;
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setp.ne.s32 %p18, %r371, 6;
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@%p18 bra $L__BB0_11;
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add.s32 %r358, %r80, -128;
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mov.b32 %r357, %f86;
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bfe.u32 %r356, %r357, 23, 8;
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add.s32 %r355, %r356, -128;
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shr.u32 %r354, %r355, 5;
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st.local.u32 [%rd5], %rd144;
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mov.u32 %r84, 6;
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sub.s32 %r85, %r84, %r354;
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mul.wide.s32 %rd54, %r85, 4;
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add.s64 %rd55, %rd1, %rd54;
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ld.local.u32 %r372, [%rd55];
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ld.local.u32 %r373, [%rd55+-4];
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and.b32 %r24, %r355, 31;
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setp.eq.s32 %p19, %r24, 0;
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@%p19 bra $L__BB0_14;
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mov.b32 %r366, %f86;
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bfe.u32 %r365, %r366, 23, 8;
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add.s32 %r364, %r365, -128;
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shr.u32 %r363, %r364, 5;
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mov.u32 %r362, 4;
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sub.s32 %r361, %r362, %r363;
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mov.u32 %r86, 32;
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sub.s32 %r87, %r86, %r24;
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shr.u32 %r88, %r373, %r87;
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shl.b32 %r89, %r372, %r24;
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add.s32 %r372, %r88, %r89;
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mul.wide.s32 %rd56, %r361, 4;
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add.s64 %rd57, %rd1, %rd56;
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ld.local.u32 %r90, [%rd57];
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shr.u32 %r91, %r90, %r87;
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shl.b32 %r92, %r373, %r24;
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add.s32 %r373, %r91, %r92;
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|
|
$L__BB0_14:
|
|
mov.b32 %r359, %f86;
|
|
and.b32 %r93, %r359, -2147483648;
|
|
shr.u32 %r94, %r373, 30;
|
|
shl.b32 %r95, %r372, 2;
|
|
or.b32 %r96, %r94, %r95;
|
|
shr.u32 %r97, %r96, 31;
|
|
shr.u32 %r98, %r372, 30;
|
|
add.s32 %r99, %r97, %r98;
|
|
neg.s32 %r100, %r99;
|
|
setp.eq.s32 %p20, %r93, 0;
|
|
selp.b32 %r374, %r99, %r100, %p20;
|
|
setp.ne.s32 %p21, %r97, 0;
|
|
xor.b32 %r101, %r93, -2147483648;
|
|
selp.b32 %r102, %r101, %r93, %p21;
|
|
selp.b32 %r103, -1, 0, %p21;
|
|
xor.b32 %r104, %r96, %r103;
|
|
shl.b32 %r105, %r373, 2;
|
|
xor.b32 %r106, %r105, %r103;
|
|
cvt.u64.u32 %rd58, %r104;
|
|
cvt.u64.u32 %rd59, %r106;
|
|
bfi.b64 %rd60, %rd58, %rd59, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd60;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f472, %fd2;
|
|
setp.eq.s32 %p22, %r102, 0;
|
|
neg.f32 %f473, %f472;
|
|
selp.f32 %f1369, %f472, %f473, %p22;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r31, %r374, 1;
|
|
and.b32 %r32, %r31, 1;
|
|
setp.eq.s32 %p23, %r32, 0;
|
|
selp.f32 %f92, %f1369, 0f3F800000, %p23;
|
|
mul.rn.f32 %f93, %f1369, %f1369;
|
|
mov.f32 %f1370, 0fB94D4153;
|
|
@%p23 bra $L__BB0_18;
|
|
|
|
mov.f32 %f476, 0fBAB607ED;
|
|
mov.f32 %f477, 0f37CBAC00;
|
|
fma.rn.f32 %f1370, %f477, %f93, %f476;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f478, 0f3C0885E4, 0f3D2AAABB, %p23;
|
|
fma.rn.f32 %f479, %f1370, %f93, %f478;
|
|
selp.f32 %f480, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
|
|
fma.rn.f32 %f481, %f479, %f93, %f480;
|
|
mov.f32 %f482, 0f00000000;
|
|
fma.rn.f32 %f483, %f93, %f92, %f482;
|
|
fma.rn.f32 %f1371, %f481, %f483, %f92;
|
|
and.b32 %r108, %r31, 2;
|
|
setp.eq.s32 %p25, %r108, 0;
|
|
@%p25 bra $L__BB0_20;
|
|
|
|
mov.f32 %f485, 0fBF800000;
|
|
fma.rn.f32 %f1371, %f1371, %f485, %f482;
|
|
|
|
$L__BB0_20:
|
|
mul.f32 %f1303, %f86, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r378, %f1303;
|
|
setp.ltu.f32 %p164, %f88, 0f47CE4780;
|
|
@%p164 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p27, %f88, 0f7F800000;
|
|
@%p27 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f488, 0f00000000;
|
|
mul.rn.f32 %f1372, %f86, %f488;
|
|
mov.u32 %r378, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r33, %f86;
|
|
bfe.u32 %r110, %r33, 23, 8;
|
|
add.s32 %r34, %r110, -128;
|
|
shl.b32 %r111, %r33, 8;
|
|
or.b32 %r35, %r111, -2147483648;
|
|
shr.u32 %r36, %r34, 5;
|
|
mov.u64 %rd145, 0;
|
|
mov.u32 %r375, 0;
|
|
mov.u64 %rd146, %rd145;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd63, %rd145, 2;
|
|
add.s64 %rd65, %rd50, %rd63;
|
|
ld.global.nc.u32 %r112, [%rd65];
|
|
mad.wide.u32 %rd66, %r112, %r35, %rd146;
|
|
shr.u64 %rd146, %rd66, 32;
|
|
add.s64 %rd67, %rd1, %rd63;
|
|
st.local.u32 [%rd67], %rd66;
|
|
add.s32 %r375, %r375, 1;
|
|
cvt.s64.s32 %rd145, %r375;
|
|
setp.ne.s32 %p28, %r375, 6;
|
|
@%p28 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd5], %rd146;
|
|
mov.u32 %r113, 4;
|
|
sub.s32 %r39, %r113, %r36;
|
|
mov.u32 %r114, 6;
|
|
sub.s32 %r115, %r114, %r36;
|
|
mul.wide.s32 %rd68, %r115, 4;
|
|
add.s64 %rd69, %rd1, %rd68;
|
|
ld.local.u32 %r376, [%rd69];
|
|
ld.local.u32 %r377, [%rd69+-4];
|
|
and.b32 %r42, %r34, 31;
|
|
setp.eq.s32 %p29, %r42, 0;
|
|
@%p29 bra $L__BB0_26;
|
|
|
|
mov.u32 %r116, 32;
|
|
sub.s32 %r117, %r116, %r42;
|
|
shr.u32 %r118, %r377, %r117;
|
|
shl.b32 %r119, %r376, %r42;
|
|
add.s32 %r376, %r118, %r119;
|
|
mul.wide.s32 %rd70, %r39, 4;
|
|
add.s64 %rd71, %rd1, %rd70;
|
|
ld.local.u32 %r120, [%rd71];
|
|
shr.u32 %r121, %r120, %r117;
|
|
shl.b32 %r122, %r377, %r42;
|
|
add.s32 %r377, %r121, %r122;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r123, %r33, -2147483648;
|
|
shr.u32 %r124, %r377, 30;
|
|
shl.b32 %r125, %r376, 2;
|
|
or.b32 %r126, %r124, %r125;
|
|
shr.u32 %r127, %r126, 31;
|
|
shr.u32 %r128, %r376, 30;
|
|
add.s32 %r129, %r127, %r128;
|
|
neg.s32 %r130, %r129;
|
|
setp.eq.s32 %p30, %r123, 0;
|
|
selp.b32 %r378, %r129, %r130, %p30;
|
|
setp.ne.s32 %p31, %r127, 0;
|
|
xor.b32 %r131, %r123, -2147483648;
|
|
selp.b32 %r132, %r131, %r123, %p31;
|
|
selp.b32 %r133, -1, 0, %p31;
|
|
xor.b32 %r134, %r126, %r133;
|
|
shl.b32 %r135, %r377, 2;
|
|
xor.b32 %r136, %r135, %r133;
|
|
cvt.u64.u32 %rd72, %r134;
|
|
cvt.u64.u32 %rd73, %r136;
|
|
bfi.b64 %rd74, %rd72, %rd73, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd74;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f486, %fd4;
|
|
setp.eq.s32 %p32, %r132, 0;
|
|
neg.f32 %f487, %f486;
|
|
selp.f32 %f1372, %f486, %f487, %p32;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f102, %f85, %f1371;
|
|
and.b32 %r49, %r378, 1;
|
|
setp.eq.s32 %p33, %r49, 0;
|
|
mul.rn.f32 %f104, %f1372, %f1372;
|
|
mov.f32 %f1373, 0fB94D4153;
|
|
@%p33 bra $L__BB0_30;
|
|
|
|
mov.f32 %f490, 0fBAB607ED;
|
|
mov.f32 %f491, 0f37CBAC00;
|
|
fma.rn.f32 %f1373, %f491, %f104, %f490;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f1305, %f1372, 0f3F800000, %p33;
|
|
selp.f32 %f492, 0f3C0885E4, 0f3D2AAABB, %p33;
|
|
fma.rn.f32 %f493, %f1373, %f104, %f492;
|
|
selp.f32 %f494, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
|
|
fma.rn.f32 %f495, %f493, %f104, %f494;
|
|
mov.f32 %f496, 0f00000000;
|
|
fma.rn.f32 %f497, %f104, %f1305, %f496;
|
|
fma.rn.f32 %f1374, %f495, %f497, %f1305;
|
|
and.b32 %r138, %r378, 2;
|
|
setp.eq.s32 %p35, %r138, 0;
|
|
@%p35 bra $L__BB0_32;
|
|
|
|
mov.f32 %f499, 0fBF800000;
|
|
fma.rn.f32 %f1374, %f1374, %f499, %f496;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f500, %f85, %f1374;
|
|
mul.f32 %f501, %f13, %f500;
|
|
mul.f32 %f502, %f14, %f500;
|
|
mul.f32 %f503, %f15, %f500;
|
|
fma.rn.f32 %f504, %f22, %f102, %f501;
|
|
fma.rn.f32 %f505, %f21, %f102, %f502;
|
|
fma.rn.f32 %f506, %f20, %f102, %f503;
|
|
fma.rn.f32 %f110, %f1306, %f84, %f504;
|
|
fma.rn.f32 %f111, %f1307, %f84, %f505;
|
|
fma.rn.f32 %f112, %f1308, %f84, %f506;
|
|
setp.leu.f32 %p36, %f111, 0f00000000;
|
|
setp.ne.s32 %p37, %r7, 0;
|
|
and.pred %p38, %p37, %p36;
|
|
@%p38 bra $L__BB0_34;
|
|
|
|
mov.f32 %f521, 0f38D1B717;
|
|
max.f32 %f513, %f520, %f521;
|
|
mov.f32 %f514, 0f6C4ECB8F;
|
|
mov.f32 %f515, 0f00000000;
|
|
mov.u32 %r175, 2;
|
|
mov.u32 %r176, 1;
|
|
mov.u32 %r177, 3;
|
|
mov.u32 %r180, 1065353216;
|
|
mov.u32 %r209, 0;
|
|
// begin inline asm
|
|
call(%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169,%r170),_optix_trace_typed_32,(%r209,%rd4,%f10,%f11,%f12,%f110,%f111,%f112,%f513,%f514,%f515,%r176,%r209,%r176,%r175,%r176,%r177,%r180,%r180,%r180,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209);
|
|
// end inline asm
|
|
mov.b32 %f522, %r139;
|
|
mov.b32 %f523, %r140;
|
|
mov.b32 %f524, %r141;
|
|
mul.f32 %f525, %f1307, %f111;
|
|
fma.rn.f32 %f526, %f1306, %f110, %f525;
|
|
fma.rn.f32 %f527, %f1308, %f112, %f526;
|
|
add.f32 %f1399, %f1399, %f522;
|
|
add.f32 %f1400, %f1400, %f523;
|
|
add.f32 %f1401, %f1401, %f524;
|
|
fma.rn.f32 %f1396, %f111, %f522, %f1396;
|
|
fma.rn.f32 %f1397, %f111, %f523, %f1397;
|
|
fma.rn.f32 %f1398, %f111, %f524, %f1398;
|
|
fma.rn.f32 %f1393, %f112, %f522, %f1393;
|
|
fma.rn.f32 %f1394, %f112, %f523, %f1394;
|
|
fma.rn.f32 %f1395, %f112, %f524, %f1395;
|
|
fma.rn.f32 %f1390, %f110, %f522, %f1390;
|
|
fma.rn.f32 %f1391, %f110, %f523, %f1391;
|
|
fma.rn.f32 %f1392, %f110, %f524, %f1392;
|
|
mul.f32 %f528, %f110, %f111;
|
|
fma.rn.f32 %f1387, %f528, %f522, %f1387;
|
|
fma.rn.f32 %f1388, %f528, %f523, %f1388;
|
|
fma.rn.f32 %f1389, %f528, %f524, %f1389;
|
|
mul.f32 %f529, %f111, %f112;
|
|
fma.rn.f32 %f1384, %f529, %f522, %f1384;
|
|
fma.rn.f32 %f1385, %f529, %f523, %f1385;
|
|
fma.rn.f32 %f1386, %f529, %f524, %f1386;
|
|
fma.rn.f32 %f530, %f112, %f112, 0fBEAAAAAB;
|
|
fma.rn.f32 %f1381, %f530, %f522, %f1381;
|
|
fma.rn.f32 %f1382, %f530, %f523, %f1382;
|
|
fma.rn.f32 %f1383, %f530, %f524, %f1383;
|
|
mul.f32 %f531, %f110, %f112;
|
|
fma.rn.f32 %f1378, %f531, %f522, %f1378;
|
|
fma.rn.f32 %f1379, %f531, %f523, %f1379;
|
|
fma.rn.f32 %f1380, %f531, %f524, %f1380;
|
|
mul.f32 %f532, %f111, %f111;
|
|
mul.f32 %f533, %f110, %f110;
|
|
sub.f32 %f534, %f533, %f532;
|
|
fma.rn.f32 %f1375, %f534, %f522, %f1375;
|
|
fma.rn.f32 %f1376, %f534, %f523, %f1376;
|
|
fma.rn.f32 %f1377, %f534, %f524, %f1377;
|
|
cvt.sat.f32.f32 %f535, %f527;
|
|
fma.rn.f32 %f1402, %f535, %f522, %f1402;
|
|
fma.rn.f32 %f1403, %f535, %f523, %f1403;
|
|
fma.rn.f32 %f1404, %f535, %f524, %f1404;
|
|
|
|
$L__BB0_34:
|
|
add.s32 %r369, %r369, 1;
|
|
setp.lt.s32 %p39, %r369, %r4;
|
|
@%p39 bra $L__BB0_8;
|
|
|
|
add.s32 %r367, %r367, 1;
|
|
setp.lt.s32 %p40, %r367, %r4;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_36:
|
|
mul.lo.s32 %r210, %r4, %r4;
|
|
cvt.rn.f32.s32 %f536, %r210;
|
|
rcp.rn.f32 %f537, %f536;
|
|
mul.f32 %f538, %f537, %f1402;
|
|
mul.f32 %f539, %f537, %f1403;
|
|
mul.f32 %f540, %f537, %f1404;
|
|
mul.f32 %f203, %f537, %f1399;
|
|
mul.f32 %f204, %f537, %f1400;
|
|
mul.f32 %f205, %f537, %f1401;
|
|
mul.f32 %f206, %f537, %f1396;
|
|
mul.f32 %f207, %f537, %f1397;
|
|
mul.f32 %f208, %f537, %f1398;
|
|
mul.f32 %f209, %f537, %f1393;
|
|
mul.f32 %f210, %f537, %f1394;
|
|
mul.f32 %f211, %f537, %f1395;
|
|
mul.f32 %f212, %f537, %f1390;
|
|
mul.f32 %f213, %f537, %f1391;
|
|
mul.f32 %f214, %f537, %f1392;
|
|
mul.f32 %f215, %f537, %f1387;
|
|
mul.f32 %f216, %f537, %f1388;
|
|
mul.f32 %f217, %f537, %f1389;
|
|
mul.f32 %f218, %f537, %f1384;
|
|
mul.f32 %f219, %f537, %f1385;
|
|
mul.f32 %f220, %f537, %f1386;
|
|
mul.f32 %f221, %f537, %f1381;
|
|
mul.f32 %f222, %f537, %f1382;
|
|
mul.f32 %f223, %f537, %f1383;
|
|
mul.f32 %f224, %f537, %f1378;
|
|
mul.f32 %f225, %f537, %f1379;
|
|
mul.f32 %f226, %f537, %f1380;
|
|
mul.f32 %f227, %f537, %f1375;
|
|
mul.f32 %f228, %f537, %f1376;
|
|
mul.f32 %f229, %f537, %f1377;
|
|
fma.rn.f32 %f541, %f537, %f1402, %f538;
|
|
fma.rn.f32 %f542, %f537, %f1403, %f539;
|
|
fma.rn.f32 %f543, %f537, %f1404, %f540;
|
|
ld.const.v4.f32 {%f544, %f545, %f546, %f547}, [params+576];
|
|
mul.f32 %f233, %f541, %f544;
|
|
mul.f32 %f234, %f542, %f545;
|
|
mul.f32 %f235, %f543, %f546;
|
|
ld.const.u32 %r52, [params+104];
|
|
and.b32 %r211, %r52, 1;
|
|
setp.eq.b32 %p41, %r211, 1;
|
|
mov.pred %p42, 0;
|
|
xor.pred %p43, %p41, %p42;
|
|
not.pred %p44, %p43;
|
|
@%p44 bra $L__BB0_110;
|
|
|
|
mov.f32 %f549, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f550, %f549;
|
|
add.f32 %f551, %f550, %f550;
|
|
mov.f32 %f552, 0f3EE66666;
|
|
sub.f32 %f553, %f552, %f551;
|
|
abs.f32 %f236, %f553;
|
|
abs.f32 %f237, %f233;
|
|
setp.lt.f32 %p45, %f237, 0f00800000;
|
|
mul.f32 %f554, %f237, 0f4B800000;
|
|
selp.f32 %f555, %f554, %f237, %p45;
|
|
selp.f32 %f556, 0fC3170000, 0fC2FE0000, %p45;
|
|
mov.b32 %r212, %f555;
|
|
and.b32 %r213, %r212, 8388607;
|
|
or.b32 %r214, %r213, 1065353216;
|
|
mov.b32 %f557, %r214;
|
|
shr.u32 %r215, %r212, 23;
|
|
cvt.rn.f32.u32 %f558, %r215;
|
|
add.f32 %f559, %f556, %f558;
|
|
setp.gt.f32 %p46, %f557, 0f3FB504F3;
|
|
mul.f32 %f560, %f557, 0f3F000000;
|
|
add.f32 %f561, %f559, 0f3F800000;
|
|
selp.f32 %f562, %f561, %f559, %p46;
|
|
selp.f32 %f563, %f560, %f557, %p46;
|
|
add.f32 %f564, %f563, 0fBF800000;
|
|
add.f32 %f565, %f563, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f566, %f565;
|
|
add.f32 %f567, %f564, %f564;
|
|
mul.f32 %f568, %f567, %f566;
|
|
mul.f32 %f569, %f568, %f568;
|
|
mov.f32 %f570, 0f3C4CAF63;
|
|
mov.f32 %f571, 0f3B18F0FE;
|
|
fma.rn.f32 %f572, %f571, %f569, %f570;
|
|
mov.f32 %f573, 0f3DAAAABD;
|
|
fma.rn.f32 %f574, %f572, %f569, %f573;
|
|
mul.rn.f32 %f575, %f574, %f569;
|
|
mul.rn.f32 %f576, %f575, %f568;
|
|
sub.f32 %f577, %f564, %f568;
|
|
add.f32 %f578, %f577, %f577;
|
|
neg.f32 %f579, %f568;
|
|
fma.rn.f32 %f580, %f579, %f564, %f578;
|
|
mul.rn.f32 %f581, %f566, %f580;
|
|
add.f32 %f582, %f576, %f568;
|
|
sub.f32 %f583, %f568, %f582;
|
|
add.f32 %f584, %f576, %f583;
|
|
add.f32 %f585, %f581, %f584;
|
|
add.f32 %f586, %f582, %f585;
|
|
sub.f32 %f587, %f582, %f586;
|
|
add.f32 %f588, %f585, %f587;
|
|
mov.f32 %f589, 0f3F317200;
|
|
mul.rn.f32 %f590, %f562, %f589;
|
|
mov.f32 %f591, 0f35BFBE8E;
|
|
mul.rn.f32 %f592, %f562, %f591;
|
|
add.f32 %f593, %f590, %f586;
|
|
sub.f32 %f594, %f590, %f593;
|
|
add.f32 %f595, %f586, %f594;
|
|
add.f32 %f596, %f588, %f595;
|
|
add.f32 %f597, %f592, %f596;
|
|
add.f32 %f598, %f593, %f597;
|
|
sub.f32 %f599, %f593, %f598;
|
|
add.f32 %f600, %f597, %f599;
|
|
mul.rn.f32 %f601, %f552, %f598;
|
|
neg.f32 %f602, %f601;
|
|
fma.rn.f32 %f603, %f552, %f598, %f602;
|
|
fma.rn.f32 %f604, %f552, %f600, %f603;
|
|
mov.f32 %f605, 0f00000000;
|
|
fma.rn.f32 %f606, %f605, %f598, %f604;
|
|
add.rn.f32 %f607, %f601, %f606;
|
|
neg.f32 %f608, %f607;
|
|
add.rn.f32 %f609, %f601, %f608;
|
|
add.rn.f32 %f610, %f609, %f606;
|
|
mov.b32 %r216, %f607;
|
|
setp.eq.s32 %p47, %r216, 1118925336;
|
|
add.s32 %r217, %r216, -1;
|
|
mov.b32 %f611, %r217;
|
|
add.f32 %f612, %f610, 0f37000000;
|
|
selp.f32 %f238, %f612, %f610, %p47;
|
|
selp.f32 %f613, %f611, %f607, %p47;
|
|
mov.f32 %f614, 0f3FB8AA3B;
|
|
mul.rn.f32 %f615, %f613, %f614;
|
|
cvt.rzi.f32.f32 %f616, %f615;
|
|
abs.f32 %f617, %f616;
|
|
setp.gt.f32 %p48, %f617, 0f42FC0000;
|
|
mov.b32 %r218, %f616;
|
|
and.b32 %r219, %r218, -2147483648;
|
|
or.b32 %r220, %r219, 1123811328;
|
|
mov.b32 %f618, %r220;
|
|
selp.f32 %f619, %f618, %f616, %p48;
|
|
mov.f32 %f620, 0fBF317218;
|
|
fma.rn.f32 %f621, %f619, %f620, %f613;
|
|
mov.f32 %f622, 0f3102E308;
|
|
fma.rn.f32 %f623, %f619, %f622, %f621;
|
|
mul.f32 %f624, %f623, 0f3FB8AA3B;
|
|
add.f32 %f625, %f619, 0f4B40007F;
|
|
mov.b32 %r221, %f625;
|
|
shl.b32 %r222, %r221, 23;
|
|
mov.b32 %f626, %r222;
|
|
ex2.approx.ftz.f32 %f627, %f624;
|
|
mul.f32 %f239, %f627, %f626;
|
|
setp.eq.f32 %p49, %f239, 0f7F800000;
|
|
mov.f32 %f1435, 0f7F800000;
|
|
@%p49 bra $L__BB0_39;
|
|
|
|
fma.rn.f32 %f1435, %f239, %f238, %f239;
|
|
|
|
$L__BB0_39:
|
|
setp.lt.f32 %p50, %f233, 0f00000000;
|
|
setp.eq.f32 %p51, %f236, 0f3F800000;
|
|
and.pred %p1, %p50, %p51;
|
|
setp.eq.f32 %p52, %f233, 0f00000000;
|
|
@%p52 bra $L__BB0_43;
|
|
bra.uni $L__BB0_40;
|
|
|
|
$L__BB0_43:
|
|
add.f32 %f632, %f233, %f233;
|
|
selp.f32 %f1437, %f632, 0f00000000, %p51;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_146:
|
|
mov.f32 %f1221, 0f00000000;
|
|
mov.u32 %r380, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs183, %f1221;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs182, %f1221;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs181, %f1221;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs184, 0;
|
|
st.global.v4.u16 [%rd26], {%rs181, %rs182, %rs183, %rs184};
|
|
|
|
$L__BB0_147:
|
|
ld.const.u64 %rd116, [params+256];
|
|
cvta.to.global.u64 %rd117, %rd116;
|
|
ld.const.u32 %r333, [params+248];
|
|
mad.lo.s32 %r334, %r333, %r6, %r5;
|
|
mul.wide.u32 %rd118, %r334, 8;
|
|
add.s64 %rd27, %rd117, %rd118;
|
|
setp.eq.s32 %p155, %r380, 0;
|
|
@%p155 bra $L__BB0_149;
|
|
|
|
ld.global.v4.u16 {%rs191, %rs192, %rs193, %rs194}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1222, %rs191;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1223, %rs192;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1224, %rs193;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1225, %f1222, 0f00000000;
|
|
add.f32 %f1226, %f1223, 0f00000000;
|
|
add.f32 %f1227, %f1224, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs190, %f1227;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs189, %f1226;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs188, %f1225;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs195, 0;
|
|
st.global.v4.u16 [%rd27], {%rs188, %rs189, %rs190, %rs195};
|
|
bra.uni $L__BB0_150;
|
|
|
|
$L__BB0_149:
|
|
mov.f32 %f1230, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs198, %f1230;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs197, %f1230;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs196, %f1230;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs199, 0;
|
|
st.global.v4.u16 [%rd27], {%rs196, %rs197, %rs198, %rs199};
|
|
|
|
$L__BB0_150:
|
|
ld.const.u64 %rd119, [params+272];
|
|
cvta.to.global.u64 %rd120, %rd119;
|
|
ld.const.u32 %r335, [params+264];
|
|
mad.lo.s32 %r336, %r335, %r6, %r5;
|
|
mul.wide.u32 %rd121, %r336, 8;
|
|
add.s64 %rd28, %rd120, %rd121;
|
|
@%p155 bra $L__BB0_152;
|
|
|
|
ld.global.v4.u16 {%rs206, %rs207, %rs208, %rs209}, [%rd28];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1231, %rs206;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1232, %rs207;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1233, %rs208;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1234, %f1231, 0f00000000;
|
|
add.f32 %f1235, %f1232, 0f00000000;
|
|
add.f32 %f1236, %f1233, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs205, %f1236;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs204, %f1235;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs203, %f1234;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs210, 0;
|
|
st.global.v4.u16 [%rd28], {%rs203, %rs204, %rs205, %rs210};
|
|
bra.uni $L__BB0_153;
|
|
|
|
$L__BB0_152:
|
|
mov.f32 %f1239, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs213, %f1239;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs212, %f1239;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs211, %f1239;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs214, 0;
|
|
st.global.v4.u16 [%rd28], {%rs211, %rs212, %rs213, %rs214};
|
|
|
|
$L__BB0_153:
|
|
ld.const.u64 %rd122, [params+288];
|
|
cvta.to.global.u64 %rd123, %rd122;
|
|
ld.const.u32 %r337, [params+280];
|
|
mad.lo.s32 %r338, %r337, %r6, %r5;
|
|
mul.wide.u32 %rd124, %r338, 8;
|
|
add.s64 %rd29, %rd123, %rd124;
|
|
@%p155 bra $L__BB0_155;
|
|
|
|
ld.global.v4.u16 {%rs221, %rs222, %rs223, %rs224}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1240, %rs221;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1241, %rs222;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1242, %rs223;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1243, %f1240, 0f00000000;
|
|
add.f32 %f1244, %f1241, 0f00000000;
|
|
add.f32 %f1245, %f1242, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs220, %f1245;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs219, %f1244;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs218, %f1243;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs225, 0;
|
|
st.global.v4.u16 [%rd29], {%rs218, %rs219, %rs220, %rs225};
|
|
bra.uni $L__BB0_156;
|
|
|
|
$L__BB0_155:
|
|
mov.f32 %f1248, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs228, %f1248;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs227, %f1248;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs226, %f1248;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs229, 0;
|
|
st.global.v4.u16 [%rd29], {%rs226, %rs227, %rs228, %rs229};
|
|
|
|
$L__BB0_156:
|
|
ld.const.u64 %rd125, [params+304];
|
|
cvta.to.global.u64 %rd126, %rd125;
|
|
ld.const.u32 %r339, [params+296];
|
|
mad.lo.s32 %r340, %r339, %r6, %r5;
|
|
mul.wide.u32 %rd127, %r340, 8;
|
|
add.s64 %rd30, %rd126, %rd127;
|
|
@%p155 bra $L__BB0_158;
|
|
|
|
ld.global.v4.u16 {%rs236, %rs237, %rs238, %rs239}, [%rd30];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1249, %rs236;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1250, %rs237;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1251, %rs238;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1252, %f1249, 0f00000000;
|
|
add.f32 %f1253, %f1250, 0f00000000;
|
|
add.f32 %f1254, %f1251, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs235, %f1254;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs234, %f1253;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs233, %f1252;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs240, 0;
|
|
st.global.v4.u16 [%rd30], {%rs233, %rs234, %rs235, %rs240};
|
|
bra.uni $L__BB0_159;
|
|
|
|
$L__BB0_158:
|
|
mov.f32 %f1257, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs243, %f1257;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs242, %f1257;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs241, %f1257;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs244, 0;
|
|
st.global.v4.u16 [%rd30], {%rs241, %rs242, %rs243, %rs244};
|
|
|
|
$L__BB0_159:
|
|
ld.const.u64 %rd128, [params+320];
|
|
cvta.to.global.u64 %rd129, %rd128;
|
|
ld.const.u32 %r341, [params+312];
|
|
mad.lo.s32 %r342, %r341, %r6, %r5;
|
|
mul.wide.u32 %rd130, %r342, 8;
|
|
add.s64 %rd31, %rd129, %rd130;
|
|
@%p155 bra $L__BB0_161;
|
|
|
|
ld.global.v4.u16 {%rs251, %rs252, %rs253, %rs254}, [%rd31];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1258, %rs251;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1259, %rs252;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1260, %rs253;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1261, %f1258, 0f00000000;
|
|
add.f32 %f1262, %f1259, 0f00000000;
|
|
add.f32 %f1263, %f1260, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs250, %f1263;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs249, %f1262;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs248, %f1261;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs255, 0;
|
|
st.global.v4.u16 [%rd31], {%rs248, %rs249, %rs250, %rs255};
|
|
bra.uni $L__BB0_162;
|
|
|
|
$L__BB0_161:
|
|
mov.f32 %f1266, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs258, %f1266;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs257, %f1266;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs256, %f1266;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs259, 0;
|
|
st.global.v4.u16 [%rd31], {%rs256, %rs257, %rs258, %rs259};
|
|
|
|
$L__BB0_162:
|
|
ld.const.u64 %rd131, [params+336];
|
|
cvta.to.global.u64 %rd132, %rd131;
|
|
ld.const.u32 %r343, [params+328];
|
|
mad.lo.s32 %r344, %r343, %r6, %r5;
|
|
mul.wide.u32 %rd133, %r344, 8;
|
|
add.s64 %rd32, %rd132, %rd133;
|
|
@%p155 bra $L__BB0_164;
|
|
|
|
ld.global.v4.u16 {%rs266, %rs267, %rs268, %rs269}, [%rd32];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1267, %rs266;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1268, %rs267;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1269, %rs268;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1270, %f1267, 0f00000000;
|
|
add.f32 %f1271, %f1268, 0f00000000;
|
|
add.f32 %f1272, %f1269, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs265, %f1272;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs264, %f1271;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs263, %f1270;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs270, 0;
|
|
st.global.v4.u16 [%rd32], {%rs263, %rs264, %rs265, %rs270};
|
|
bra.uni $L__BB0_165;
|
|
|
|
$L__BB0_164:
|
|
mov.f32 %f1275, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs273, %f1275;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs272, %f1275;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs271, %f1275;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs274, 0;
|
|
st.global.v4.u16 [%rd32], {%rs271, %rs272, %rs273, %rs274};
|
|
|
|
$L__BB0_165:
|
|
ld.const.u64 %rd134, [params+352];
|
|
cvta.to.global.u64 %rd135, %rd134;
|
|
ld.const.u32 %r345, [params+344];
|
|
mad.lo.s32 %r346, %r345, %r6, %r5;
|
|
mul.wide.u32 %rd136, %r346, 8;
|
|
add.s64 %rd33, %rd135, %rd136;
|
|
@%p155 bra $L__BB0_167;
|
|
|
|
ld.global.v4.u16 {%rs281, %rs282, %rs283, %rs284}, [%rd33];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1276, %rs281;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1277, %rs282;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1278, %rs283;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1279, %f1276, 0f00000000;
|
|
add.f32 %f1280, %f1277, 0f00000000;
|
|
add.f32 %f1281, %f1278, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs280, %f1281;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs279, %f1280;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs278, %f1279;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs285, 0;
|
|
st.global.v4.u16 [%rd33], {%rs278, %rs279, %rs280, %rs285};
|
|
bra.uni $L__BB0_168;
|
|
|
|
$L__BB0_167:
|
|
mov.f32 %f1284, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs288, %f1284;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs287, %f1284;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs286, %f1284;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs289, 0;
|
|
st.global.v4.u16 [%rd33], {%rs286, %rs287, %rs288, %rs289};
|
|
|
|
$L__BB0_168:
|
|
ld.const.u64 %rd137, [params+368];
|
|
cvta.to.global.u64 %rd138, %rd137;
|
|
ld.const.u32 %r347, [params+360];
|
|
mad.lo.s32 %r348, %r347, %r6, %r5;
|
|
mul.wide.u32 %rd139, %r348, 8;
|
|
add.s64 %rd34, %rd138, %rd139;
|
|
@%p155 bra $L__BB0_170;
|
|
|
|
ld.global.v4.u16 {%rs296, %rs297, %rs298, %rs299}, [%rd34];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1285, %rs296;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1286, %rs297;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1287, %rs298;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1288, %f1285, 0f00000000;
|
|
add.f32 %f1289, %f1286, 0f00000000;
|
|
add.f32 %f1290, %f1287, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs295, %f1290;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs294, %f1289;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs293, %f1288;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs300, 0;
|
|
st.global.v4.u16 [%rd34], {%rs293, %rs294, %rs295, %rs300};
|
|
bra.uni $L__BB0_171;
|
|
|
|
$L__BB0_170:
|
|
mov.f32 %f1293, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs303, %f1293;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs302, %f1293;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs301, %f1293;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs304, 0;
|
|
st.global.v4.u16 [%rd34], {%rs301, %rs302, %rs303, %rs304};
|
|
|
|
$L__BB0_171:
|
|
ld.const.u64 %rd140, [params+384];
|
|
cvta.to.global.u64 %rd141, %rd140;
|
|
ld.const.u32 %r349, [params+376];
|
|
mad.lo.s32 %r350, %r349, %r6, %r5;
|
|
mul.wide.u32 %rd142, %r350, 8;
|
|
add.s64 %rd35, %rd141, %rd142;
|
|
@%p155 bra $L__BB0_173;
|
|
|
|
ld.global.v4.u16 {%rs311, %rs312, %rs313, %rs314}, [%rd35];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1294, %rs311;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1295, %rs312;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1296, %rs313;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1297, %f1294, 0f00000000;
|
|
add.f32 %f1298, %f1295, 0f00000000;
|
|
add.f32 %f1299, %f1296, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs310, %f1299;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs309, %f1298;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs308, %f1297;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs315, 0;
|
|
st.global.v4.u16 [%rd35], {%rs308, %rs309, %rs310, %rs315};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_173:
|
|
mov.f32 %f1302, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs318, %f1302;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs317, %f1302;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs316, %f1302;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs319, 0;
|
|
st.global.v4.u16 [%rd35], {%rs316, %rs317, %rs318, %rs319};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_40:
|
|
mov.b32 %r223, %f1435;
|
|
xor.b32 %r224, %r223, -2147483648;
|
|
mov.b32 %f628, %r224;
|
|
selp.f32 %f1437, %f628, %f1435, %p1;
|
|
setp.geu.f32 %p53, %f233, 0f00000000;
|
|
@%p53 bra $L__BB0_44;
|
|
|
|
mov.f32 %f629, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f630, %f629;
|
|
setp.eq.f32 %p54, %f630, 0f3EE66666;
|
|
@%p54 bra $L__BB0_44;
|
|
|
|
mov.f32 %f1437, 0f7FFFFFFF;
|
|
|
|
$L__BB0_44:
|
|
add.f32 %f633, %f237, 0f3EE66666;
|
|
mov.b32 %r225, %f633;
|
|
setp.lt.s32 %p56, %r225, 2139095040;
|
|
@%p56 bra $L__BB0_49;
|
|
|
|
setp.gtu.f32 %p57, %f237, 0f7F800000;
|
|
@%p57 bra $L__BB0_48;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f1437, %f233, 0f3EE66666;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_46:
|
|
setp.neu.f32 %p58, %f237, 0f7F800000;
|
|
@%p58 bra $L__BB0_49;
|
|
|
|
selp.f32 %f1437, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_49:
|
|
setp.eq.f32 %p59, %f233, 0f3F800000;
|
|
selp.f32 %f248, 0f3F800000, %f1437, %p59;
|
|
abs.f32 %f249, %f234;
|
|
setp.lt.f32 %p60, %f249, 0f00800000;
|
|
mul.f32 %f635, %f249, 0f4B800000;
|
|
selp.f32 %f636, %f635, %f249, %p60;
|
|
selp.f32 %f637, 0fC3170000, 0fC2FE0000, %p60;
|
|
mov.b32 %r226, %f636;
|
|
and.b32 %r227, %r226, 8388607;
|
|
or.b32 %r228, %r227, 1065353216;
|
|
mov.b32 %f638, %r228;
|
|
shr.u32 %r229, %r226, 23;
|
|
cvt.rn.f32.u32 %f639, %r229;
|
|
add.f32 %f640, %f637, %f639;
|
|
setp.gt.f32 %p61, %f638, 0f3FB504F3;
|
|
mul.f32 %f641, %f638, 0f3F000000;
|
|
add.f32 %f642, %f640, 0f3F800000;
|
|
selp.f32 %f643, %f642, %f640, %p61;
|
|
selp.f32 %f644, %f641, %f638, %p61;
|
|
add.f32 %f645, %f644, 0fBF800000;
|
|
add.f32 %f646, %f644, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f647, %f646;
|
|
add.f32 %f648, %f645, %f645;
|
|
mul.f32 %f649, %f648, %f647;
|
|
mul.f32 %f650, %f649, %f649;
|
|
mov.f32 %f651, 0f3C4CAF63;
|
|
mov.f32 %f652, 0f3B18F0FE;
|
|
fma.rn.f32 %f653, %f652, %f650, %f651;
|
|
mov.f32 %f654, 0f3DAAAABD;
|
|
fma.rn.f32 %f655, %f653, %f650, %f654;
|
|
mul.rn.f32 %f656, %f655, %f650;
|
|
mul.rn.f32 %f657, %f656, %f649;
|
|
sub.f32 %f658, %f645, %f649;
|
|
add.f32 %f659, %f658, %f658;
|
|
neg.f32 %f660, %f649;
|
|
fma.rn.f32 %f661, %f660, %f645, %f659;
|
|
mul.rn.f32 %f662, %f647, %f661;
|
|
add.f32 %f663, %f657, %f649;
|
|
sub.f32 %f664, %f649, %f663;
|
|
add.f32 %f665, %f657, %f664;
|
|
add.f32 %f666, %f662, %f665;
|
|
add.f32 %f667, %f663, %f666;
|
|
sub.f32 %f668, %f663, %f667;
|
|
add.f32 %f669, %f666, %f668;
|
|
mov.f32 %f670, 0f3F317200;
|
|
mul.rn.f32 %f671, %f643, %f670;
|
|
mov.f32 %f672, 0f35BFBE8E;
|
|
mul.rn.f32 %f673, %f643, %f672;
|
|
add.f32 %f674, %f671, %f667;
|
|
sub.f32 %f675, %f671, %f674;
|
|
add.f32 %f676, %f667, %f675;
|
|
add.f32 %f677, %f669, %f676;
|
|
add.f32 %f678, %f673, %f677;
|
|
add.f32 %f679, %f674, %f678;
|
|
sub.f32 %f680, %f674, %f679;
|
|
add.f32 %f681, %f678, %f680;
|
|
mov.f32 %f682, 0f3EE66666;
|
|
mul.rn.f32 %f683, %f682, %f679;
|
|
neg.f32 %f684, %f683;
|
|
fma.rn.f32 %f685, %f682, %f679, %f684;
|
|
fma.rn.f32 %f686, %f682, %f681, %f685;
|
|
mov.f32 %f687, 0f00000000;
|
|
fma.rn.f32 %f688, %f687, %f679, %f686;
|
|
add.rn.f32 %f689, %f683, %f688;
|
|
neg.f32 %f690, %f689;
|
|
add.rn.f32 %f691, %f683, %f690;
|
|
add.rn.f32 %f692, %f691, %f688;
|
|
mov.b32 %r230, %f689;
|
|
setp.eq.s32 %p62, %r230, 1118925336;
|
|
add.s32 %r231, %r230, -1;
|
|
mov.b32 %f693, %r231;
|
|
add.f32 %f694, %f692, 0f37000000;
|
|
selp.f32 %f250, %f694, %f692, %p62;
|
|
selp.f32 %f695, %f693, %f689, %p62;
|
|
mov.f32 %f696, 0f3FB8AA3B;
|
|
mul.rn.f32 %f697, %f695, %f696;
|
|
cvt.rzi.f32.f32 %f698, %f697;
|
|
abs.f32 %f699, %f698;
|
|
setp.gt.f32 %p63, %f699, 0f42FC0000;
|
|
mov.b32 %r232, %f698;
|
|
and.b32 %r233, %r232, -2147483648;
|
|
or.b32 %r234, %r233, 1123811328;
|
|
mov.b32 %f700, %r234;
|
|
selp.f32 %f701, %f700, %f698, %p63;
|
|
mov.f32 %f702, 0fBF317218;
|
|
fma.rn.f32 %f703, %f701, %f702, %f695;
|
|
mov.f32 %f704, 0f3102E308;
|
|
fma.rn.f32 %f705, %f701, %f704, %f703;
|
|
mul.f32 %f706, %f705, 0f3FB8AA3B;
|
|
add.f32 %f707, %f701, 0f4B40007F;
|
|
mov.b32 %r235, %f707;
|
|
shl.b32 %r236, %r235, 23;
|
|
mov.b32 %f708, %r236;
|
|
ex2.approx.ftz.f32 %f709, %f706;
|
|
mul.f32 %f251, %f709, %f708;
|
|
setp.eq.f32 %p64, %f251, 0f7F800000;
|
|
mov.f32 %f1438, 0f7F800000;
|
|
@%p64 bra $L__BB0_51;
|
|
|
|
fma.rn.f32 %f1438, %f251, %f250, %f251;
|
|
|
|
$L__BB0_51:
|
|
setp.lt.f32 %p65, %f234, 0f00000000;
|
|
and.pred %p2, %p65, %p51;
|
|
setp.eq.f32 %p67, %f234, 0f00000000;
|
|
@%p67 bra $L__BB0_55;
|
|
bra.uni $L__BB0_52;
|
|
|
|
$L__BB0_55:
|
|
add.f32 %f714, %f234, %f234;
|
|
selp.f32 %f1440, %f714, 0f00000000, %p51;
|
|
bra.uni $L__BB0_56;
|
|
|
|
$L__BB0_52:
|
|
mov.b32 %r237, %f1438;
|
|
xor.b32 %r238, %r237, -2147483648;
|
|
mov.b32 %f710, %r238;
|
|
selp.f32 %f1440, %f710, %f1438, %p2;
|
|
setp.geu.f32 %p68, %f234, 0f00000000;
|
|
@%p68 bra $L__BB0_56;
|
|
|
|
mov.f32 %f711, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f712, %f711;
|
|
setp.eq.f32 %p69, %f712, 0f3EE66666;
|
|
@%p69 bra $L__BB0_56;
|
|
|
|
mov.f32 %f1440, 0f7FFFFFFF;
|
|
|
|
$L__BB0_56:
|
|
add.f32 %f715, %f249, 0f3EE66666;
|
|
mov.b32 %r239, %f715;
|
|
setp.lt.s32 %p71, %r239, 2139095040;
|
|
@%p71 bra $L__BB0_61;
|
|
|
|
setp.gtu.f32 %p72, %f249, 0f7F800000;
|
|
@%p72 bra $L__BB0_60;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_60:
|
|
add.f32 %f1440, %f234, 0f3EE66666;
|
|
bra.uni $L__BB0_61;
|
|
|
|
$L__BB0_58:
|
|
setp.neu.f32 %p73, %f249, 0f7F800000;
|
|
@%p73 bra $L__BB0_61;
|
|
|
|
selp.f32 %f1440, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_61:
|
|
setp.eq.f32 %p74, %f234, 0f3F800000;
|
|
selp.f32 %f260, 0f3F800000, %f1440, %p74;
|
|
abs.f32 %f261, %f235;
|
|
setp.lt.f32 %p75, %f261, 0f00800000;
|
|
mul.f32 %f717, %f261, 0f4B800000;
|
|
selp.f32 %f718, %f717, %f261, %p75;
|
|
selp.f32 %f719, 0fC3170000, 0fC2FE0000, %p75;
|
|
mov.b32 %r240, %f718;
|
|
and.b32 %r241, %r240, 8388607;
|
|
or.b32 %r242, %r241, 1065353216;
|
|
mov.b32 %f720, %r242;
|
|
shr.u32 %r243, %r240, 23;
|
|
cvt.rn.f32.u32 %f721, %r243;
|
|
add.f32 %f722, %f719, %f721;
|
|
setp.gt.f32 %p76, %f720, 0f3FB504F3;
|
|
mul.f32 %f723, %f720, 0f3F000000;
|
|
add.f32 %f724, %f722, 0f3F800000;
|
|
selp.f32 %f725, %f724, %f722, %p76;
|
|
selp.f32 %f726, %f723, %f720, %p76;
|
|
add.f32 %f727, %f726, 0fBF800000;
|
|
add.f32 %f728, %f726, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f729, %f728;
|
|
add.f32 %f730, %f727, %f727;
|
|
mul.f32 %f731, %f730, %f729;
|
|
mul.f32 %f732, %f731, %f731;
|
|
mov.f32 %f733, 0f3C4CAF63;
|
|
mov.f32 %f734, 0f3B18F0FE;
|
|
fma.rn.f32 %f735, %f734, %f732, %f733;
|
|
mov.f32 %f736, 0f3DAAAABD;
|
|
fma.rn.f32 %f737, %f735, %f732, %f736;
|
|
mul.rn.f32 %f738, %f737, %f732;
|
|
mul.rn.f32 %f739, %f738, %f731;
|
|
sub.f32 %f740, %f727, %f731;
|
|
add.f32 %f741, %f740, %f740;
|
|
neg.f32 %f742, %f731;
|
|
fma.rn.f32 %f743, %f742, %f727, %f741;
|
|
mul.rn.f32 %f744, %f729, %f743;
|
|
add.f32 %f745, %f739, %f731;
|
|
sub.f32 %f746, %f731, %f745;
|
|
add.f32 %f747, %f739, %f746;
|
|
add.f32 %f748, %f744, %f747;
|
|
add.f32 %f749, %f745, %f748;
|
|
sub.f32 %f750, %f745, %f749;
|
|
add.f32 %f751, %f748, %f750;
|
|
mov.f32 %f752, 0f3F317200;
|
|
mul.rn.f32 %f753, %f725, %f752;
|
|
mov.f32 %f754, 0f35BFBE8E;
|
|
mul.rn.f32 %f755, %f725, %f754;
|
|
add.f32 %f756, %f753, %f749;
|
|
sub.f32 %f757, %f753, %f756;
|
|
add.f32 %f758, %f749, %f757;
|
|
add.f32 %f759, %f751, %f758;
|
|
add.f32 %f760, %f755, %f759;
|
|
add.f32 %f761, %f756, %f760;
|
|
sub.f32 %f762, %f756, %f761;
|
|
add.f32 %f763, %f760, %f762;
|
|
mov.f32 %f764, 0f3EE66666;
|
|
mul.rn.f32 %f765, %f764, %f761;
|
|
neg.f32 %f766, %f765;
|
|
fma.rn.f32 %f767, %f764, %f761, %f766;
|
|
fma.rn.f32 %f768, %f764, %f763, %f767;
|
|
mov.f32 %f769, 0f00000000;
|
|
fma.rn.f32 %f770, %f769, %f761, %f768;
|
|
add.rn.f32 %f771, %f765, %f770;
|
|
neg.f32 %f772, %f771;
|
|
add.rn.f32 %f773, %f765, %f772;
|
|
add.rn.f32 %f774, %f773, %f770;
|
|
mov.b32 %r244, %f771;
|
|
setp.eq.s32 %p77, %r244, 1118925336;
|
|
add.s32 %r245, %r244, -1;
|
|
mov.b32 %f775, %r245;
|
|
add.f32 %f776, %f774, 0f37000000;
|
|
selp.f32 %f262, %f776, %f774, %p77;
|
|
selp.f32 %f777, %f775, %f771, %p77;
|
|
mov.f32 %f778, 0f3FB8AA3B;
|
|
mul.rn.f32 %f779, %f777, %f778;
|
|
cvt.rzi.f32.f32 %f780, %f779;
|
|
abs.f32 %f781, %f780;
|
|
setp.gt.f32 %p78, %f781, 0f42FC0000;
|
|
mov.b32 %r246, %f780;
|
|
and.b32 %r247, %r246, -2147483648;
|
|
or.b32 %r248, %r247, 1123811328;
|
|
mov.b32 %f782, %r248;
|
|
selp.f32 %f783, %f782, %f780, %p78;
|
|
mov.f32 %f784, 0fBF317218;
|
|
fma.rn.f32 %f785, %f783, %f784, %f777;
|
|
mov.f32 %f786, 0f3102E308;
|
|
fma.rn.f32 %f787, %f783, %f786, %f785;
|
|
mul.f32 %f788, %f787, 0f3FB8AA3B;
|
|
add.f32 %f789, %f783, 0f4B40007F;
|
|
mov.b32 %r249, %f789;
|
|
shl.b32 %r250, %r249, 23;
|
|
mov.b32 %f790, %r250;
|
|
ex2.approx.ftz.f32 %f791, %f788;
|
|
mul.f32 %f263, %f791, %f790;
|
|
setp.eq.f32 %p79, %f263, 0f7F800000;
|
|
mov.f32 %f1441, 0f7F800000;
|
|
@%p79 bra $L__BB0_63;
|
|
|
|
fma.rn.f32 %f1441, %f263, %f262, %f263;
|
|
|
|
$L__BB0_63:
|
|
setp.lt.f32 %p80, %f235, 0f00000000;
|
|
and.pred %p3, %p80, %p51;
|
|
setp.eq.f32 %p82, %f235, 0f00000000;
|
|
@%p82 bra $L__BB0_67;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_67:
|
|
add.f32 %f796, %f235, %f235;
|
|
selp.f32 %f1443, %f796, 0f00000000, %p51;
|
|
bra.uni $L__BB0_68;
|
|
|
|
$L__BB0_64:
|
|
mov.b32 %r251, %f1441;
|
|
xor.b32 %r252, %r251, -2147483648;
|
|
mov.b32 %f792, %r252;
|
|
selp.f32 %f1443, %f792, %f1441, %p3;
|
|
setp.geu.f32 %p83, %f235, 0f00000000;
|
|
@%p83 bra $L__BB0_68;
|
|
|
|
mov.f32 %f793, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f794, %f793;
|
|
setp.eq.f32 %p84, %f794, 0f3EE66666;
|
|
@%p84 bra $L__BB0_68;
|
|
|
|
mov.f32 %f1443, 0f7FFFFFFF;
|
|
|
|
$L__BB0_68:
|
|
add.f32 %f797, %f261, 0f3EE66666;
|
|
mov.b32 %r253, %f797;
|
|
setp.lt.s32 %p86, %r253, 2139095040;
|
|
@%p86 bra $L__BB0_73;
|
|
|
|
setp.gtu.f32 %p87, %f261, 0f7F800000;
|
|
@%p87 bra $L__BB0_72;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_72:
|
|
add.f32 %f1443, %f235, 0f3EE66666;
|
|
bra.uni $L__BB0_73;
|
|
|
|
$L__BB0_70:
|
|
setp.neu.f32 %p88, %f261, 0f7F800000;
|
|
@%p88 bra $L__BB0_73;
|
|
|
|
selp.f32 %f1443, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_73:
|
|
setp.eq.f32 %p89, %f235, 0f3F800000;
|
|
mov.f32 %f799, 0f3F800000;
|
|
selp.f32 %f800, 0f3F800000, %f1443, %p89;
|
|
ld.const.u64 %rd76, [params+144];
|
|
cvta.to.global.u64 %rd14, %rd76;
|
|
ld.const.u32 %r254, [params+136];
|
|
mad.lo.s32 %r255, %r254, %r6, %r5;
|
|
cvt.u64.u32 %rd15, %r255;
|
|
min.f32 %f801, %f248, %f799;
|
|
mov.f32 %f802, 0f00000000;
|
|
max.f32 %f272, %f802, %f801;
|
|
min.f32 %f803, %f260, %f799;
|
|
max.f32 %f273, %f802, %f803;
|
|
min.f32 %f804, %f800, %f799;
|
|
max.f32 %f274, %f802, %f804;
|
|
mov.f32 %f805, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f806, %f805;
|
|
add.f32 %f807, %f806, %f806;
|
|
mov.f32 %f808, 0f3ED55555;
|
|
sub.f32 %f809, %f808, %f807;
|
|
abs.f32 %f275, %f809;
|
|
abs.f32 %f276, %f272;
|
|
setp.lt.f32 %p90, %f276, 0f00800000;
|
|
mul.f32 %f810, %f276, 0f4B800000;
|
|
selp.f32 %f811, %f810, %f276, %p90;
|
|
selp.f32 %f812, 0fC3170000, 0fC2FE0000, %p90;
|
|
mov.b32 %r256, %f811;
|
|
and.b32 %r257, %r256, 8388607;
|
|
or.b32 %r258, %r257, 1065353216;
|
|
mov.b32 %f813, %r258;
|
|
shr.u32 %r259, %r256, 23;
|
|
cvt.rn.f32.u32 %f814, %r259;
|
|
add.f32 %f815, %f812, %f814;
|
|
setp.gt.f32 %p91, %f813, 0f3FB504F3;
|
|
mul.f32 %f816, %f813, 0f3F000000;
|
|
add.f32 %f817, %f815, 0f3F800000;
|
|
selp.f32 %f818, %f817, %f815, %p91;
|
|
selp.f32 %f819, %f816, %f813, %p91;
|
|
add.f32 %f820, %f819, 0fBF800000;
|
|
add.f32 %f821, %f819, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f822, %f821;
|
|
add.f32 %f823, %f820, %f820;
|
|
mul.f32 %f824, %f823, %f822;
|
|
mul.f32 %f825, %f824, %f824;
|
|
mov.f32 %f826, 0f3C4CAF63;
|
|
mov.f32 %f827, 0f3B18F0FE;
|
|
fma.rn.f32 %f828, %f827, %f825, %f826;
|
|
mov.f32 %f829, 0f3DAAAABD;
|
|
fma.rn.f32 %f830, %f828, %f825, %f829;
|
|
mul.rn.f32 %f831, %f830, %f825;
|
|
mul.rn.f32 %f832, %f831, %f824;
|
|
sub.f32 %f833, %f820, %f824;
|
|
add.f32 %f834, %f833, %f833;
|
|
neg.f32 %f835, %f824;
|
|
fma.rn.f32 %f836, %f835, %f820, %f834;
|
|
mul.rn.f32 %f837, %f822, %f836;
|
|
add.f32 %f838, %f832, %f824;
|
|
sub.f32 %f839, %f824, %f838;
|
|
add.f32 %f840, %f832, %f839;
|
|
add.f32 %f841, %f837, %f840;
|
|
add.f32 %f842, %f838, %f841;
|
|
sub.f32 %f843, %f838, %f842;
|
|
add.f32 %f844, %f841, %f843;
|
|
mov.f32 %f845, 0f3F317200;
|
|
mul.rn.f32 %f846, %f818, %f845;
|
|
mov.f32 %f847, 0f35BFBE8E;
|
|
mul.rn.f32 %f848, %f818, %f847;
|
|
add.f32 %f849, %f846, %f842;
|
|
sub.f32 %f850, %f846, %f849;
|
|
add.f32 %f851, %f842, %f850;
|
|
add.f32 %f852, %f844, %f851;
|
|
add.f32 %f853, %f848, %f852;
|
|
add.f32 %f854, %f849, %f853;
|
|
sub.f32 %f855, %f849, %f854;
|
|
add.f32 %f856, %f853, %f855;
|
|
mul.rn.f32 %f857, %f808, %f854;
|
|
neg.f32 %f858, %f857;
|
|
fma.rn.f32 %f859, %f808, %f854, %f858;
|
|
fma.rn.f32 %f860, %f808, %f856, %f859;
|
|
fma.rn.f32 %f861, %f802, %f854, %f860;
|
|
add.rn.f32 %f862, %f857, %f861;
|
|
neg.f32 %f863, %f862;
|
|
add.rn.f32 %f864, %f857, %f863;
|
|
add.rn.f32 %f865, %f864, %f861;
|
|
mov.b32 %r260, %f862;
|
|
setp.eq.s32 %p92, %r260, 1118925336;
|
|
add.s32 %r261, %r260, -1;
|
|
mov.b32 %f866, %r261;
|
|
add.f32 %f867, %f865, 0f37000000;
|
|
selp.f32 %f277, %f867, %f865, %p92;
|
|
selp.f32 %f868, %f866, %f862, %p92;
|
|
mov.f32 %f869, 0f3FB8AA3B;
|
|
mul.rn.f32 %f870, %f868, %f869;
|
|
cvt.rzi.f32.f32 %f871, %f870;
|
|
abs.f32 %f872, %f871;
|
|
setp.gt.f32 %p93, %f872, 0f42FC0000;
|
|
mov.b32 %r262, %f871;
|
|
and.b32 %r263, %r262, -2147483648;
|
|
or.b32 %r264, %r263, 1123811328;
|
|
mov.b32 %f873, %r264;
|
|
selp.f32 %f874, %f873, %f871, %p93;
|
|
mov.f32 %f875, 0fBF317218;
|
|
fma.rn.f32 %f876, %f874, %f875, %f868;
|
|
mov.f32 %f877, 0f3102E308;
|
|
fma.rn.f32 %f878, %f874, %f877, %f876;
|
|
mul.f32 %f879, %f878, 0f3FB8AA3B;
|
|
add.f32 %f880, %f874, 0f4B40007F;
|
|
mov.b32 %r265, %f880;
|
|
shl.b32 %r266, %r265, 23;
|
|
mov.b32 %f881, %r266;
|
|
ex2.approx.ftz.f32 %f882, %f879;
|
|
mul.f32 %f278, %f882, %f881;
|
|
setp.eq.f32 %p94, %f278, 0f7F800000;
|
|
mov.f32 %f1444, 0f7F800000;
|
|
@%p94 bra $L__BB0_75;
|
|
|
|
fma.rn.f32 %f1444, %f278, %f277, %f278;
|
|
|
|
$L__BB0_75:
|
|
setp.lt.f32 %p95, %f272, 0f00000000;
|
|
setp.eq.f32 %p96, %f275, 0f3F800000;
|
|
and.pred %p4, %p95, %p96;
|
|
setp.eq.f32 %p97, %f272, 0f00000000;
|
|
@%p97 bra $L__BB0_79;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_79:
|
|
add.f32 %f887, %f272, %f272;
|
|
selp.f32 %f1446, %f887, 0f00000000, %p96;
|
|
bra.uni $L__BB0_80;
|
|
|
|
$L__BB0_76:
|
|
mov.b32 %r267, %f1444;
|
|
xor.b32 %r268, %r267, -2147483648;
|
|
mov.b32 %f883, %r268;
|
|
selp.f32 %f1446, %f883, %f1444, %p4;
|
|
setp.geu.f32 %p98, %f272, 0f00000000;
|
|
@%p98 bra $L__BB0_80;
|
|
|
|
mov.f32 %f884, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f885, %f884;
|
|
setp.eq.f32 %p99, %f885, 0f3ED55555;
|
|
@%p99 bra $L__BB0_80;
|
|
|
|
mov.f32 %f1446, 0f7FFFFFFF;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f888, %f276, 0f3ED55555;
|
|
mov.b32 %r269, %f888;
|
|
setp.lt.s32 %p101, %r269, 2139095040;
|
|
@%p101 bra $L__BB0_85;
|
|
|
|
setp.gtu.f32 %p102, %f276, 0f7F800000;
|
|
@%p102 bra $L__BB0_84;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_84:
|
|
add.f32 %f1446, %f272, 0f3ED55555;
|
|
bra.uni $L__BB0_85;
|
|
|
|
$L__BB0_82:
|
|
setp.neu.f32 %p103, %f276, 0f7F800000;
|
|
@%p103 bra $L__BB0_85;
|
|
|
|
selp.f32 %f1446, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_85:
|
|
abs.f32 %f287, %f273;
|
|
setp.lt.f32 %p104, %f287, 0f00800000;
|
|
mul.f32 %f890, %f287, 0f4B800000;
|
|
selp.f32 %f891, %f890, %f287, %p104;
|
|
selp.f32 %f892, 0fC3170000, 0fC2FE0000, %p104;
|
|
mov.b32 %r270, %f891;
|
|
and.b32 %r271, %r270, 8388607;
|
|
or.b32 %r272, %r271, 1065353216;
|
|
mov.b32 %f893, %r272;
|
|
shr.u32 %r273, %r270, 23;
|
|
cvt.rn.f32.u32 %f894, %r273;
|
|
add.f32 %f895, %f892, %f894;
|
|
setp.gt.f32 %p105, %f893, 0f3FB504F3;
|
|
mul.f32 %f896, %f893, 0f3F000000;
|
|
add.f32 %f897, %f895, 0f3F800000;
|
|
selp.f32 %f898, %f897, %f895, %p105;
|
|
selp.f32 %f899, %f896, %f893, %p105;
|
|
add.f32 %f900, %f899, 0fBF800000;
|
|
add.f32 %f901, %f899, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f902, %f901;
|
|
add.f32 %f903, %f900, %f900;
|
|
mul.f32 %f904, %f903, %f902;
|
|
mul.f32 %f905, %f904, %f904;
|
|
mov.f32 %f906, 0f3C4CAF63;
|
|
mov.f32 %f907, 0f3B18F0FE;
|
|
fma.rn.f32 %f908, %f907, %f905, %f906;
|
|
mov.f32 %f909, 0f3DAAAABD;
|
|
fma.rn.f32 %f910, %f908, %f905, %f909;
|
|
mul.rn.f32 %f911, %f910, %f905;
|
|
mul.rn.f32 %f912, %f911, %f904;
|
|
sub.f32 %f913, %f900, %f904;
|
|
add.f32 %f914, %f913, %f913;
|
|
neg.f32 %f915, %f904;
|
|
fma.rn.f32 %f916, %f915, %f900, %f914;
|
|
mul.rn.f32 %f917, %f902, %f916;
|
|
add.f32 %f918, %f912, %f904;
|
|
sub.f32 %f919, %f904, %f918;
|
|
add.f32 %f920, %f912, %f919;
|
|
add.f32 %f921, %f917, %f920;
|
|
add.f32 %f922, %f918, %f921;
|
|
sub.f32 %f923, %f918, %f922;
|
|
add.f32 %f924, %f921, %f923;
|
|
mov.f32 %f925, 0f3F317200;
|
|
mul.rn.f32 %f926, %f898, %f925;
|
|
mov.f32 %f927, 0f35BFBE8E;
|
|
mul.rn.f32 %f928, %f898, %f927;
|
|
add.f32 %f929, %f926, %f922;
|
|
sub.f32 %f930, %f926, %f929;
|
|
add.f32 %f931, %f922, %f930;
|
|
add.f32 %f932, %f924, %f931;
|
|
add.f32 %f933, %f928, %f932;
|
|
add.f32 %f934, %f929, %f933;
|
|
sub.f32 %f935, %f929, %f934;
|
|
add.f32 %f936, %f933, %f935;
|
|
mov.f32 %f937, 0f3ED55555;
|
|
mul.rn.f32 %f938, %f937, %f934;
|
|
neg.f32 %f939, %f938;
|
|
fma.rn.f32 %f940, %f937, %f934, %f939;
|
|
fma.rn.f32 %f941, %f937, %f936, %f940;
|
|
mov.f32 %f942, 0f00000000;
|
|
fma.rn.f32 %f943, %f942, %f934, %f941;
|
|
add.rn.f32 %f944, %f938, %f943;
|
|
neg.f32 %f945, %f944;
|
|
add.rn.f32 %f946, %f938, %f945;
|
|
add.rn.f32 %f947, %f946, %f943;
|
|
mov.b32 %r274, %f944;
|
|
setp.eq.s32 %p106, %r274, 1118925336;
|
|
add.s32 %r275, %r274, -1;
|
|
mov.b32 %f948, %r275;
|
|
add.f32 %f949, %f947, 0f37000000;
|
|
selp.f32 %f288, %f949, %f947, %p106;
|
|
selp.f32 %f950, %f948, %f944, %p106;
|
|
mov.f32 %f951, 0f3FB8AA3B;
|
|
mul.rn.f32 %f952, %f950, %f951;
|
|
cvt.rzi.f32.f32 %f953, %f952;
|
|
abs.f32 %f954, %f953;
|
|
setp.gt.f32 %p107, %f954, 0f42FC0000;
|
|
mov.b32 %r276, %f953;
|
|
and.b32 %r277, %r276, -2147483648;
|
|
or.b32 %r278, %r277, 1123811328;
|
|
mov.b32 %f955, %r278;
|
|
selp.f32 %f956, %f955, %f953, %p107;
|
|
mov.f32 %f957, 0fBF317218;
|
|
fma.rn.f32 %f958, %f956, %f957, %f950;
|
|
mov.f32 %f959, 0f3102E308;
|
|
fma.rn.f32 %f960, %f956, %f959, %f958;
|
|
mul.f32 %f961, %f960, 0f3FB8AA3B;
|
|
add.f32 %f962, %f956, 0f4B40007F;
|
|
mov.b32 %r279, %f962;
|
|
shl.b32 %r280, %r279, 23;
|
|
mov.b32 %f963, %r280;
|
|
ex2.approx.ftz.f32 %f964, %f961;
|
|
mul.f32 %f289, %f964, %f963;
|
|
setp.eq.f32 %p108, %f289, 0f7F800000;
|
|
mov.f32 %f1447, 0f7F800000;
|
|
@%p108 bra $L__BB0_87;
|
|
|
|
fma.rn.f32 %f1447, %f289, %f288, %f289;
|
|
|
|
$L__BB0_87:
|
|
setp.lt.f32 %p109, %f273, 0f00000000;
|
|
and.pred %p5, %p109, %p96;
|
|
setp.eq.f32 %p111, %f273, 0f00000000;
|
|
@%p111 bra $L__BB0_91;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_91:
|
|
add.f32 %f969, %f273, %f273;
|
|
selp.f32 %f1449, %f969, 0f00000000, %p96;
|
|
bra.uni $L__BB0_92;
|
|
|
|
$L__BB0_88:
|
|
mov.b32 %r281, %f1447;
|
|
xor.b32 %r282, %r281, -2147483648;
|
|
mov.b32 %f965, %r282;
|
|
selp.f32 %f1449, %f965, %f1447, %p5;
|
|
setp.geu.f32 %p112, %f273, 0f00000000;
|
|
@%p112 bra $L__BB0_92;
|
|
|
|
mov.f32 %f966, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f967, %f966;
|
|
setp.eq.f32 %p113, %f967, 0f3ED55555;
|
|
@%p113 bra $L__BB0_92;
|
|
|
|
mov.f32 %f1449, 0f7FFFFFFF;
|
|
|
|
$L__BB0_92:
|
|
add.f32 %f970, %f287, 0f3ED55555;
|
|
mov.b32 %r283, %f970;
|
|
setp.lt.s32 %p115, %r283, 2139095040;
|
|
@%p115 bra $L__BB0_97;
|
|
|
|
setp.gtu.f32 %p116, %f287, 0f7F800000;
|
|
@%p116 bra $L__BB0_96;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_96:
|
|
add.f32 %f1449, %f273, 0f3ED55555;
|
|
bra.uni $L__BB0_97;
|
|
|
|
$L__BB0_94:
|
|
setp.neu.f32 %p117, %f287, 0f7F800000;
|
|
@%p117 bra $L__BB0_97;
|
|
|
|
selp.f32 %f1449, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_97:
|
|
abs.f32 %f298, %f274;
|
|
setp.lt.f32 %p118, %f298, 0f00800000;
|
|
mul.f32 %f972, %f298, 0f4B800000;
|
|
selp.f32 %f973, %f972, %f298, %p118;
|
|
selp.f32 %f974, 0fC3170000, 0fC2FE0000, %p118;
|
|
mov.b32 %r284, %f973;
|
|
and.b32 %r285, %r284, 8388607;
|
|
or.b32 %r286, %r285, 1065353216;
|
|
mov.b32 %f975, %r286;
|
|
shr.u32 %r287, %r284, 23;
|
|
cvt.rn.f32.u32 %f976, %r287;
|
|
add.f32 %f977, %f974, %f976;
|
|
setp.gt.f32 %p119, %f975, 0f3FB504F3;
|
|
mul.f32 %f978, %f975, 0f3F000000;
|
|
add.f32 %f979, %f977, 0f3F800000;
|
|
selp.f32 %f980, %f979, %f977, %p119;
|
|
selp.f32 %f981, %f978, %f975, %p119;
|
|
add.f32 %f982, %f981, 0fBF800000;
|
|
add.f32 %f983, %f981, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f984, %f983;
|
|
add.f32 %f985, %f982, %f982;
|
|
mul.f32 %f986, %f985, %f984;
|
|
mul.f32 %f987, %f986, %f986;
|
|
mov.f32 %f988, 0f3C4CAF63;
|
|
mov.f32 %f989, 0f3B18F0FE;
|
|
fma.rn.f32 %f990, %f989, %f987, %f988;
|
|
mov.f32 %f991, 0f3DAAAABD;
|
|
fma.rn.f32 %f992, %f990, %f987, %f991;
|
|
mul.rn.f32 %f993, %f992, %f987;
|
|
mul.rn.f32 %f994, %f993, %f986;
|
|
sub.f32 %f995, %f982, %f986;
|
|
add.f32 %f996, %f995, %f995;
|
|
neg.f32 %f997, %f986;
|
|
fma.rn.f32 %f998, %f997, %f982, %f996;
|
|
mul.rn.f32 %f999, %f984, %f998;
|
|
add.f32 %f1000, %f994, %f986;
|
|
sub.f32 %f1001, %f986, %f1000;
|
|
add.f32 %f1002, %f994, %f1001;
|
|
add.f32 %f1003, %f999, %f1002;
|
|
add.f32 %f1004, %f1000, %f1003;
|
|
sub.f32 %f1005, %f1000, %f1004;
|
|
add.f32 %f1006, %f1003, %f1005;
|
|
mov.f32 %f1007, 0f3F317200;
|
|
mul.rn.f32 %f1008, %f980, %f1007;
|
|
mov.f32 %f1009, 0f35BFBE8E;
|
|
mul.rn.f32 %f1010, %f980, %f1009;
|
|
add.f32 %f1011, %f1008, %f1004;
|
|
sub.f32 %f1012, %f1008, %f1011;
|
|
add.f32 %f1013, %f1004, %f1012;
|
|
add.f32 %f1014, %f1006, %f1013;
|
|
add.f32 %f1015, %f1010, %f1014;
|
|
add.f32 %f1016, %f1011, %f1015;
|
|
sub.f32 %f1017, %f1011, %f1016;
|
|
add.f32 %f1018, %f1015, %f1017;
|
|
mov.f32 %f1019, 0f3ED55555;
|
|
mul.rn.f32 %f1020, %f1019, %f1016;
|
|
neg.f32 %f1021, %f1020;
|
|
fma.rn.f32 %f1022, %f1019, %f1016, %f1021;
|
|
fma.rn.f32 %f1023, %f1019, %f1018, %f1022;
|
|
mov.f32 %f1024, 0f00000000;
|
|
fma.rn.f32 %f1025, %f1024, %f1016, %f1023;
|
|
add.rn.f32 %f1026, %f1020, %f1025;
|
|
neg.f32 %f1027, %f1026;
|
|
add.rn.f32 %f1028, %f1020, %f1027;
|
|
add.rn.f32 %f1029, %f1028, %f1025;
|
|
mov.b32 %r288, %f1026;
|
|
setp.eq.s32 %p120, %r288, 1118925336;
|
|
add.s32 %r289, %r288, -1;
|
|
mov.b32 %f1030, %r289;
|
|
add.f32 %f1031, %f1029, 0f37000000;
|
|
selp.f32 %f299, %f1031, %f1029, %p120;
|
|
selp.f32 %f1032, %f1030, %f1026, %p120;
|
|
mov.f32 %f1033, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1034, %f1032, %f1033;
|
|
cvt.rzi.f32.f32 %f1035, %f1034;
|
|
abs.f32 %f1036, %f1035;
|
|
setp.gt.f32 %p121, %f1036, 0f42FC0000;
|
|
mov.b32 %r290, %f1035;
|
|
and.b32 %r291, %r290, -2147483648;
|
|
or.b32 %r292, %r291, 1123811328;
|
|
mov.b32 %f1037, %r292;
|
|
selp.f32 %f1038, %f1037, %f1035, %p121;
|
|
mov.f32 %f1039, 0fBF317218;
|
|
fma.rn.f32 %f1040, %f1038, %f1039, %f1032;
|
|
mov.f32 %f1041, 0f3102E308;
|
|
fma.rn.f32 %f1042, %f1038, %f1041, %f1040;
|
|
mul.f32 %f1043, %f1042, 0f3FB8AA3B;
|
|
add.f32 %f1044, %f1038, 0f4B40007F;
|
|
mov.b32 %r293, %f1044;
|
|
shl.b32 %r294, %r293, 23;
|
|
mov.b32 %f1045, %r294;
|
|
ex2.approx.ftz.f32 %f1046, %f1043;
|
|
mul.f32 %f300, %f1046, %f1045;
|
|
setp.eq.f32 %p122, %f300, 0f7F800000;
|
|
mov.f32 %f1450, 0f7F800000;
|
|
@%p122 bra $L__BB0_99;
|
|
|
|
fma.rn.f32 %f1450, %f300, %f299, %f300;
|
|
|
|
$L__BB0_99:
|
|
setp.lt.f32 %p123, %f274, 0f00000000;
|
|
and.pred %p6, %p123, %p96;
|
|
setp.eq.f32 %p125, %f274, 0f00000000;
|
|
@%p125 bra $L__BB0_103;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_103:
|
|
add.f32 %f1051, %f274, %f274;
|
|
selp.f32 %f1452, %f1051, 0f00000000, %p96;
|
|
bra.uni $L__BB0_104;
|
|
|
|
$L__BB0_100:
|
|
mov.b32 %r295, %f1450;
|
|
xor.b32 %r296, %r295, -2147483648;
|
|
mov.b32 %f1047, %r296;
|
|
selp.f32 %f1452, %f1047, %f1450, %p6;
|
|
setp.geu.f32 %p126, %f274, 0f00000000;
|
|
@%p126 bra $L__BB0_104;
|
|
|
|
mov.f32 %f1048, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1049, %f1048;
|
|
setp.eq.f32 %p127, %f1049, 0f3ED55555;
|
|
@%p127 bra $L__BB0_104;
|
|
|
|
mov.f32 %f1452, 0f7FFFFFFF;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f1052, %f298, 0f3ED55555;
|
|
mov.b32 %r297, %f1052;
|
|
setp.lt.s32 %p129, %r297, 2139095040;
|
|
@%p129 bra $L__BB0_109;
|
|
|
|
setp.gtu.f32 %p130, %f298, 0f7F800000;
|
|
@%p130 bra $L__BB0_108;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_108:
|
|
add.f32 %f1452, %f274, 0f3ED55555;
|
|
bra.uni $L__BB0_109;
|
|
|
|
$L__BB0_106:
|
|
setp.neu.f32 %p131, %f298, 0f7F800000;
|
|
@%p131 bra $L__BB0_109;
|
|
|
|
selp.f32 %f1452, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_109:
|
|
fma.rn.f32 %f1053, %f1446, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p132, %f272, 0f3F800000;
|
|
mov.f32 %f1054, 0f3F800000;
|
|
selp.f32 %f1055, 0f3F7FFFFF, %f1053, %p132;
|
|
mul.f32 %f1056, %f272, 0f414EB852;
|
|
setp.lt.f32 %p133, %f272, 0f3B4D2E1C;
|
|
selp.f32 %f1057, %f1056, %f1055, %p133;
|
|
fma.rn.f32 %f1058, %f1449, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p134, %f273, 0f3F800000;
|
|
selp.f32 %f1059, 0f3F7FFFFF, %f1058, %p134;
|
|
mul.f32 %f1060, %f273, 0f414EB852;
|
|
setp.lt.f32 %p135, %f273, 0f3B4D2E1C;
|
|
selp.f32 %f1061, %f1060, %f1059, %p135;
|
|
fma.rn.f32 %f1062, %f1452, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p136, %f274, 0f3F800000;
|
|
selp.f32 %f1063, 0f3F7FFFFF, %f1062, %p136;
|
|
mul.f32 %f1064, %f274, 0f414EB852;
|
|
setp.lt.f32 %p137, %f274, 0f3B4D2E1C;
|
|
selp.f32 %f1065, %f1064, %f1063, %p137;
|
|
min.f32 %f1066, %f1057, %f1054;
|
|
mov.f32 %f1067, 0f00000000;
|
|
max.f32 %f1068, %f1067, %f1066;
|
|
mul.f32 %f1069, %f1068, 0f43800000;
|
|
cvt.rzi.u32.f32 %r298, %f1069;
|
|
min.u32 %r299, %r298, 255;
|
|
min.f32 %f1070, %f1061, %f1054;
|
|
max.f32 %f1071, %f1067, %f1070;
|
|
mul.f32 %f1072, %f1071, 0f43800000;
|
|
cvt.rzi.u32.f32 %r300, %f1072;
|
|
min.u32 %r301, %r300, 255;
|
|
min.f32 %f1073, %f1065, %f1054;
|
|
max.f32 %f1074, %f1067, %f1073;
|
|
mul.f32 %f1075, %f1074, 0f43800000;
|
|
cvt.rzi.u32.f32 %r302, %f1075;
|
|
min.u32 %r303, %r302, 255;
|
|
shl.b64 %rd77, %rd15, 2;
|
|
add.s64 %rd78, %rd14, %rd77;
|
|
cvt.u16.u32 %rs15, %r303;
|
|
cvt.u16.u32 %rs16, %r301;
|
|
cvt.u16.u32 %rs17, %r299;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v4.u8 [%rd78], {%rs17, %rs16, %rs15, %rs18};
|
|
|
|
$L__BB0_110:
|
|
and.b32 %r304, %r52, 4;
|
|
setp.eq.s32 %p138, %r304, 0;
|
|
ld.const.u32 %r379, [params+108];
|
|
@%p138 bra $L__BB0_114;
|
|
|
|
setp.eq.s32 %p139, %r379, 0;
|
|
ld.const.u64 %rd79, [params+224];
|
|
cvta.to.global.u64 %rd80, %rd79;
|
|
ld.const.u32 %r305, [params+216];
|
|
mad.lo.s32 %r306, %r305, %r6, %r5;
|
|
mul.wide.u32 %rd81, %r306, 8;
|
|
add.s64 %rd16, %rd80, %rd81;
|
|
@%p139 bra $L__BB0_113;
|
|
|
|
ld.global.v4.u16 {%rs26, %rs27, %rs28, %rs29}, [%rd16];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1076, %rs26;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1077, %rs27;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1078, %rs28;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1079, %f233, %f1076;
|
|
add.f32 %f1080, %f234, %f1077;
|
|
add.f32 %f1081, %f235, %f1078;
|
|
mov.f32 %f1082, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs24, %f1081;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs23, %f1080;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs22, %f1079;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs25, %f1082;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd16], {%rs22, %rs23, %rs24, %rs25};
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_113:
|
|
mov.f32 %f1086, 0f3F800000;
|
|
mov.u32 %r379, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f1086;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs32, %f235;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs31, %f234;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f233;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd16], {%rs30, %rs31, %rs32, %rs33};
|
|
|
|
$L__BB0_114:
|
|
mul.f32 %f309, %f544, 0f40800000;
|
|
mul.f32 %f1087, %f203, %f309;
|
|
mul.f32 %f310, %f545, 0f40800000;
|
|
mul.f32 %f1088, %f204, %f310;
|
|
mul.f32 %f311, %f546, 0f40800000;
|
|
mul.f32 %f1089, %f205, %f311;
|
|
mul.f32 %f312, %f1087, 0f3F558750;
|
|
mul.f32 %f313, %f1088, 0f3F558750;
|
|
mul.f32 %f314, %f1089, 0f3F558750;
|
|
ld.const.u64 %rd82, [params+256];
|
|
cvta.to.global.u64 %rd83, %rd82;
|
|
ld.const.u32 %r308, [params+248];
|
|
mad.lo.s32 %r309, %r308, %r6, %r5;
|
|
mul.wide.u32 %rd84, %r309, 8;
|
|
add.s64 %rd17, %rd83, %rd84;
|
|
setp.eq.s32 %p140, %r379, 0;
|
|
@%p140 bra $L__BB0_116;
|
|
|
|
ld.global.v4.u16 {%rs41, %rs42, %rs43, %rs44}, [%rd17];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1090, %rs41;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1091, %rs42;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1092, %rs43;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1093, %f312, %f1090;
|
|
add.f32 %f1094, %f313, %f1091;
|
|
add.f32 %f1095, %f314, %f1092;
|
|
mov.f32 %f1096, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs39, %f1095;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f1094;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f1093;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f1096;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd17], {%rs37, %rs38, %rs39, %rs40};
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_116:
|
|
mov.f32 %f1100, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f1100;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs47, %f314;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs46, %f313;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs45, %f312;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd17], {%rs45, %rs46, %rs47, %rs48};
|
|
|
|
$L__BB0_117:
|
|
mul.f32 %f1101, %f206, %f309;
|
|
mul.f32 %f315, %f1101, 0f3FB8EBD1;
|
|
mul.f32 %f1102, %f207, %f310;
|
|
mul.f32 %f316, %f1102, 0f3FB8EBD1;
|
|
mul.f32 %f1103, %f208, %f311;
|
|
mul.f32 %f317, %f1103, 0f3FB8EBD1;
|
|
ld.const.u64 %rd85, [params+272];
|
|
cvta.to.global.u64 %rd86, %rd85;
|
|
ld.const.u32 %r310, [params+264];
|
|
mad.lo.s32 %r311, %r310, %r6, %r5;
|
|
mul.wide.u32 %rd87, %r311, 8;
|
|
add.s64 %rd18, %rd86, %rd87;
|
|
@%p140 bra $L__BB0_119;
|
|
|
|
ld.global.v4.u16 {%rs56, %rs57, %rs58, %rs59}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1104, %rs56;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1105, %rs57;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1106, %rs58;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1107, %f315, %f1104;
|
|
add.f32 %f1108, %f316, %f1105;
|
|
add.f32 %f1109, %f317, %f1106;
|
|
mov.f32 %f1110, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f1109;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f1108;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f1107;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f1110;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs52, %rs53, %rs54, %rs55};
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_119:
|
|
mov.f32 %f1114, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f1114;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f317;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f316;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f315;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs60, %rs61, %rs62, %rs63};
|
|
|
|
$L__BB0_120:
|
|
mul.f32 %f1115, %f209, %f309;
|
|
mul.f32 %f318, %f1115, 0f3FB8EBD1;
|
|
mul.f32 %f1116, %f210, %f310;
|
|
mul.f32 %f319, %f1116, 0f3FB8EBD1;
|
|
mul.f32 %f1117, %f211, %f311;
|
|
mul.f32 %f320, %f1117, 0f3FB8EBD1;
|
|
ld.const.u64 %rd88, [params+288];
|
|
cvta.to.global.u64 %rd89, %rd88;
|
|
ld.const.u32 %r312, [params+280];
|
|
mad.lo.s32 %r313, %r312, %r6, %r5;
|
|
mul.wide.u32 %rd90, %r313, 8;
|
|
add.s64 %rd19, %rd89, %rd90;
|
|
@%p140 bra $L__BB0_122;
|
|
|
|
ld.global.v4.u16 {%rs71, %rs72, %rs73, %rs74}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1118, %rs71;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1119, %rs72;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1120, %rs73;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1121, %f318, %f1118;
|
|
add.f32 %f1122, %f319, %f1119;
|
|
add.f32 %f1123, %f320, %f1120;
|
|
mov.f32 %f1124, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f1123;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1122;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f1121;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1124;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs67, %rs68, %rs69, %rs70};
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_122:
|
|
mov.f32 %f1128, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f1128;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f320;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f319;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f318;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs75, %rs76, %rs77, %rs78};
|
|
|
|
$L__BB0_123:
|
|
mul.f32 %f1129, %f212, %f309;
|
|
mul.f32 %f321, %f1129, 0f3FB8EBD1;
|
|
mul.f32 %f1130, %f213, %f310;
|
|
mul.f32 %f322, %f1130, 0f3FB8EBD1;
|
|
mul.f32 %f1131, %f214, %f311;
|
|
mul.f32 %f323, %f1131, 0f3FB8EBD1;
|
|
ld.const.u64 %rd91, [params+304];
|
|
cvta.to.global.u64 %rd92, %rd91;
|
|
ld.const.u32 %r314, [params+296];
|
|
mad.lo.s32 %r315, %r314, %r6, %r5;
|
|
mul.wide.u32 %rd93, %r315, 8;
|
|
add.s64 %rd20, %rd92, %rd93;
|
|
@%p140 bra $L__BB0_125;
|
|
|
|
ld.global.v4.u16 {%rs86, %rs87, %rs88, %rs89}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1132, %rs86;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1133, %rs87;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1134, %rs88;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1135, %f321, %f1132;
|
|
add.f32 %f1136, %f322, %f1133;
|
|
add.f32 %f1137, %f323, %f1134;
|
|
mov.f32 %f1138, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1137;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1136;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f1135;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1138;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs82, %rs83, %rs84, %rs85};
|
|
bra.uni $L__BB0_126;
|
|
|
|
$L__BB0_125:
|
|
mov.f32 %f1142, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f1142;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f323;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f322;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f321;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs90, %rs91, %rs92, %rs93};
|
|
|
|
$L__BB0_126:
|
|
mul.f32 %f1143, %f215, %f309;
|
|
mul.f32 %f324, %f1143, 0f404EBF87;
|
|
mul.f32 %f1144, %f216, %f310;
|
|
mul.f32 %f325, %f1144, 0f404EBF87;
|
|
mul.f32 %f1145, %f217, %f311;
|
|
mul.f32 %f326, %f1145, 0f404EBF87;
|
|
ld.const.u64 %rd94, [params+320];
|
|
cvta.to.global.u64 %rd95, %rd94;
|
|
ld.const.u32 %r316, [params+312];
|
|
mad.lo.s32 %r317, %r316, %r6, %r5;
|
|
mul.wide.u32 %rd96, %r317, 8;
|
|
add.s64 %rd21, %rd95, %rd96;
|
|
@%p140 bra $L__BB0_128;
|
|
|
|
ld.global.v4.u16 {%rs101, %rs102, %rs103, %rs104}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1146, %rs101;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1147, %rs102;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1148, %rs103;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1149, %f324, %f1146;
|
|
add.f32 %f1150, %f325, %f1147;
|
|
add.f32 %f1151, %f326, %f1148;
|
|
mov.f32 %f1152, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs99, %f1151;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs98, %f1150;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f1149;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs100, %f1152;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs97, %rs98, %rs99, %rs100};
|
|
bra.uni $L__BB0_129;
|
|
|
|
$L__BB0_128:
|
|
mov.f32 %f1156, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f1156;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f326;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f325;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs105, %f324;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs105, %rs106, %rs107, %rs108};
|
|
|
|
$L__BB0_129:
|
|
mul.f32 %f1157, %f218, %f309;
|
|
mul.f32 %f327, %f1157, 0f404EBF87;
|
|
mul.f32 %f1158, %f219, %f310;
|
|
mul.f32 %f328, %f1158, 0f404EBF87;
|
|
mul.f32 %f1159, %f220, %f311;
|
|
mul.f32 %f329, %f1159, 0f404EBF87;
|
|
ld.const.u64 %rd97, [params+336];
|
|
cvta.to.global.u64 %rd98, %rd97;
|
|
ld.const.u32 %r318, [params+328];
|
|
mad.lo.s32 %r319, %r318, %r6, %r5;
|
|
mul.wide.u32 %rd99, %r319, 8;
|
|
add.s64 %rd22, %rd98, %rd99;
|
|
@%p140 bra $L__BB0_131;
|
|
|
|
ld.global.v4.u16 {%rs116, %rs117, %rs118, %rs119}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1160, %rs116;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1161, %rs117;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1162, %rs118;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1163, %f327, %f1160;
|
|
add.f32 %f1164, %f328, %f1161;
|
|
add.f32 %f1165, %f329, %f1162;
|
|
mov.f32 %f1166, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f1165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1164;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs112, %f1163;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1166;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs112, %rs113, %rs114, %rs115};
|
|
bra.uni $L__BB0_132;
|
|
|
|
$L__BB0_131:
|
|
mov.f32 %f1170, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f1170;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f329;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f328;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f327;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs120, %rs121, %rs122, %rs123};
|
|
|
|
$L__BB0_132:
|
|
mul.f32 %f1171, %f221, %f309;
|
|
mul.f32 %f330, %f1171, 0f40330C94;
|
|
mul.f32 %f1172, %f222, %f310;
|
|
mul.f32 %f331, %f1172, 0f40330C94;
|
|
mul.f32 %f1173, %f223, %f311;
|
|
mul.f32 %f332, %f1173, 0f40330C94;
|
|
ld.const.u64 %rd100, [params+352];
|
|
cvta.to.global.u64 %rd101, %rd100;
|
|
ld.const.u32 %r320, [params+344];
|
|
mad.lo.s32 %r321, %r320, %r6, %r5;
|
|
mul.wide.u32 %rd102, %r321, 8;
|
|
add.s64 %rd23, %rd101, %rd102;
|
|
@%p140 bra $L__BB0_134;
|
|
|
|
ld.global.v4.u16 {%rs131, %rs132, %rs133, %rs134}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1174, %rs131;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1175, %rs132;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1176, %rs133;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1177, %f330, %f1174;
|
|
add.f32 %f1178, %f331, %f1175;
|
|
add.f32 %f1179, %f332, %f1176;
|
|
mov.f32 %f1180, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1179;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1178;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1177;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1180;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs127, %rs128, %rs129, %rs130};
|
|
bra.uni $L__BB0_135;
|
|
|
|
$L__BB0_134:
|
|
mov.f32 %f1184, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f1184;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f332;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f331;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f330;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs135, %rs136, %rs137, %rs138};
|
|
|
|
$L__BB0_135:
|
|
mul.f32 %f1185, %f224, %f309;
|
|
mul.f32 %f333, %f1185, 0f404EBF87;
|
|
mul.f32 %f1186, %f225, %f310;
|
|
mul.f32 %f334, %f1186, 0f404EBF87;
|
|
mul.f32 %f1187, %f226, %f311;
|
|
mul.f32 %f335, %f1187, 0f404EBF87;
|
|
ld.const.u64 %rd103, [params+368];
|
|
cvta.to.global.u64 %rd104, %rd103;
|
|
ld.const.u32 %r322, [params+360];
|
|
mad.lo.s32 %r323, %r322, %r6, %r5;
|
|
mul.wide.u32 %rd105, %r323, 8;
|
|
add.s64 %rd24, %rd104, %rd105;
|
|
@%p140 bra $L__BB0_137;
|
|
|
|
ld.global.v4.u16 {%rs146, %rs147, %rs148, %rs149}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1188, %rs146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1189, %rs147;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1190, %rs148;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1191, %f333, %f1188;
|
|
add.f32 %f1192, %f334, %f1189;
|
|
add.f32 %f1193, %f335, %f1190;
|
|
mov.f32 %f1194, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1193;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1192;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1191;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1194;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs142, %rs143, %rs144, %rs145};
|
|
bra.uni $L__BB0_138;
|
|
|
|
$L__BB0_137:
|
|
mov.f32 %f1198, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f1198;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f335;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f334;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f333;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs150, %rs151, %rs152, %rs153};
|
|
|
|
$L__BB0_138:
|
|
mul.f32 %f1199, %f227, %f309;
|
|
mul.f32 %f336, %f1199, 0f3FCEBF87;
|
|
mul.f32 %f1200, %f228, %f310;
|
|
mul.f32 %f337, %f1200, 0f3FCEBF87;
|
|
mul.f32 %f1201, %f229, %f311;
|
|
mul.f32 %f338, %f1201, 0f3FCEBF87;
|
|
ld.const.u64 %rd106, [params+384];
|
|
cvta.to.global.u64 %rd107, %rd106;
|
|
ld.const.u32 %r324, [params+376];
|
|
mad.lo.s32 %r325, %r324, %r6, %r5;
|
|
mul.wide.u32 %rd108, %r325, 8;
|
|
add.s64 %rd25, %rd107, %rd108;
|
|
@%p140 bra $L__BB0_140;
|
|
|
|
ld.global.v4.u16 {%rs161, %rs162, %rs163, %rs164}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1202, %rs161;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1203, %rs162;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1204, %rs163;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1205, %f336, %f1202;
|
|
add.f32 %f1206, %f337, %f1203;
|
|
add.f32 %f1207, %f338, %f1204;
|
|
mov.f32 %f1208, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1207;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1206;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1205;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1208;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs157, %rs158, %rs159, %rs160};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_140:
|
|
mov.f32 %f1212, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs168, %f1212;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs167, %f338;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f337;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f336;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs165, %rs166, %rs167, %rs168};
|
|
|
|
$L__BB0_174:
|
|
ret;
|
|
|
|
}
|
|
|