3305 lines
88 KiB
Plaintext
3305 lines
88 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<209>;
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.reg .b16 %rs<327>;
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.reg .f32 %f<1587>;
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.reg .b32 %r<485>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<167>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r60), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r61), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+616];
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abs.s32 %r4, %r3;
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ld.const.u32 %r5, [params+540];
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shl.b32 %r6, %r5, 1;
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ld.const.u64 %rd44, [params+400];
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cvta.to.global.u64 %rd45, %rd44;
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ld.const.u32 %r66, [params+392];
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mad.lo.s32 %r67, %r66, %r61, %r60;
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mul.wide.u32 %rd46, %r67, 4;
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add.s64 %rd2, %rd45, %rd46;
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ld.global.v2.u8 {%rs7, %rs326}, [%rd2];
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or.b16 %rs9, %rs7, %rs326;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p10, %rs10, 0;
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@%p10 bra $L__BB0_2;
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ld.global.u8 %rs325, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs325, [%rd2+2];
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setp.eq.s16 %p11, %rs325, 0;
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mov.f32 %f1477, 0f00000000;
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mov.u16 %rs326, 0;
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mov.f32 %f1478, %f1477;
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mov.f32 %f1479, %f1477;
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@%p11 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f324, %rs7;
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div.rn.f32 %f325, %f324, 0f437F0000;
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fma.rn.f32 %f326, %f325, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs326, 255;
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cvt.rn.f32.u16 %f327, %rs13;
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div.rn.f32 %f328, %f327, 0f437F0000;
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fma.rn.f32 %f329, %f328, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f330, %rs325;
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div.rn.f32 %f331, %f330, 0f437F0000;
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fma.rn.f32 %f332, %f331, 0f40000000, 0fBF800000;
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mul.f32 %f333, %f329, %f329;
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fma.rn.f32 %f334, %f326, %f326, %f333;
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fma.rn.f32 %f335, %f332, %f332, %f334;
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sqrt.rn.f32 %f336, %f335;
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rcp.rn.f32 %f337, %f336;
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mul.f32 %f1479, %f337, %f332;
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mul.f32 %f1478, %f337, %f329;
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mul.f32 %f1477, %f326, %f337;
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$L__BB0_4:
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ld.const.v2.u32 {%r68, %r69}, [params];
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add.s32 %r7, %r68, %r60;
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add.s32 %r8, %r69, %r61;
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setp.eq.f32 %p12, %f1477, 0f00000000;
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setp.eq.f32 %p13, %f1478, 0f00000000;
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and.pred %p14, %p12, %p13;
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setp.eq.f32 %p15, %f1479, 0f00000000;
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and.pred %p16, %p15, %p14;
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@%p16 bra $L__BB0_173;
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bra.uni $L__BB0_5;
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$L__BB0_173:
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ld.const.u32 %r57, [params+104];
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and.b32 %r439, %r57, 1;
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setp.eq.b32 %p192, %r439, 1;
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mov.pred %p193, 0;
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xor.pred %p194, %p192, %p193;
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not.pred %p195, %p194;
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@%p195 bra $L__BB0_175;
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ld.const.u64 %rd122, [params+144];
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cvta.to.global.u64 %rd123, %rd122;
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ld.const.u32 %r440, [params+136];
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mad.lo.s32 %r441, %r440, %r8, %r7;
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mul.wide.u32 %rd124, %r441, 4;
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add.s64 %rd125, %rd123, %rd124;
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mov.u16 %rs172, 0;
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st.global.v4.u8 [%rd125], {%rs172, %rs172, %rs172, %rs172};
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$L__BB0_175:
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and.b32 %r442, %r57, 8;
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setp.eq.s32 %p196, %r442, 0;
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@%p196 bra $L__BB0_177;
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ld.const.u64 %rd126, [params+192];
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cvta.to.global.u64 %rd127, %rd126;
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ld.const.u32 %r443, [params+184];
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mad.lo.s32 %r444, %r443, %r8, %r7;
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mov.f32 %f1380, 0f00000000;
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cvt.rzi.u32.f32 %r445, %f1380;
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mul.wide.u32 %rd128, %r444, 2;
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add.s64 %rd129, %rd127, %rd128;
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mov.u16 %rs173, 0;
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cvt.u16.u32 %rs174, %r445;
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st.global.v2.u8 [%rd129], {%rs174, %rs173};
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$L__BB0_177:
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and.b32 %r446, %r57, 4;
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setp.eq.s32 %p197, %r446, 0;
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ld.const.u32 %r484, [params+108];
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@%p197 bra $L__BB0_181;
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setp.eq.s32 %p198, %r484, 0;
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ld.const.u64 %rd130, [params+224];
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cvta.to.global.u64 %rd131, %rd130;
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ld.const.u32 %r447, [params+216];
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mad.lo.s32 %r448, %r447, %r8, %r7;
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mul.wide.u32 %rd132, %r448, 8;
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add.s64 %rd33, %rd131, %rd132;
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@%p198 bra $L__BB0_180;
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ld.global.v4.u16 {%rs181, %rs182, %rs183, %rs184}, [%rd33];
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// begin inline asm
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{ cvt.f32.f16 %f1381, %rs181;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1382, %rs182;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1383, %rs183;}
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// end inline asm
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add.f32 %f1384, %f1381, 0f00000000;
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add.f32 %f1385, %f1382, 0f00000000;
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add.f32 %f1386, %f1383, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs180, %f1386;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs179, %f1385;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs178, %f1384;}
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// end inline asm
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mov.u16 %rs185, 0;
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st.global.v4.u16 [%rd33], {%rs178, %rs179, %rs180, %rs185};
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bra.uni $L__BB0_181;
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$L__BB0_5:
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ld.const.u64 %rd47, [params+432];
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cvta.to.global.u64 %rd48, %rd47;
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ld.const.u32 %r73, [params+424];
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mad.lo.s32 %r74, %r73, %r61, %r60;
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mul.wide.u32 %rd49, %r74, 12;
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add.s64 %rd50, %rd48, %rd49;
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ld.global.f32 %f10, [%rd50];
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mul.f32 %f349, %f10, 0f3456BF95;
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ld.global.f32 %f11, [%rd50+4];
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mul.f32 %f350, %f11, 0f3456BF95;
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ld.global.f32 %f12, [%rd50+8];
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mul.f32 %f351, %f12, 0f3456BF95;
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abs.f32 %f352, %f1477;
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div.rn.f32 %f353, %f349, %f352;
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abs.f32 %f354, %f1478;
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div.rn.f32 %f355, %f350, %f354;
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abs.f32 %f356, %f1479;
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div.rn.f32 %f357, %f351, %f356;
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abs.f32 %f358, %f353;
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abs.f32 %f359, %f355;
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abs.f32 %f360, %f357;
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mov.f32 %f361, 0f38D1B717;
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max.f32 %f362, %f358, %f361;
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max.f32 %f363, %f359, %f361;
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max.f32 %f364, %f360, %f361;
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fma.rn.f32 %f13, %f1477, %f362, %f10;
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fma.rn.f32 %f14, %f1478, %f363, %f11;
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fma.rn.f32 %f15, %f1479, %f364, %f12;
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ld.const.u64 %rd51, [params+128];
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cvta.to.global.u64 %rd52, %rd51;
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ld.const.u32 %r75, [params+120];
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mad.lo.s32 %r76, %r75, %r61, %r60;
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mul.wide.u32 %rd53, %r76, 4;
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add.s64 %rd54, %rd52, %rd53;
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ld.global.u32 %r475, [%rd54];
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setp.lt.s32 %p18, %r4, 1;
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mov.pred %p17, 0;
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mov.f32 %f1494, 0f00000000;
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mov.u32 %r471, 0;
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mov.f32 %f1495, %f1494;
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mov.f32 %f1496, %f1494;
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mov.f32 %f1497, %f1494;
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mov.f32 %f1498, %f1494;
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mov.f32 %f1499, %f1494;
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mov.f32 %f1500, %f1494;
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mov.f32 %f1501, %f1494;
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mov.f32 %f1502, %f1494;
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mov.f32 %f1503, %f1494;
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mov.f32 %f1504, %f1494;
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mov.pred %p208, %p17;
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@%p18 bra $L__BB0_23;
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ld.const.f32 %f16, [params+620];
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ld.const.u64 %rd55, [params+624];
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cvta.to.global.u64 %rd3, %rd55;
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ld.const.u64 %rd56, [params+640];
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cvta.to.global.u64 %rd57, %rd56;
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ld.const.u32 %r78, [params+632];
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and.b32 %r79, %r61, 255;
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and.b32 %r80, %r60, 255;
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mad.lo.s32 %r81, %r78, %r79, %r80;
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mul.wide.u32 %rd58, %r81, 3;
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add.s64 %rd4, %rd57, %rd58;
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ld.const.f32 %f17, [params+660];
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mul.f32 %f18, %f13, 0f3456BF95;
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mul.f32 %f19, %f14, 0f3456BF95;
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mul.f32 %f20, %f15, 0f3456BF95;
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ld.const.u64 %rd5, [params+96];
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abs.f32 %f503, %f19;
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abs.f32 %f504, %f18;
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max.f32 %f505, %f504, %f503;
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abs.f32 %f506, %f20;
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max.f32 %f507, %f505, %f506;
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$L__BB0_7:
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shl.b32 %r82, %r471, 1;
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mul.wide.s32 %rd59, %r82, 12;
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add.s64 %rd6, %rd3, %rd59;
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ld.global.f32 %f376, [%rd6];
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sub.f32 %f377, %f376, %f10;
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ld.global.f32 %f378, [%rd6+4];
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sub.f32 %f379, %f378, %f11;
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ld.global.f32 %f380, [%rd6+8];
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sub.f32 %f381, %f380, %f12;
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mul.f32 %f382, %f379, %f379;
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fma.rn.f32 %f383, %f377, %f377, %f382;
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fma.rn.f32 %f384, %f381, %f381, %f383;
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sqrt.rn.f32 %f32, %f384;
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rcp.rn.f32 %f385, %f32;
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mul.f32 %f33, %f377, %f385;
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mul.f32 %f34, %f379, %f385;
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mul.f32 %f35, %f381, %f385;
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mul.f32 %f386, %f32, %f32;
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div.rn.f32 %f36, %f16, %f386;
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ld.global.u8 %rs15, [%rd4];
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cvt.rn.f32.u16 %f387, %rs15;
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div.rn.f32 %f388, %f387, 0fC37F0000;
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fma.rn.f32 %f389, %f388, 0f3F333333, 0f3F800000;
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setp.gt.f32 %p20, %f36, %f389;
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setp.ne.s32 %p21, %r5, 0;
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and.pred %p22, %p21, %p20;
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mov.pred %p208, -1;
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@%p22 bra $L__BB0_23;
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mul.f32 %f37, %f32, %f17;
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mov.f32 %f394, 0f40800000;
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abs.f32 %f39, %f37;
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setp.lt.f32 %p23, %f39, 0f00800000;
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mul.f32 %f396, %f39, 0f4B800000;
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selp.f32 %f397, %f396, %f39, %p23;
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selp.f32 %f398, 0fC3170000, 0fC2FE0000, %p23;
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mov.b32 %r83, %f397;
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and.b32 %r84, %r83, 8388607;
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or.b32 %r85, %r84, 1065353216;
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mov.b32 %f399, %r85;
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shr.u32 %r86, %r83, 23;
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cvt.rn.f32.u32 %f400, %r86;
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add.f32 %f401, %f398, %f400;
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setp.gt.f32 %p24, %f399, 0f3FB504F3;
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mul.f32 %f402, %f399, 0f3F000000;
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add.f32 %f403, %f401, 0f3F800000;
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selp.f32 %f404, %f403, %f401, %p24;
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selp.f32 %f405, %f402, %f399, %p24;
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add.f32 %f406, %f405, 0fBF800000;
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add.f32 %f407, %f405, 0f3F800000;
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rcp.approx.ftz.f32 %f408, %f407;
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add.f32 %f409, %f406, %f406;
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mul.f32 %f410, %f409, %f408;
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mul.f32 %f411, %f410, %f410;
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mov.f32 %f412, 0f3C4CAF63;
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mov.f32 %f413, 0f3B18F0FE;
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fma.rn.f32 %f414, %f413, %f411, %f412;
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mov.f32 %f415, 0f3DAAAABD;
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fma.rn.f32 %f416, %f414, %f411, %f415;
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mul.rn.f32 %f417, %f416, %f411;
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mul.rn.f32 %f418, %f417, %f410;
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sub.f32 %f419, %f406, %f410;
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add.f32 %f420, %f419, %f419;
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neg.f32 %f421, %f410;
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fma.rn.f32 %f422, %f421, %f406, %f420;
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mul.rn.f32 %f423, %f408, %f422;
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add.f32 %f424, %f418, %f410;
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sub.f32 %f425, %f410, %f424;
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add.f32 %f426, %f418, %f425;
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add.f32 %f427, %f423, %f426;
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add.f32 %f428, %f424, %f427;
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sub.f32 %f429, %f424, %f428;
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add.f32 %f430, %f427, %f429;
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mov.f32 %f431, 0f3F317200;
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mul.rn.f32 %f432, %f404, %f431;
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mov.f32 %f433, 0f35BFBE8E;
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mul.rn.f32 %f434, %f404, %f433;
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add.f32 %f435, %f432, %f428;
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sub.f32 %f436, %f432, %f435;
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add.f32 %f437, %f428, %f436;
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add.f32 %f438, %f430, %f437;
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add.f32 %f439, %f434, %f438;
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add.f32 %f440, %f435, %f439;
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sub.f32 %f441, %f435, %f440;
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add.f32 %f442, %f439, %f441;
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mul.rn.f32 %f443, %f394, %f440;
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neg.f32 %f444, %f443;
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fma.rn.f32 %f445, %f394, %f440, %f444;
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fma.rn.f32 %f446, %f394, %f442, %f445;
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mov.f32 %f447, 0f00000000;
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fma.rn.f32 %f448, %f447, %f440, %f446;
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add.rn.f32 %f449, %f443, %f448;
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neg.f32 %f450, %f449;
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add.rn.f32 %f451, %f443, %f450;
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add.rn.f32 %f452, %f451, %f448;
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mov.b32 %r87, %f449;
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setp.eq.s32 %p25, %r87, 1118925336;
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add.s32 %r88, %r87, -1;
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mov.b32 %f453, %r88;
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add.f32 %f454, %f452, 0f37000000;
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selp.f32 %f40, %f454, %f452, %p25;
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selp.f32 %f455, %f453, %f449, %p25;
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mov.f32 %f456, 0f3FB8AA3B;
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mul.rn.f32 %f457, %f455, %f456;
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cvt.rzi.f32.f32 %f458, %f457;
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abs.f32 %f459, %f458;
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setp.gt.f32 %p26, %f459, 0f42FC0000;
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mov.b32 %r89, %f458;
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and.b32 %r90, %r89, -2147483648;
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or.b32 %r91, %r90, 1123811328;
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mov.b32 %f460, %r91;
|
|
selp.f32 %f461, %f460, %f458, %p26;
|
|
mov.f32 %f462, 0fBF317218;
|
|
fma.rn.f32 %f463, %f461, %f462, %f455;
|
|
mov.f32 %f464, 0f3102E308;
|
|
fma.rn.f32 %f465, %f461, %f464, %f463;
|
|
mul.f32 %f466, %f465, 0f3FB8AA3B;
|
|
add.f32 %f467, %f461, 0f4B40007F;
|
|
mov.b32 %r92, %f467;
|
|
shl.b32 %r93, %r92, 23;
|
|
mov.b32 %f468, %r93;
|
|
ex2.approx.ftz.f32 %f469, %f466;
|
|
mul.f32 %f41, %f469, %f468;
|
|
setp.eq.f32 %p27, %f41, 0f7F800000;
|
|
mov.f32 %f1491, 0f7F800000;
|
|
@%p27 bra $L__BB0_10;
|
|
|
|
fma.rn.f32 %f1491, %f41, %f40, %f41;
|
|
|
|
$L__BB0_10:
|
|
mov.f32 %f1476, 0f40000000;
|
|
cvt.rzi.f32.f32 %f1475, %f1476;
|
|
add.f32 %f1474, %f1475, %f1475;
|
|
mov.f32 %f1473, 0f40800000;
|
|
sub.f32 %f1472, %f1473, %f1474;
|
|
abs.f32 %f1471, %f1472;
|
|
setp.lt.f32 %p28, %f37, 0f00000000;
|
|
setp.eq.f32 %p29, %f1471, 0f3F800000;
|
|
and.pred %p1, %p28, %p29;
|
|
setp.eq.f32 %p30, %f37, 0f00000000;
|
|
@%p30 bra $L__BB0_14;
|
|
bra.uni $L__BB0_11;
|
|
|
|
$L__BB0_14:
|
|
add.f32 %f474, %f37, %f37;
|
|
selp.f32 %f1493, %f474, 0f00000000, %p29;
|
|
bra.uni $L__BB0_15;
|
|
|
|
$L__BB0_11:
|
|
mov.b32 %r94, %f1491;
|
|
xor.b32 %r95, %r94, -2147483648;
|
|
mov.b32 %f470, %r95;
|
|
selp.f32 %f1493, %f470, %f1491, %p1;
|
|
setp.geu.f32 %p31, %f37, 0f00000000;
|
|
@%p31 bra $L__BB0_15;
|
|
|
|
mov.f32 %f471, 0f40800000;
|
|
cvt.rzi.f32.f32 %f472, %f471;
|
|
setp.eq.f32 %p32, %f472, 0f40800000;
|
|
@%p32 bra $L__BB0_15;
|
|
|
|
mov.f32 %f1493, 0f7FFFFFFF;
|
|
|
|
$L__BB0_15:
|
|
add.f32 %f475, %f39, 0f40800000;
|
|
mov.b32 %r96, %f475;
|
|
setp.lt.s32 %p34, %r96, 2139095040;
|
|
@%p34 bra $L__BB0_20;
|
|
|
|
setp.gtu.f32 %p35, %f39, 0f7F800000;
|
|
@%p35 bra $L__BB0_19;
|
|
bra.uni $L__BB0_17;
|
|
|
|
$L__BB0_19:
|
|
add.f32 %f1493, %f37, 0f40800000;
|
|
bra.uni $L__BB0_20;
|
|
|
|
$L__BB0_17:
|
|
setp.neu.f32 %p36, %f39, 0f7F800000;
|
|
@%p36 bra $L__BB0_20;
|
|
|
|
selp.f32 %f1493, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_20:
|
|
shl.b32 %r468, %r471, 1;
|
|
mul.wide.s32 %rd161, %r468, 12;
|
|
add.s64 %rd160, %rd3, %rd161;
|
|
mov.f32 %f476, 0f3F800000;
|
|
sub.f32 %f477, %f476, %f1493;
|
|
setp.eq.f32 %p37, %f37, 0f3F800000;
|
|
selp.f32 %f478, 0f00000000, %f477, %p37;
|
|
cvt.sat.f32.f32 %f479, %f478;
|
|
mul.f32 %f480, %f36, %f479;
|
|
ld.global.f32 %f481, [%rd160+12];
|
|
mul.f32 %f482, %f33, %f481;
|
|
ld.global.f32 %f483, [%rd160+16];
|
|
mul.f32 %f484, %f34, %f483;
|
|
neg.f32 %f485, %f484;
|
|
sub.f32 %f486, %f485, %f482;
|
|
ld.global.f32 %f487, [%rd160+20];
|
|
mul.f32 %f488, %f35, %f487;
|
|
sub.f32 %f489, %f486, %f488;
|
|
cvt.sat.f32.f32 %f490, %f489;
|
|
mul.f32 %f50, %f480, %f490;
|
|
mul.f32 %f491, %f1478, %f34;
|
|
fma.rn.f32 %f492, %f1477, %f33, %f491;
|
|
fma.rn.f32 %f51, %f1479, %f35, %f492;
|
|
setp.leu.f32 %p38, %f50, 0f3727C5AC;
|
|
@%p38 bra $L__BB0_22;
|
|
|
|
cvt.sat.f32.f32 %f502, %f51;
|
|
mov.f32 %f508, 0f38D1B717;
|
|
max.f32 %f499, %f507, %f508;
|
|
sub.f32 %f500, %f32, %f499;
|
|
mov.f32 %f501, 0f00000000;
|
|
mov.u32 %r133, 2;
|
|
mov.u32 %r135, 1;
|
|
mov.u32 %r136, 1065353216;
|
|
mov.u32 %r167, 0;
|
|
// begin inline asm
|
|
call(%r97,%r98,%r99,%r100,%r101,%r102,%r103,%r104,%r105,%r106,%r107,%r108,%r109,%r110,%r111,%r112,%r113,%r114,%r115,%r116,%r117,%r118,%r119,%r120,%r121,%r122,%r123,%r124,%r125,%r126,%r127,%r128),_optix_trace_typed_32,(%r167,%rd5,%f13,%f14,%f15,%f33,%f34,%f35,%f499,%f500,%f501,%r135,%r167,%r135,%r133,%r135,%r135,%r136,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167,%r167);
|
|
// end inline asm
|
|
mov.b32 %f509, %r97;
|
|
mul.f32 %f510, %f50, 0f3EA2F983;
|
|
mul.f32 %f511, %f510, %f509;
|
|
fma.rn.f32 %f1504, %f502, %f511, %f1504;
|
|
add.f32 %f1503, %f1503, %f511;
|
|
fma.rn.f32 %f1502, %f34, %f511, %f1502;
|
|
fma.rn.f32 %f1501, %f35, %f511, %f1501;
|
|
fma.rn.f32 %f1500, %f33, %f511, %f1500;
|
|
mul.f32 %f512, %f33, %f34;
|
|
fma.rn.f32 %f1499, %f512, %f511, %f1499;
|
|
mul.f32 %f513, %f34, %f35;
|
|
fma.rn.f32 %f1498, %f513, %f511, %f1498;
|
|
fma.rn.f32 %f514, %f35, %f35, 0fBEAAAAAB;
|
|
fma.rn.f32 %f1497, %f514, %f511, %f1497;
|
|
mul.f32 %f515, %f33, %f35;
|
|
fma.rn.f32 %f1496, %f515, %f511, %f1496;
|
|
mul.f32 %f516, %f34, %f34;
|
|
mul.f32 %f517, %f33, %f33;
|
|
sub.f32 %f518, %f517, %f516;
|
|
fma.rn.f32 %f1495, %f518, %f511, %f1495;
|
|
add.f32 %f1494, %f1494, %f509;
|
|
|
|
$L__BB0_22:
|
|
add.s32 %r471, %r471, 1;
|
|
setp.lt.s32 %p40, %r471, %r4;
|
|
mov.pred %p208, %p17;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_23:
|
|
cvt.rn.f32.s32 %f519, %r471;
|
|
mov.f32 %f520, 0f3F800000;
|
|
max.f32 %f521, %f519, %f520;
|
|
div.rn.f32 %f1565, %f1504, %f521;
|
|
div.rn.f32 %f1555, %f1494, %f521;
|
|
div.rn.f32 %f1564, %f1503, %f521;
|
|
div.rn.f32 %f1563, %f1502, %f521;
|
|
div.rn.f32 %f1562, %f1501, %f521;
|
|
div.rn.f32 %f1561, %f1500, %f521;
|
|
div.rn.f32 %f1560, %f1499, %f521;
|
|
div.rn.f32 %f1559, %f1498, %f521;
|
|
div.rn.f32 %f1558, %f1497, %f521;
|
|
div.rn.f32 %f1557, %f1496, %f521;
|
|
div.rn.f32 %f1556, %f1495, %f521;
|
|
not.pred %p41, %p208;
|
|
@%p41 bra $L__BB0_54;
|
|
|
|
setp.lt.s32 %p42, %r5, 1;
|
|
mov.f32 %f1537, 0f00000000;
|
|
mov.f32 %f1536, %f1537;
|
|
mov.f32 %f1535, %f1537;
|
|
mov.f32 %f1534, %f1537;
|
|
mov.f32 %f1533, %f1537;
|
|
mov.f32 %f1532, %f1537;
|
|
mov.f32 %f1531, %f1537;
|
|
mov.f32 %f1530, %f1537;
|
|
mov.f32 %f1529, %f1537;
|
|
mov.f32 %f1528, %f1537;
|
|
mov.f32 %f1527, %f1537;
|
|
@%p42 bra $L__BB0_53;
|
|
|
|
cvt.rn.f32.s32 %f544, %r6;
|
|
rcp.rn.f32 %f96, %f544;
|
|
mul.f32 %f97, %f13, 0f3456BF95;
|
|
mul.f32 %f98, %f14, 0f3456BF95;
|
|
mul.f32 %f99, %f15, 0f3456BF95;
|
|
mov.u32 %r168, 0;
|
|
ld.const.u64 %rd7, [params+96];
|
|
add.s64 %rd8, %rd1, 24;
|
|
mov.u64 %rd61, __cudart_i2opi_f;
|
|
abs.f32 %f601, %f98;
|
|
abs.f32 %f602, %f97;
|
|
max.f32 %f603, %f602, %f601;
|
|
abs.f32 %f604, %f99;
|
|
max.f32 %f605, %f603, %f604;
|
|
mov.u32 %r472, %r168;
|
|
|
|
$L__BB0_26:
|
|
cvt.rn.f32.s32 %f111, %r472;
|
|
mov.u32 %r474, %r168;
|
|
|
|
$L__BB0_27:
|
|
mad.lo.s32 %r170, %r475, 1664525, 1013904223;
|
|
and.b32 %r171, %r170, 16777215;
|
|
cvt.rn.f32.u32 %f545, %r171;
|
|
fma.rn.f32 %f546, %f545, 0f33800000, %f111;
|
|
mul.f32 %f547, %f96, %f546;
|
|
mad.lo.s32 %r475, %r170, 1664525, 1013904223;
|
|
and.b32 %r172, %r475, 16777215;
|
|
cvt.rn.f32.u32 %f548, %r172;
|
|
cvt.rn.f32.s32 %f549, %r474;
|
|
fma.rn.f32 %f550, %f548, 0f33800000, %f549;
|
|
mul.f32 %f551, %f96, %f550;
|
|
fma.rn.f32 %f552, %f96, %f546, %f547;
|
|
mov.f32 %f553, 0f3F800000;
|
|
sub.f32 %f123, %f553, %f552;
|
|
mul.f32 %f124, %f123, %f123;
|
|
sub.f32 %f554, %f553, %f124;
|
|
mov.f32 %f555, 0f00000000;
|
|
max.f32 %f556, %f555, %f554;
|
|
sqrt.rn.f32 %f125, %f556;
|
|
mul.f32 %f126, %f551, 0f40C90FDB;
|
|
mul.f32 %f557, %f126, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r482, %f557;
|
|
cvt.rn.f32.s32 %f558, %r482;
|
|
mov.f32 %f559, 0fBFC90FDA;
|
|
fma.rn.f32 %f560, %f558, %f559, %f126;
|
|
mov.f32 %f561, 0fB3A22168;
|
|
fma.rn.f32 %f562, %f558, %f561, %f560;
|
|
mov.f32 %f563, 0fA7C234C5;
|
|
fma.rn.f32 %f1541, %f558, %f563, %f562;
|
|
abs.f32 %f128, %f126;
|
|
setp.ltu.f32 %p43, %f128, 0f47CE4780;
|
|
mov.u32 %r479, %r482;
|
|
mov.f32 %f1538, %f1541;
|
|
@%p43 bra $L__BB0_35;
|
|
|
|
setp.eq.f32 %p44, %f128, 0f7F800000;
|
|
@%p44 bra $L__BB0_34;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_34:
|
|
mov.f32 %f566, 0f00000000;
|
|
mul.rn.f32 %f1538, %f126, %f566;
|
|
mov.u32 %r479, 0;
|
|
bra.uni $L__BB0_35;
|
|
|
|
$L__BB0_29:
|
|
mov.b32 %r19, %f126;
|
|
bfe.u32 %r174, %r19, 23, 8;
|
|
add.s32 %r20, %r174, -128;
|
|
shl.b32 %r175, %r19, 8;
|
|
or.b32 %r21, %r175, -2147483648;
|
|
shr.u32 %r22, %r20, 5;
|
|
mov.u64 %rd164, 0;
|
|
mov.u32 %r476, 0;
|
|
mov.u64 %rd162, %rd1;
|
|
mov.u64 %rd163, %rd61;
|
|
|
|
$L__BB0_30:
|
|
.pragma "nounroll";
|
|
ld.global.nc.u32 %r176, [%rd163];
|
|
mad.wide.u32 %rd63, %r176, %r21, %rd164;
|
|
shr.u64 %rd164, %rd63, 32;
|
|
st.local.u32 [%rd162], %rd63;
|
|
add.s64 %rd163, %rd163, 4;
|
|
add.s64 %rd162, %rd162, 4;
|
|
add.s32 %r476, %r476, 1;
|
|
setp.ne.s32 %p45, %r476, 6;
|
|
@%p45 bra $L__BB0_30;
|
|
|
|
st.local.u32 [%rd8], %rd164;
|
|
mov.u32 %r177, 4;
|
|
sub.s32 %r25, %r177, %r22;
|
|
mov.u32 %r178, 6;
|
|
sub.s32 %r179, %r178, %r22;
|
|
mul.wide.s32 %rd64, %r179, 4;
|
|
add.s64 %rd65, %rd1, %rd64;
|
|
ld.local.u32 %r477, [%rd65];
|
|
ld.local.u32 %r478, [%rd65+-4];
|
|
and.b32 %r28, %r20, 31;
|
|
setp.eq.s32 %p46, %r28, 0;
|
|
@%p46 bra $L__BB0_33;
|
|
|
|
mov.u32 %r180, 32;
|
|
sub.s32 %r181, %r180, %r28;
|
|
shr.u32 %r182, %r478, %r181;
|
|
shl.b32 %r183, %r477, %r28;
|
|
add.s32 %r477, %r182, %r183;
|
|
mul.wide.s32 %rd66, %r25, 4;
|
|
add.s64 %rd67, %rd1, %rd66;
|
|
ld.local.u32 %r184, [%rd67];
|
|
shr.u32 %r185, %r184, %r181;
|
|
shl.b32 %r186, %r478, %r28;
|
|
add.s32 %r478, %r185, %r186;
|
|
|
|
$L__BB0_33:
|
|
and.b32 %r187, %r19, -2147483648;
|
|
shr.u32 %r188, %r478, 30;
|
|
shl.b32 %r189, %r477, 2;
|
|
or.b32 %r190, %r188, %r189;
|
|
shr.u32 %r191, %r190, 31;
|
|
shr.u32 %r192, %r477, 30;
|
|
add.s32 %r193, %r191, %r192;
|
|
neg.s32 %r194, %r193;
|
|
setp.eq.s32 %p47, %r187, 0;
|
|
selp.b32 %r479, %r193, %r194, %p47;
|
|
setp.ne.s32 %p48, %r191, 0;
|
|
xor.b32 %r195, %r187, -2147483648;
|
|
selp.b32 %r196, %r195, %r187, %p48;
|
|
selp.b32 %r197, -1, 0, %p48;
|
|
xor.b32 %r198, %r190, %r197;
|
|
shl.b32 %r199, %r478, 2;
|
|
xor.b32 %r200, %r199, %r197;
|
|
cvt.u64.u32 %rd68, %r198;
|
|
cvt.u64.u32 %rd69, %r200;
|
|
bfi.b64 %rd70, %rd68, %rd69, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd70;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f564, %fd2;
|
|
setp.eq.s32 %p49, %r196, 0;
|
|
neg.f32 %f565, %f564;
|
|
selp.f32 %f1538, %f564, %f565, %p49;
|
|
|
|
$L__BB0_35:
|
|
add.s32 %r35, %r479, 1;
|
|
and.b32 %r36, %r35, 1;
|
|
setp.eq.s32 %p50, %r36, 0;
|
|
selp.f32 %f132, %f1538, 0f3F800000, %p50;
|
|
mul.rn.f32 %f133, %f1538, %f1538;
|
|
mov.f32 %f1539, 0fB94D4153;
|
|
@%p50 bra $L__BB0_37;
|
|
|
|
mov.f32 %f568, 0fBAB607ED;
|
|
mov.f32 %f569, 0f37CBAC00;
|
|
fma.rn.f32 %f1539, %f569, %f133, %f568;
|
|
|
|
$L__BB0_37:
|
|
selp.f32 %f570, 0f3C0885E4, 0f3D2AAABB, %p50;
|
|
fma.rn.f32 %f571, %f1539, %f133, %f570;
|
|
selp.f32 %f572, 0fBE2AAAA8, 0fBEFFFFFF, %p50;
|
|
fma.rn.f32 %f573, %f571, %f133, %f572;
|
|
mov.f32 %f574, 0f00000000;
|
|
fma.rn.f32 %f575, %f133, %f132, %f574;
|
|
fma.rn.f32 %f1540, %f573, %f575, %f132;
|
|
and.b32 %r202, %r35, 2;
|
|
setp.eq.s32 %p52, %r202, 0;
|
|
@%p52 bra $L__BB0_39;
|
|
|
|
mov.f32 %f577, 0fBF800000;
|
|
fma.rn.f32 %f1540, %f1540, %f577, %f574;
|
|
|
|
$L__BB0_39:
|
|
@%p43 bra $L__BB0_47;
|
|
|
|
setp.eq.f32 %p54, %f128, 0f7F800000;
|
|
@%p54 bra $L__BB0_46;
|
|
bra.uni $L__BB0_41;
|
|
|
|
$L__BB0_46:
|
|
mov.f32 %f580, 0f00000000;
|
|
mul.rn.f32 %f1541, %f126, %f580;
|
|
mov.u32 %r482, 0;
|
|
bra.uni $L__BB0_47;
|
|
|
|
$L__BB0_41:
|
|
mov.b32 %r37, %f126;
|
|
bfe.u32 %r203, %r37, 23, 8;
|
|
add.s32 %r38, %r203, -128;
|
|
shl.b32 %r204, %r37, 8;
|
|
or.b32 %r39, %r204, -2147483648;
|
|
shr.u32 %r40, %r38, 5;
|
|
mov.u64 %rd165, 0;
|
|
mov.u64 %rd166, %rd165;
|
|
|
|
$L__BB0_42:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd73, %rd165, 2;
|
|
mov.u64 %rd74, __cudart_i2opi_f;
|
|
add.s64 %rd75, %rd74, %rd73;
|
|
ld.global.nc.u32 %r205, [%rd75];
|
|
mad.wide.u32 %rd76, %r205, %r39, %rd166;
|
|
shr.u64 %rd166, %rd76, 32;
|
|
add.s64 %rd77, %rd1, %rd73;
|
|
st.local.u32 [%rd77], %rd76;
|
|
cvt.u32.u64 %r206, %rd165;
|
|
add.s32 %r207, %r206, 1;
|
|
cvt.s64.s32 %rd165, %r207;
|
|
setp.ne.s32 %p55, %r207, 6;
|
|
@%p55 bra $L__BB0_42;
|
|
|
|
st.local.u32 [%rd8], %rd166;
|
|
mov.u32 %r208, 4;
|
|
sub.s32 %r41, %r208, %r40;
|
|
mov.u32 %r209, 6;
|
|
sub.s32 %r210, %r209, %r40;
|
|
mul.wide.s32 %rd78, %r210, 4;
|
|
add.s64 %rd79, %rd1, %rd78;
|
|
ld.local.u32 %r480, [%rd79];
|
|
ld.local.u32 %r481, [%rd79+-4];
|
|
and.b32 %r44, %r38, 31;
|
|
setp.eq.s32 %p56, %r44, 0;
|
|
@%p56 bra $L__BB0_45;
|
|
|
|
mov.u32 %r211, 32;
|
|
sub.s32 %r212, %r211, %r44;
|
|
shr.u32 %r213, %r481, %r212;
|
|
shl.b32 %r214, %r480, %r44;
|
|
add.s32 %r480, %r213, %r214;
|
|
mul.wide.s32 %rd80, %r41, 4;
|
|
add.s64 %rd81, %rd1, %rd80;
|
|
ld.local.u32 %r215, [%rd81];
|
|
shr.u32 %r216, %r215, %r212;
|
|
shl.b32 %r217, %r481, %r44;
|
|
add.s32 %r481, %r216, %r217;
|
|
|
|
$L__BB0_45:
|
|
and.b32 %r218, %r37, -2147483648;
|
|
shr.u32 %r219, %r481, 30;
|
|
shl.b32 %r220, %r480, 2;
|
|
or.b32 %r221, %r219, %r220;
|
|
shr.u32 %r222, %r221, 31;
|
|
shr.u32 %r223, %r480, 30;
|
|
add.s32 %r224, %r222, %r223;
|
|
neg.s32 %r225, %r224;
|
|
setp.eq.s32 %p57, %r218, 0;
|
|
selp.b32 %r482, %r224, %r225, %p57;
|
|
setp.ne.s32 %p58, %r222, 0;
|
|
xor.b32 %r226, %r218, -2147483648;
|
|
selp.b32 %r227, %r226, %r218, %p58;
|
|
selp.b32 %r228, -1, 0, %p58;
|
|
xor.b32 %r229, %r221, %r228;
|
|
shl.b32 %r230, %r481, 2;
|
|
xor.b32 %r231, %r230, %r228;
|
|
cvt.u64.u32 %rd82, %r229;
|
|
cvt.u64.u32 %rd83, %r231;
|
|
bfi.b64 %rd84, %rd82, %rd83, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd84;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f578, %fd4;
|
|
setp.eq.s32 %p59, %r227, 0;
|
|
neg.f32 %f579, %f578;
|
|
selp.f32 %f1541, %f578, %f579, %p59;
|
|
|
|
$L__BB0_47:
|
|
mul.f32 %f142, %f125, %f1540;
|
|
and.b32 %r51, %r482, 1;
|
|
setp.eq.s32 %p60, %r51, 0;
|
|
selp.f32 %f143, %f1541, 0f3F800000, %p60;
|
|
mul.rn.f32 %f144, %f1541, %f1541;
|
|
mov.f32 %f1542, 0fB94D4153;
|
|
@%p60 bra $L__BB0_49;
|
|
|
|
mov.f32 %f582, 0fBAB607ED;
|
|
mov.f32 %f583, 0f37CBAC00;
|
|
fma.rn.f32 %f1542, %f583, %f144, %f582;
|
|
|
|
$L__BB0_49:
|
|
selp.f32 %f584, 0f3C0885E4, 0f3D2AAABB, %p60;
|
|
fma.rn.f32 %f585, %f1542, %f144, %f584;
|
|
selp.f32 %f586, 0fBE2AAAA8, 0fBEFFFFFF, %p60;
|
|
fma.rn.f32 %f587, %f585, %f144, %f586;
|
|
mov.f32 %f588, 0f00000000;
|
|
fma.rn.f32 %f589, %f144, %f143, %f588;
|
|
fma.rn.f32 %f1543, %f587, %f589, %f143;
|
|
and.b32 %r233, %r482, 2;
|
|
setp.eq.s32 %p62, %r233, 0;
|
|
@%p62 bra $L__BB0_51;
|
|
|
|
mov.f32 %f591, 0fBF800000;
|
|
fma.rn.f32 %f1543, %f1543, %f591, %f588;
|
|
|
|
$L__BB0_51:
|
|
mov.f32 %f606, 0f38D1B717;
|
|
max.f32 %f598, %f605, %f606;
|
|
mul.f32 %f596, %f125, %f1543;
|
|
mov.f32 %f599, 0f6C4ECB8F;
|
|
mov.u32 %r270, 2;
|
|
mov.u32 %r272, 1;
|
|
mov.u32 %r304, 0;
|
|
// begin inline asm
|
|
call(%r234,%r235,%r236,%r237,%r238,%r239,%r240,%r241,%r242,%r243,%r244,%r245,%r246,%r247,%r248,%r249,%r250,%r251,%r252,%r253,%r254,%r255,%r256,%r257,%r258,%r259,%r260,%r261,%r262,%r263,%r264,%r265),_optix_trace_typed_32,(%r304,%rd7,%f13,%f14,%f15,%f142,%f596,%f123,%f598,%f599,%f588,%r272,%r304,%r304,%r270,%r304,%r272,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304,%r304);
|
|
// end inline asm
|
|
mov.b32 %f607, %r234;
|
|
setp.lt.f32 %p63, %f607, 0f00000000;
|
|
selp.f32 %f608, 0f00000000, %f607, %p63;
|
|
setp.geu.f32 %p64, %f607, 0f00000000;
|
|
selp.f32 %f609, 0f3F800000, 0f00000000, %p64;
|
|
add.f32 %f1537, %f1537, %f609;
|
|
add.f32 %f1528, %f1528, %f608;
|
|
fma.rn.f32 %f1529, %f596, %f608, %f1529;
|
|
fma.rn.f32 %f1530, %f123, %f608, %f1530;
|
|
fma.rn.f32 %f1531, %f142, %f608, %f1531;
|
|
mul.f32 %f610, %f142, %f596;
|
|
fma.rn.f32 %f1532, %f610, %f608, %f1532;
|
|
mul.f32 %f611, %f123, %f596;
|
|
fma.rn.f32 %f1533, %f611, %f608, %f1533;
|
|
add.f32 %f612, %f124, 0fBEAAAAAB;
|
|
fma.rn.f32 %f1534, %f612, %f608, %f1534;
|
|
mul.f32 %f613, %f123, %f142;
|
|
fma.rn.f32 %f1535, %f613, %f608, %f1535;
|
|
mul.f32 %f614, %f596, %f596;
|
|
mul.f32 %f615, %f142, %f142;
|
|
sub.f32 %f616, %f615, %f614;
|
|
fma.rn.f32 %f1536, %f616, %f608, %f1536;
|
|
mul.f32 %f617, %f1478, %f596;
|
|
fma.rn.f32 %f618, %f1477, %f142, %f617;
|
|
fma.rn.f32 %f619, %f1479, %f123, %f618;
|
|
cvt.sat.f32.f32 %f620, %f619;
|
|
fma.rn.f32 %f1527, %f620, %f608, %f1527;
|
|
add.s32 %r474, %r474, 1;
|
|
setp.lt.s32 %p65, %r474, %r6;
|
|
@%p65 bra $L__BB0_27;
|
|
|
|
add.s32 %r472, %r472, 1;
|
|
setp.lt.s32 %p66, %r472, %r6;
|
|
@%p66 bra $L__BB0_26;
|
|
|
|
$L__BB0_53:
|
|
mul.lo.s32 %r305, %r6, %r6;
|
|
cvt.rn.f32.s32 %f621, %r305;
|
|
div.rn.f32 %f622, %f1527, %f621;
|
|
div.rn.f32 %f1555, %f1537, %f621;
|
|
div.rn.f32 %f1564, %f1528, %f621;
|
|
div.rn.f32 %f1563, %f1529, %f621;
|
|
div.rn.f32 %f1562, %f1530, %f621;
|
|
div.rn.f32 %f1561, %f1531, %f621;
|
|
div.rn.f32 %f1560, %f1532, %f621;
|
|
div.rn.f32 %f1559, %f1533, %f621;
|
|
div.rn.f32 %f1558, %f1534, %f621;
|
|
div.rn.f32 %f1557, %f1535, %f621;
|
|
div.rn.f32 %f1556, %f1536, %f621;
|
|
add.f32 %f1565, %f622, %f622;
|
|
|
|
$L__BB0_54:
|
|
ld.const.u32 %r469, [params+616];
|
|
setp.lt.s32 %p67, %r469, 0;
|
|
selp.f32 %f194, %f1565, %f1555, %p67;
|
|
ld.const.u32 %r54, [params+104];
|
|
and.b32 %r306, %r54, 8;
|
|
setp.eq.s32 %p68, %r306, 0;
|
|
@%p68 bra $L__BB0_68;
|
|
|
|
ld.const.u64 %rd86, [params+192];
|
|
cvta.to.global.u64 %rd19, %rd86;
|
|
ld.const.u32 %r307, [params+184];
|
|
mad.lo.s32 %r308, %r307, %r8, %r7;
|
|
cvt.u64.u32 %rd20, %r308;
|
|
mov.f32 %f624, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f625, %f624;
|
|
add.f32 %f626, %f625, %f625;
|
|
mov.f32 %f627, 0f3EE8BA2E;
|
|
sub.f32 %f628, %f627, %f626;
|
|
abs.f32 %f195, %f628;
|
|
abs.f32 %f196, %f194;
|
|
setp.lt.f32 %p69, %f196, 0f00800000;
|
|
mul.f32 %f629, %f196, 0f4B800000;
|
|
selp.f32 %f630, %f629, %f196, %p69;
|
|
selp.f32 %f631, 0fC3170000, 0fC2FE0000, %p69;
|
|
mov.b32 %r309, %f630;
|
|
and.b32 %r310, %r309, 8388607;
|
|
or.b32 %r311, %r310, 1065353216;
|
|
mov.b32 %f632, %r311;
|
|
shr.u32 %r312, %r309, 23;
|
|
cvt.rn.f32.u32 %f633, %r312;
|
|
add.f32 %f634, %f631, %f633;
|
|
setp.gt.f32 %p70, %f632, 0f3FB504F3;
|
|
mul.f32 %f635, %f632, 0f3F000000;
|
|
add.f32 %f636, %f634, 0f3F800000;
|
|
selp.f32 %f637, %f636, %f634, %p70;
|
|
selp.f32 %f638, %f635, %f632, %p70;
|
|
add.f32 %f639, %f638, 0fBF800000;
|
|
add.f32 %f640, %f638, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f641, %f640;
|
|
add.f32 %f642, %f639, %f639;
|
|
mul.f32 %f643, %f642, %f641;
|
|
mul.f32 %f644, %f643, %f643;
|
|
mov.f32 %f645, 0f3C4CAF63;
|
|
mov.f32 %f646, 0f3B18F0FE;
|
|
fma.rn.f32 %f647, %f646, %f644, %f645;
|
|
mov.f32 %f648, 0f3DAAAABD;
|
|
fma.rn.f32 %f649, %f647, %f644, %f648;
|
|
mul.rn.f32 %f650, %f649, %f644;
|
|
mul.rn.f32 %f651, %f650, %f643;
|
|
sub.f32 %f652, %f639, %f643;
|
|
add.f32 %f653, %f652, %f652;
|
|
neg.f32 %f654, %f643;
|
|
fma.rn.f32 %f655, %f654, %f639, %f653;
|
|
mul.rn.f32 %f656, %f641, %f655;
|
|
add.f32 %f657, %f651, %f643;
|
|
sub.f32 %f658, %f643, %f657;
|
|
add.f32 %f659, %f651, %f658;
|
|
add.f32 %f660, %f656, %f659;
|
|
add.f32 %f661, %f657, %f660;
|
|
sub.f32 %f662, %f657, %f661;
|
|
add.f32 %f663, %f660, %f662;
|
|
mov.f32 %f664, 0f3F317200;
|
|
mul.rn.f32 %f665, %f637, %f664;
|
|
mov.f32 %f666, 0f35BFBE8E;
|
|
mul.rn.f32 %f667, %f637, %f666;
|
|
add.f32 %f668, %f665, %f661;
|
|
sub.f32 %f669, %f665, %f668;
|
|
add.f32 %f670, %f661, %f669;
|
|
add.f32 %f671, %f663, %f670;
|
|
add.f32 %f672, %f667, %f671;
|
|
add.f32 %f673, %f668, %f672;
|
|
sub.f32 %f674, %f668, %f673;
|
|
add.f32 %f675, %f672, %f674;
|
|
mul.rn.f32 %f676, %f627, %f673;
|
|
neg.f32 %f677, %f676;
|
|
fma.rn.f32 %f678, %f627, %f673, %f677;
|
|
fma.rn.f32 %f679, %f627, %f675, %f678;
|
|
mov.f32 %f680, 0f00000000;
|
|
fma.rn.f32 %f681, %f680, %f673, %f679;
|
|
add.rn.f32 %f682, %f676, %f681;
|
|
neg.f32 %f683, %f682;
|
|
add.rn.f32 %f684, %f676, %f683;
|
|
add.rn.f32 %f685, %f684, %f681;
|
|
mov.b32 %r313, %f682;
|
|
setp.eq.s32 %p71, %r313, 1118925336;
|
|
add.s32 %r314, %r313, -1;
|
|
mov.b32 %f686, %r314;
|
|
add.f32 %f687, %f685, 0f37000000;
|
|
selp.f32 %f197, %f687, %f685, %p71;
|
|
selp.f32 %f688, %f686, %f682, %p71;
|
|
mov.f32 %f689, 0f3FB8AA3B;
|
|
mul.rn.f32 %f690, %f688, %f689;
|
|
cvt.rzi.f32.f32 %f691, %f690;
|
|
abs.f32 %f692, %f691;
|
|
setp.gt.f32 %p72, %f692, 0f42FC0000;
|
|
mov.b32 %r315, %f691;
|
|
and.b32 %r316, %r315, -2147483648;
|
|
or.b32 %r317, %r316, 1123811328;
|
|
mov.b32 %f693, %r317;
|
|
selp.f32 %f694, %f693, %f691, %p72;
|
|
mov.f32 %f695, 0fBF317218;
|
|
fma.rn.f32 %f696, %f694, %f695, %f688;
|
|
mov.f32 %f697, 0f3102E308;
|
|
fma.rn.f32 %f698, %f694, %f697, %f696;
|
|
mul.f32 %f699, %f698, 0f3FB8AA3B;
|
|
add.f32 %f700, %f694, 0f4B40007F;
|
|
mov.b32 %r318, %f700;
|
|
shl.b32 %r319, %r318, 23;
|
|
mov.b32 %f701, %r319;
|
|
ex2.approx.ftz.f32 %f702, %f699;
|
|
mul.f32 %f198, %f702, %f701;
|
|
setp.eq.f32 %p73, %f198, 0f7F800000;
|
|
mov.f32 %f1566, 0f7F800000;
|
|
@%p73 bra $L__BB0_57;
|
|
|
|
fma.rn.f32 %f1566, %f198, %f197, %f198;
|
|
|
|
$L__BB0_57:
|
|
setp.lt.f32 %p74, %f194, 0f00000000;
|
|
setp.eq.f32 %p75, %f195, 0f3F800000;
|
|
and.pred %p3, %p74, %p75;
|
|
setp.eq.f32 %p76, %f194, 0f00000000;
|
|
@%p76 bra $L__BB0_61;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_61:
|
|
add.f32 %f707, %f194, %f194;
|
|
selp.f32 %f1568, %f707, 0f00000000, %p75;
|
|
bra.uni $L__BB0_62;
|
|
|
|
$L__BB0_180:
|
|
mov.f32 %f1389, 0f00000000;
|
|
mov.u32 %r484, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs188, %f1389;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs187, %f1389;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs186, %f1389;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs189, 0;
|
|
st.global.v4.u16 [%rd33], {%rs186, %rs187, %rs188, %rs189};
|
|
|
|
$L__BB0_181:
|
|
ld.const.u64 %rd133, [params+256];
|
|
cvta.to.global.u64 %rd134, %rd133;
|
|
ld.const.u32 %r450, [params+248];
|
|
mad.lo.s32 %r451, %r450, %r8, %r7;
|
|
mul.wide.u32 %rd135, %r451, 8;
|
|
add.s64 %rd34, %rd134, %rd135;
|
|
setp.eq.s32 %p199, %r484, 0;
|
|
@%p199 bra $L__BB0_183;
|
|
|
|
ld.global.v4.u16 {%rs196, %rs197, %rs198, %rs199}, [%rd34];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1390, %rs196;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1391, %rs197;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1392, %rs198;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1393, %f1390, 0f00000000;
|
|
add.f32 %f1394, %f1391, 0f00000000;
|
|
add.f32 %f1395, %f1392, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs195, %f1395;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs194, %f1394;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs193, %f1393;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs200, 0;
|
|
st.global.v4.u16 [%rd34], {%rs193, %rs194, %rs195, %rs200};
|
|
bra.uni $L__BB0_184;
|
|
|
|
$L__BB0_183:
|
|
mov.f32 %f1398, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs203, %f1398;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs202, %f1398;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs201, %f1398;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs204, 0;
|
|
st.global.v4.u16 [%rd34], {%rs201, %rs202, %rs203, %rs204};
|
|
|
|
$L__BB0_184:
|
|
ld.const.u64 %rd136, [params+272];
|
|
cvta.to.global.u64 %rd137, %rd136;
|
|
ld.const.u32 %r452, [params+264];
|
|
mad.lo.s32 %r453, %r452, %r8, %r7;
|
|
mul.wide.u32 %rd138, %r453, 8;
|
|
add.s64 %rd35, %rd137, %rd138;
|
|
@%p199 bra $L__BB0_186;
|
|
|
|
ld.global.v4.u16 {%rs211, %rs212, %rs213, %rs214}, [%rd35];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1399, %rs211;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1400, %rs212;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1401, %rs213;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1402, %f1399, 0f00000000;
|
|
add.f32 %f1403, %f1400, 0f00000000;
|
|
add.f32 %f1404, %f1401, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs210, %f1404;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs209, %f1403;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs208, %f1402;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs215, 0;
|
|
st.global.v4.u16 [%rd35], {%rs208, %rs209, %rs210, %rs215};
|
|
bra.uni $L__BB0_187;
|
|
|
|
$L__BB0_186:
|
|
mov.f32 %f1407, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs218, %f1407;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs217, %f1407;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs216, %f1407;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs219, 0;
|
|
st.global.v4.u16 [%rd35], {%rs216, %rs217, %rs218, %rs219};
|
|
|
|
$L__BB0_187:
|
|
ld.const.u64 %rd139, [params+288];
|
|
cvta.to.global.u64 %rd140, %rd139;
|
|
ld.const.u32 %r454, [params+280];
|
|
mad.lo.s32 %r455, %r454, %r8, %r7;
|
|
mul.wide.u32 %rd141, %r455, 8;
|
|
add.s64 %rd36, %rd140, %rd141;
|
|
@%p199 bra $L__BB0_189;
|
|
|
|
ld.global.v4.u16 {%rs226, %rs227, %rs228, %rs229}, [%rd36];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1408, %rs226;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1409, %rs227;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1410, %rs228;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1411, %f1408, 0f00000000;
|
|
add.f32 %f1412, %f1409, 0f00000000;
|
|
add.f32 %f1413, %f1410, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs225, %f1413;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs224, %f1412;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs223, %f1411;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs230, 0;
|
|
st.global.v4.u16 [%rd36], {%rs223, %rs224, %rs225, %rs230};
|
|
bra.uni $L__BB0_190;
|
|
|
|
$L__BB0_189:
|
|
mov.f32 %f1416, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs233, %f1416;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs232, %f1416;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs231, %f1416;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs234, 0;
|
|
st.global.v4.u16 [%rd36], {%rs231, %rs232, %rs233, %rs234};
|
|
|
|
$L__BB0_190:
|
|
ld.const.u64 %rd142, [params+304];
|
|
cvta.to.global.u64 %rd143, %rd142;
|
|
ld.const.u32 %r456, [params+296];
|
|
mad.lo.s32 %r457, %r456, %r8, %r7;
|
|
mul.wide.u32 %rd144, %r457, 8;
|
|
add.s64 %rd37, %rd143, %rd144;
|
|
@%p199 bra $L__BB0_192;
|
|
|
|
ld.global.v4.u16 {%rs241, %rs242, %rs243, %rs244}, [%rd37];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1417, %rs241;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1418, %rs242;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1419, %rs243;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1420, %f1417, 0f00000000;
|
|
add.f32 %f1421, %f1418, 0f00000000;
|
|
add.f32 %f1422, %f1419, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs240, %f1422;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs239, %f1421;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs238, %f1420;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs245, 0;
|
|
st.global.v4.u16 [%rd37], {%rs238, %rs239, %rs240, %rs245};
|
|
bra.uni $L__BB0_193;
|
|
|
|
$L__BB0_192:
|
|
mov.f32 %f1425, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs248, %f1425;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs247, %f1425;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs246, %f1425;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs249, 0;
|
|
st.global.v4.u16 [%rd37], {%rs246, %rs247, %rs248, %rs249};
|
|
|
|
$L__BB0_193:
|
|
ld.const.u64 %rd145, [params+320];
|
|
cvta.to.global.u64 %rd146, %rd145;
|
|
ld.const.u32 %r458, [params+312];
|
|
mad.lo.s32 %r459, %r458, %r8, %r7;
|
|
mul.wide.u32 %rd147, %r459, 8;
|
|
add.s64 %rd38, %rd146, %rd147;
|
|
@%p199 bra $L__BB0_195;
|
|
|
|
ld.global.v4.u16 {%rs256, %rs257, %rs258, %rs259}, [%rd38];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1426, %rs256;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1427, %rs257;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1428, %rs258;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1429, %f1426, 0f00000000;
|
|
add.f32 %f1430, %f1427, 0f00000000;
|
|
add.f32 %f1431, %f1428, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs255, %f1431;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs254, %f1430;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs253, %f1429;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs260, 0;
|
|
st.global.v4.u16 [%rd38], {%rs253, %rs254, %rs255, %rs260};
|
|
bra.uni $L__BB0_196;
|
|
|
|
$L__BB0_195:
|
|
mov.f32 %f1434, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs263, %f1434;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs262, %f1434;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs261, %f1434;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs264, 0;
|
|
st.global.v4.u16 [%rd38], {%rs261, %rs262, %rs263, %rs264};
|
|
|
|
$L__BB0_196:
|
|
ld.const.u64 %rd148, [params+336];
|
|
cvta.to.global.u64 %rd149, %rd148;
|
|
ld.const.u32 %r460, [params+328];
|
|
mad.lo.s32 %r461, %r460, %r8, %r7;
|
|
mul.wide.u32 %rd150, %r461, 8;
|
|
add.s64 %rd39, %rd149, %rd150;
|
|
@%p199 bra $L__BB0_198;
|
|
|
|
ld.global.v4.u16 {%rs271, %rs272, %rs273, %rs274}, [%rd39];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1435, %rs271;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1436, %rs272;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1437, %rs273;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1438, %f1435, 0f00000000;
|
|
add.f32 %f1439, %f1436, 0f00000000;
|
|
add.f32 %f1440, %f1437, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs270, %f1440;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs269, %f1439;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs268, %f1438;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs275, 0;
|
|
st.global.v4.u16 [%rd39], {%rs268, %rs269, %rs270, %rs275};
|
|
bra.uni $L__BB0_199;
|
|
|
|
$L__BB0_198:
|
|
mov.f32 %f1443, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs278, %f1443;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs277, %f1443;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs276, %f1443;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs279, 0;
|
|
st.global.v4.u16 [%rd39], {%rs276, %rs277, %rs278, %rs279};
|
|
|
|
$L__BB0_199:
|
|
ld.const.u64 %rd151, [params+352];
|
|
cvta.to.global.u64 %rd152, %rd151;
|
|
ld.const.u32 %r462, [params+344];
|
|
mad.lo.s32 %r463, %r462, %r8, %r7;
|
|
mul.wide.u32 %rd153, %r463, 8;
|
|
add.s64 %rd40, %rd152, %rd153;
|
|
@%p199 bra $L__BB0_201;
|
|
|
|
ld.global.v4.u16 {%rs286, %rs287, %rs288, %rs289}, [%rd40];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1444, %rs286;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1445, %rs287;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1446, %rs288;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1447, %f1444, 0f00000000;
|
|
add.f32 %f1448, %f1445, 0f00000000;
|
|
add.f32 %f1449, %f1446, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs285, %f1449;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs284, %f1448;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs283, %f1447;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs290, 0;
|
|
st.global.v4.u16 [%rd40], {%rs283, %rs284, %rs285, %rs290};
|
|
bra.uni $L__BB0_202;
|
|
|
|
$L__BB0_201:
|
|
mov.f32 %f1452, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs293, %f1452;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs292, %f1452;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs291, %f1452;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs294, 0;
|
|
st.global.v4.u16 [%rd40], {%rs291, %rs292, %rs293, %rs294};
|
|
|
|
$L__BB0_202:
|
|
ld.const.u64 %rd154, [params+368];
|
|
cvta.to.global.u64 %rd155, %rd154;
|
|
ld.const.u32 %r464, [params+360];
|
|
mad.lo.s32 %r465, %r464, %r8, %r7;
|
|
mul.wide.u32 %rd156, %r465, 8;
|
|
add.s64 %rd41, %rd155, %rd156;
|
|
@%p199 bra $L__BB0_204;
|
|
|
|
ld.global.v4.u16 {%rs301, %rs302, %rs303, %rs304}, [%rd41];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1453, %rs301;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1454, %rs302;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1455, %rs303;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1456, %f1453, 0f00000000;
|
|
add.f32 %f1457, %f1454, 0f00000000;
|
|
add.f32 %f1458, %f1455, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs300, %f1458;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs299, %f1457;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs298, %f1456;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs305, 0;
|
|
st.global.v4.u16 [%rd41], {%rs298, %rs299, %rs300, %rs305};
|
|
bra.uni $L__BB0_205;
|
|
|
|
$L__BB0_204:
|
|
mov.f32 %f1461, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs308, %f1461;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs307, %f1461;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs306, %f1461;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs309, 0;
|
|
st.global.v4.u16 [%rd41], {%rs306, %rs307, %rs308, %rs309};
|
|
|
|
$L__BB0_205:
|
|
ld.const.u64 %rd157, [params+384];
|
|
cvta.to.global.u64 %rd158, %rd157;
|
|
ld.const.u32 %r466, [params+376];
|
|
mad.lo.s32 %r467, %r466, %r8, %r7;
|
|
mul.wide.u32 %rd159, %r467, 8;
|
|
add.s64 %rd42, %rd158, %rd159;
|
|
@%p199 bra $L__BB0_207;
|
|
|
|
ld.global.v4.u16 {%rs316, %rs317, %rs318, %rs319}, [%rd42];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1462, %rs316;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1463, %rs317;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1464, %rs318;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1465, %f1462, 0f00000000;
|
|
add.f32 %f1466, %f1463, 0f00000000;
|
|
add.f32 %f1467, %f1464, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs315, %f1467;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs314, %f1466;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs313, %f1465;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs320, 0;
|
|
st.global.v4.u16 [%rd42], {%rs313, %rs314, %rs315, %rs320};
|
|
bra.uni $L__BB0_208;
|
|
|
|
$L__BB0_207:
|
|
mov.f32 %f1470, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs323, %f1470;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs322, %f1470;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs321, %f1470;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs324, 0;
|
|
st.global.v4.u16 [%rd42], {%rs321, %rs322, %rs323, %rs324};
|
|
bra.uni $L__BB0_208;
|
|
|
|
$L__BB0_58:
|
|
mov.b32 %r320, %f1566;
|
|
xor.b32 %r321, %r320, -2147483648;
|
|
mov.b32 %f703, %r321;
|
|
selp.f32 %f1568, %f703, %f1566, %p3;
|
|
setp.geu.f32 %p77, %f194, 0f00000000;
|
|
@%p77 bra $L__BB0_62;
|
|
|
|
mov.f32 %f704, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f705, %f704;
|
|
setp.eq.f32 %p78, %f705, 0f3EE8BA2E;
|
|
@%p78 bra $L__BB0_62;
|
|
|
|
mov.f32 %f1568, 0f7FFFFFFF;
|
|
|
|
$L__BB0_62:
|
|
add.f32 %f708, %f196, 0f3EE8BA2E;
|
|
mov.b32 %r322, %f708;
|
|
setp.lt.s32 %p80, %r322, 2139095040;
|
|
@%p80 bra $L__BB0_67;
|
|
|
|
setp.gtu.f32 %p81, %f196, 0f7F800000;
|
|
@%p81 bra $L__BB0_66;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_66:
|
|
add.f32 %f1568, %f194, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_67;
|
|
|
|
$L__BB0_64:
|
|
setp.neu.f32 %p82, %f196, 0f7F800000;
|
|
@%p82 bra $L__BB0_67;
|
|
|
|
selp.f32 %f1568, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_67:
|
|
mul.f32 %f709, %f1568, 0f437F0000;
|
|
setp.eq.f32 %p83, %f194, 0f3F800000;
|
|
selp.f32 %f710, 0f437F0000, %f709, %p83;
|
|
cvt.rzi.u32.f32 %r323, %f710;
|
|
shl.b64 %rd87, %rd20, 1;
|
|
add.s64 %rd88, %rd19, %rd87;
|
|
cvt.u16.u32 %rs16, %r323;
|
|
mov.u16 %rs17, 255;
|
|
st.global.v2.u8 [%rd88], {%rs16, %rs17};
|
|
|
|
$L__BB0_68:
|
|
ld.const.v2.f32 {%f711, %f712}, [params+648];
|
|
mul.f32 %f209, %f1565, %f711;
|
|
mul.f32 %f210, %f1565, %f712;
|
|
ld.const.f32 %f211, [params+656];
|
|
mul.f32 %f212, %f1565, %f211;
|
|
and.b32 %r324, %r54, 1;
|
|
setp.eq.b32 %p84, %r324, 1;
|
|
mov.pred %p85, 0;
|
|
xor.pred %p86, %p84, %p85;
|
|
not.pred %p87, %p86;
|
|
@%p87 bra $L__BB0_142;
|
|
|
|
mov.f32 %f714, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f715, %f714;
|
|
add.f32 %f716, %f715, %f715;
|
|
mov.f32 %f717, 0f3EE66666;
|
|
sub.f32 %f718, %f717, %f716;
|
|
abs.f32 %f213, %f718;
|
|
abs.f32 %f214, %f209;
|
|
setp.lt.f32 %p88, %f214, 0f00800000;
|
|
mul.f32 %f719, %f214, 0f4B800000;
|
|
selp.f32 %f720, %f719, %f214, %p88;
|
|
selp.f32 %f721, 0fC3170000, 0fC2FE0000, %p88;
|
|
mov.b32 %r325, %f720;
|
|
and.b32 %r326, %r325, 8388607;
|
|
or.b32 %r327, %r326, 1065353216;
|
|
mov.b32 %f722, %r327;
|
|
shr.u32 %r328, %r325, 23;
|
|
cvt.rn.f32.u32 %f723, %r328;
|
|
add.f32 %f724, %f721, %f723;
|
|
setp.gt.f32 %p89, %f722, 0f3FB504F3;
|
|
mul.f32 %f725, %f722, 0f3F000000;
|
|
add.f32 %f726, %f724, 0f3F800000;
|
|
selp.f32 %f727, %f726, %f724, %p89;
|
|
selp.f32 %f728, %f725, %f722, %p89;
|
|
add.f32 %f729, %f728, 0fBF800000;
|
|
add.f32 %f730, %f728, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f731, %f730;
|
|
add.f32 %f732, %f729, %f729;
|
|
mul.f32 %f733, %f732, %f731;
|
|
mul.f32 %f734, %f733, %f733;
|
|
mov.f32 %f735, 0f3C4CAF63;
|
|
mov.f32 %f736, 0f3B18F0FE;
|
|
fma.rn.f32 %f737, %f736, %f734, %f735;
|
|
mov.f32 %f738, 0f3DAAAABD;
|
|
fma.rn.f32 %f739, %f737, %f734, %f738;
|
|
mul.rn.f32 %f740, %f739, %f734;
|
|
mul.rn.f32 %f741, %f740, %f733;
|
|
sub.f32 %f742, %f729, %f733;
|
|
add.f32 %f743, %f742, %f742;
|
|
neg.f32 %f744, %f733;
|
|
fma.rn.f32 %f745, %f744, %f729, %f743;
|
|
mul.rn.f32 %f746, %f731, %f745;
|
|
add.f32 %f747, %f741, %f733;
|
|
sub.f32 %f748, %f733, %f747;
|
|
add.f32 %f749, %f741, %f748;
|
|
add.f32 %f750, %f746, %f749;
|
|
add.f32 %f751, %f747, %f750;
|
|
sub.f32 %f752, %f747, %f751;
|
|
add.f32 %f753, %f750, %f752;
|
|
mov.f32 %f754, 0f3F317200;
|
|
mul.rn.f32 %f755, %f727, %f754;
|
|
mov.f32 %f756, 0f35BFBE8E;
|
|
mul.rn.f32 %f757, %f727, %f756;
|
|
add.f32 %f758, %f755, %f751;
|
|
sub.f32 %f759, %f755, %f758;
|
|
add.f32 %f760, %f751, %f759;
|
|
add.f32 %f761, %f753, %f760;
|
|
add.f32 %f762, %f757, %f761;
|
|
add.f32 %f763, %f758, %f762;
|
|
sub.f32 %f764, %f758, %f763;
|
|
add.f32 %f765, %f762, %f764;
|
|
mul.rn.f32 %f766, %f717, %f763;
|
|
neg.f32 %f767, %f766;
|
|
fma.rn.f32 %f768, %f717, %f763, %f767;
|
|
fma.rn.f32 %f769, %f717, %f765, %f768;
|
|
mov.f32 %f770, 0f00000000;
|
|
fma.rn.f32 %f771, %f770, %f763, %f769;
|
|
add.rn.f32 %f772, %f766, %f771;
|
|
neg.f32 %f773, %f772;
|
|
add.rn.f32 %f774, %f766, %f773;
|
|
add.rn.f32 %f775, %f774, %f771;
|
|
mov.b32 %r329, %f772;
|
|
setp.eq.s32 %p90, %r329, 1118925336;
|
|
add.s32 %r330, %r329, -1;
|
|
mov.b32 %f776, %r330;
|
|
add.f32 %f777, %f775, 0f37000000;
|
|
selp.f32 %f215, %f777, %f775, %p90;
|
|
selp.f32 %f778, %f776, %f772, %p90;
|
|
mov.f32 %f779, 0f3FB8AA3B;
|
|
mul.rn.f32 %f780, %f778, %f779;
|
|
cvt.rzi.f32.f32 %f781, %f780;
|
|
abs.f32 %f782, %f781;
|
|
setp.gt.f32 %p91, %f782, 0f42FC0000;
|
|
mov.b32 %r331, %f781;
|
|
and.b32 %r332, %r331, -2147483648;
|
|
or.b32 %r333, %r332, 1123811328;
|
|
mov.b32 %f783, %r333;
|
|
selp.f32 %f784, %f783, %f781, %p91;
|
|
mov.f32 %f785, 0fBF317218;
|
|
fma.rn.f32 %f786, %f784, %f785, %f778;
|
|
mov.f32 %f787, 0f3102E308;
|
|
fma.rn.f32 %f788, %f784, %f787, %f786;
|
|
mul.f32 %f789, %f788, 0f3FB8AA3B;
|
|
add.f32 %f790, %f784, 0f4B40007F;
|
|
mov.b32 %r334, %f790;
|
|
shl.b32 %r335, %r334, 23;
|
|
mov.b32 %f791, %r335;
|
|
ex2.approx.ftz.f32 %f792, %f789;
|
|
mul.f32 %f216, %f792, %f791;
|
|
setp.eq.f32 %p92, %f216, 0f7F800000;
|
|
mov.f32 %f1569, 0f7F800000;
|
|
@%p92 bra $L__BB0_71;
|
|
|
|
fma.rn.f32 %f1569, %f216, %f215, %f216;
|
|
|
|
$L__BB0_71:
|
|
setp.lt.f32 %p93, %f209, 0f00000000;
|
|
setp.eq.f32 %p94, %f213, 0f3F800000;
|
|
and.pred %p4, %p93, %p94;
|
|
setp.eq.f32 %p95, %f209, 0f00000000;
|
|
@%p95 bra $L__BB0_75;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_75:
|
|
add.f32 %f797, %f209, %f209;
|
|
selp.f32 %f1571, %f797, 0f00000000, %p94;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_72:
|
|
mov.b32 %r336, %f1569;
|
|
xor.b32 %r337, %r336, -2147483648;
|
|
mov.b32 %f793, %r337;
|
|
selp.f32 %f1571, %f793, %f1569, %p4;
|
|
setp.geu.f32 %p96, %f209, 0f00000000;
|
|
@%p96 bra $L__BB0_76;
|
|
|
|
mov.f32 %f794, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f795, %f794;
|
|
setp.eq.f32 %p97, %f795, 0f3EE66666;
|
|
@%p97 bra $L__BB0_76;
|
|
|
|
mov.f32 %f1571, 0f7FFFFFFF;
|
|
|
|
$L__BB0_76:
|
|
add.f32 %f798, %f214, 0f3EE66666;
|
|
mov.b32 %r338, %f798;
|
|
setp.lt.s32 %p99, %r338, 2139095040;
|
|
@%p99 bra $L__BB0_81;
|
|
|
|
setp.gtu.f32 %p100, %f214, 0f7F800000;
|
|
@%p100 bra $L__BB0_80;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f1571, %f209, 0f3EE66666;
|
|
bra.uni $L__BB0_81;
|
|
|
|
$L__BB0_78:
|
|
setp.neu.f32 %p101, %f214, 0f7F800000;
|
|
@%p101 bra $L__BB0_81;
|
|
|
|
selp.f32 %f1571, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_81:
|
|
setp.eq.f32 %p102, %f209, 0f3F800000;
|
|
selp.f32 %f225, 0f3F800000, %f1571, %p102;
|
|
abs.f32 %f226, %f210;
|
|
setp.lt.f32 %p103, %f226, 0f00800000;
|
|
mul.f32 %f800, %f226, 0f4B800000;
|
|
selp.f32 %f801, %f800, %f226, %p103;
|
|
selp.f32 %f802, 0fC3170000, 0fC2FE0000, %p103;
|
|
mov.b32 %r339, %f801;
|
|
and.b32 %r340, %r339, 8388607;
|
|
or.b32 %r341, %r340, 1065353216;
|
|
mov.b32 %f803, %r341;
|
|
shr.u32 %r342, %r339, 23;
|
|
cvt.rn.f32.u32 %f804, %r342;
|
|
add.f32 %f805, %f802, %f804;
|
|
setp.gt.f32 %p104, %f803, 0f3FB504F3;
|
|
mul.f32 %f806, %f803, 0f3F000000;
|
|
add.f32 %f807, %f805, 0f3F800000;
|
|
selp.f32 %f808, %f807, %f805, %p104;
|
|
selp.f32 %f809, %f806, %f803, %p104;
|
|
add.f32 %f810, %f809, 0fBF800000;
|
|
add.f32 %f811, %f809, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f812, %f811;
|
|
add.f32 %f813, %f810, %f810;
|
|
mul.f32 %f814, %f813, %f812;
|
|
mul.f32 %f815, %f814, %f814;
|
|
mov.f32 %f816, 0f3C4CAF63;
|
|
mov.f32 %f817, 0f3B18F0FE;
|
|
fma.rn.f32 %f818, %f817, %f815, %f816;
|
|
mov.f32 %f819, 0f3DAAAABD;
|
|
fma.rn.f32 %f820, %f818, %f815, %f819;
|
|
mul.rn.f32 %f821, %f820, %f815;
|
|
mul.rn.f32 %f822, %f821, %f814;
|
|
sub.f32 %f823, %f810, %f814;
|
|
add.f32 %f824, %f823, %f823;
|
|
neg.f32 %f825, %f814;
|
|
fma.rn.f32 %f826, %f825, %f810, %f824;
|
|
mul.rn.f32 %f827, %f812, %f826;
|
|
add.f32 %f828, %f822, %f814;
|
|
sub.f32 %f829, %f814, %f828;
|
|
add.f32 %f830, %f822, %f829;
|
|
add.f32 %f831, %f827, %f830;
|
|
add.f32 %f832, %f828, %f831;
|
|
sub.f32 %f833, %f828, %f832;
|
|
add.f32 %f834, %f831, %f833;
|
|
mov.f32 %f835, 0f3F317200;
|
|
mul.rn.f32 %f836, %f808, %f835;
|
|
mov.f32 %f837, 0f35BFBE8E;
|
|
mul.rn.f32 %f838, %f808, %f837;
|
|
add.f32 %f839, %f836, %f832;
|
|
sub.f32 %f840, %f836, %f839;
|
|
add.f32 %f841, %f832, %f840;
|
|
add.f32 %f842, %f834, %f841;
|
|
add.f32 %f843, %f838, %f842;
|
|
add.f32 %f844, %f839, %f843;
|
|
sub.f32 %f845, %f839, %f844;
|
|
add.f32 %f846, %f843, %f845;
|
|
mov.f32 %f847, 0f3EE66666;
|
|
mul.rn.f32 %f848, %f847, %f844;
|
|
neg.f32 %f849, %f848;
|
|
fma.rn.f32 %f850, %f847, %f844, %f849;
|
|
fma.rn.f32 %f851, %f847, %f846, %f850;
|
|
mov.f32 %f852, 0f00000000;
|
|
fma.rn.f32 %f853, %f852, %f844, %f851;
|
|
add.rn.f32 %f854, %f848, %f853;
|
|
neg.f32 %f855, %f854;
|
|
add.rn.f32 %f856, %f848, %f855;
|
|
add.rn.f32 %f857, %f856, %f853;
|
|
mov.b32 %r343, %f854;
|
|
setp.eq.s32 %p105, %r343, 1118925336;
|
|
add.s32 %r344, %r343, -1;
|
|
mov.b32 %f858, %r344;
|
|
add.f32 %f859, %f857, 0f37000000;
|
|
selp.f32 %f227, %f859, %f857, %p105;
|
|
selp.f32 %f860, %f858, %f854, %p105;
|
|
mov.f32 %f861, 0f3FB8AA3B;
|
|
mul.rn.f32 %f862, %f860, %f861;
|
|
cvt.rzi.f32.f32 %f863, %f862;
|
|
abs.f32 %f864, %f863;
|
|
setp.gt.f32 %p106, %f864, 0f42FC0000;
|
|
mov.b32 %r345, %f863;
|
|
and.b32 %r346, %r345, -2147483648;
|
|
or.b32 %r347, %r346, 1123811328;
|
|
mov.b32 %f865, %r347;
|
|
selp.f32 %f866, %f865, %f863, %p106;
|
|
mov.f32 %f867, 0fBF317218;
|
|
fma.rn.f32 %f868, %f866, %f867, %f860;
|
|
mov.f32 %f869, 0f3102E308;
|
|
fma.rn.f32 %f870, %f866, %f869, %f868;
|
|
mul.f32 %f871, %f870, 0f3FB8AA3B;
|
|
add.f32 %f872, %f866, 0f4B40007F;
|
|
mov.b32 %r348, %f872;
|
|
shl.b32 %r349, %r348, 23;
|
|
mov.b32 %f873, %r349;
|
|
ex2.approx.ftz.f32 %f874, %f871;
|
|
mul.f32 %f228, %f874, %f873;
|
|
setp.eq.f32 %p107, %f228, 0f7F800000;
|
|
mov.f32 %f1572, 0f7F800000;
|
|
@%p107 bra $L__BB0_83;
|
|
|
|
fma.rn.f32 %f1572, %f228, %f227, %f228;
|
|
|
|
$L__BB0_83:
|
|
setp.lt.f32 %p108, %f210, 0f00000000;
|
|
and.pred %p5, %p108, %p94;
|
|
setp.eq.f32 %p110, %f210, 0f00000000;
|
|
@%p110 bra $L__BB0_87;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_87:
|
|
add.f32 %f879, %f210, %f210;
|
|
selp.f32 %f1574, %f879, 0f00000000, %p94;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_84:
|
|
mov.b32 %r350, %f1572;
|
|
xor.b32 %r351, %r350, -2147483648;
|
|
mov.b32 %f875, %r351;
|
|
selp.f32 %f1574, %f875, %f1572, %p5;
|
|
setp.geu.f32 %p111, %f210, 0f00000000;
|
|
@%p111 bra $L__BB0_88;
|
|
|
|
mov.f32 %f876, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f877, %f876;
|
|
setp.eq.f32 %p112, %f877, 0f3EE66666;
|
|
@%p112 bra $L__BB0_88;
|
|
|
|
mov.f32 %f1574, 0f7FFFFFFF;
|
|
|
|
$L__BB0_88:
|
|
add.f32 %f880, %f226, 0f3EE66666;
|
|
mov.b32 %r352, %f880;
|
|
setp.lt.s32 %p114, %r352, 2139095040;
|
|
@%p114 bra $L__BB0_93;
|
|
|
|
setp.gtu.f32 %p115, %f226, 0f7F800000;
|
|
@%p115 bra $L__BB0_92;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_92:
|
|
add.f32 %f1574, %f210, 0f3EE66666;
|
|
bra.uni $L__BB0_93;
|
|
|
|
$L__BB0_90:
|
|
setp.neu.f32 %p116, %f226, 0f7F800000;
|
|
@%p116 bra $L__BB0_93;
|
|
|
|
selp.f32 %f1574, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_93:
|
|
setp.eq.f32 %p117, %f210, 0f3F800000;
|
|
selp.f32 %f237, 0f3F800000, %f1574, %p117;
|
|
abs.f32 %f238, %f212;
|
|
setp.lt.f32 %p118, %f238, 0f00800000;
|
|
mul.f32 %f882, %f238, 0f4B800000;
|
|
selp.f32 %f883, %f882, %f238, %p118;
|
|
selp.f32 %f884, 0fC3170000, 0fC2FE0000, %p118;
|
|
mov.b32 %r353, %f883;
|
|
and.b32 %r354, %r353, 8388607;
|
|
or.b32 %r355, %r354, 1065353216;
|
|
mov.b32 %f885, %r355;
|
|
shr.u32 %r356, %r353, 23;
|
|
cvt.rn.f32.u32 %f886, %r356;
|
|
add.f32 %f887, %f884, %f886;
|
|
setp.gt.f32 %p119, %f885, 0f3FB504F3;
|
|
mul.f32 %f888, %f885, 0f3F000000;
|
|
add.f32 %f889, %f887, 0f3F800000;
|
|
selp.f32 %f890, %f889, %f887, %p119;
|
|
selp.f32 %f891, %f888, %f885, %p119;
|
|
add.f32 %f892, %f891, 0fBF800000;
|
|
add.f32 %f893, %f891, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f894, %f893;
|
|
add.f32 %f895, %f892, %f892;
|
|
mul.f32 %f896, %f895, %f894;
|
|
mul.f32 %f897, %f896, %f896;
|
|
mov.f32 %f898, 0f3C4CAF63;
|
|
mov.f32 %f899, 0f3B18F0FE;
|
|
fma.rn.f32 %f900, %f899, %f897, %f898;
|
|
mov.f32 %f901, 0f3DAAAABD;
|
|
fma.rn.f32 %f902, %f900, %f897, %f901;
|
|
mul.rn.f32 %f903, %f902, %f897;
|
|
mul.rn.f32 %f904, %f903, %f896;
|
|
sub.f32 %f905, %f892, %f896;
|
|
add.f32 %f906, %f905, %f905;
|
|
neg.f32 %f907, %f896;
|
|
fma.rn.f32 %f908, %f907, %f892, %f906;
|
|
mul.rn.f32 %f909, %f894, %f908;
|
|
add.f32 %f910, %f904, %f896;
|
|
sub.f32 %f911, %f896, %f910;
|
|
add.f32 %f912, %f904, %f911;
|
|
add.f32 %f913, %f909, %f912;
|
|
add.f32 %f914, %f910, %f913;
|
|
sub.f32 %f915, %f910, %f914;
|
|
add.f32 %f916, %f913, %f915;
|
|
mov.f32 %f917, 0f3F317200;
|
|
mul.rn.f32 %f918, %f890, %f917;
|
|
mov.f32 %f919, 0f35BFBE8E;
|
|
mul.rn.f32 %f920, %f890, %f919;
|
|
add.f32 %f921, %f918, %f914;
|
|
sub.f32 %f922, %f918, %f921;
|
|
add.f32 %f923, %f914, %f922;
|
|
add.f32 %f924, %f916, %f923;
|
|
add.f32 %f925, %f920, %f924;
|
|
add.f32 %f926, %f921, %f925;
|
|
sub.f32 %f927, %f921, %f926;
|
|
add.f32 %f928, %f925, %f927;
|
|
mov.f32 %f929, 0f3EE66666;
|
|
mul.rn.f32 %f930, %f929, %f926;
|
|
neg.f32 %f931, %f930;
|
|
fma.rn.f32 %f932, %f929, %f926, %f931;
|
|
fma.rn.f32 %f933, %f929, %f928, %f932;
|
|
mov.f32 %f934, 0f00000000;
|
|
fma.rn.f32 %f935, %f934, %f926, %f933;
|
|
add.rn.f32 %f936, %f930, %f935;
|
|
neg.f32 %f937, %f936;
|
|
add.rn.f32 %f938, %f930, %f937;
|
|
add.rn.f32 %f939, %f938, %f935;
|
|
mov.b32 %r357, %f936;
|
|
setp.eq.s32 %p120, %r357, 1118925336;
|
|
add.s32 %r358, %r357, -1;
|
|
mov.b32 %f940, %r358;
|
|
add.f32 %f941, %f939, 0f37000000;
|
|
selp.f32 %f239, %f941, %f939, %p120;
|
|
selp.f32 %f942, %f940, %f936, %p120;
|
|
mov.f32 %f943, 0f3FB8AA3B;
|
|
mul.rn.f32 %f944, %f942, %f943;
|
|
cvt.rzi.f32.f32 %f945, %f944;
|
|
abs.f32 %f946, %f945;
|
|
setp.gt.f32 %p121, %f946, 0f42FC0000;
|
|
mov.b32 %r359, %f945;
|
|
and.b32 %r360, %r359, -2147483648;
|
|
or.b32 %r361, %r360, 1123811328;
|
|
mov.b32 %f947, %r361;
|
|
selp.f32 %f948, %f947, %f945, %p121;
|
|
mov.f32 %f949, 0fBF317218;
|
|
fma.rn.f32 %f950, %f948, %f949, %f942;
|
|
mov.f32 %f951, 0f3102E308;
|
|
fma.rn.f32 %f952, %f948, %f951, %f950;
|
|
mul.f32 %f953, %f952, 0f3FB8AA3B;
|
|
add.f32 %f954, %f948, 0f4B40007F;
|
|
mov.b32 %r362, %f954;
|
|
shl.b32 %r363, %r362, 23;
|
|
mov.b32 %f955, %r363;
|
|
ex2.approx.ftz.f32 %f956, %f953;
|
|
mul.f32 %f240, %f956, %f955;
|
|
setp.eq.f32 %p122, %f240, 0f7F800000;
|
|
mov.f32 %f1575, 0f7F800000;
|
|
@%p122 bra $L__BB0_95;
|
|
|
|
fma.rn.f32 %f1575, %f240, %f239, %f240;
|
|
|
|
$L__BB0_95:
|
|
setp.lt.f32 %p123, %f212, 0f00000000;
|
|
and.pred %p6, %p123, %p94;
|
|
setp.eq.f32 %p125, %f212, 0f00000000;
|
|
@%p125 bra $L__BB0_99;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_99:
|
|
add.f32 %f961, %f212, %f212;
|
|
selp.f32 %f1577, %f961, 0f00000000, %p94;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_96:
|
|
mov.b32 %r364, %f1575;
|
|
xor.b32 %r365, %r364, -2147483648;
|
|
mov.b32 %f957, %r365;
|
|
selp.f32 %f1577, %f957, %f1575, %p6;
|
|
setp.geu.f32 %p126, %f212, 0f00000000;
|
|
@%p126 bra $L__BB0_100;
|
|
|
|
mov.f32 %f958, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f959, %f958;
|
|
setp.eq.f32 %p127, %f959, 0f3EE66666;
|
|
@%p127 bra $L__BB0_100;
|
|
|
|
mov.f32 %f1577, 0f7FFFFFFF;
|
|
|
|
$L__BB0_100:
|
|
add.f32 %f962, %f238, 0f3EE66666;
|
|
mov.b32 %r366, %f962;
|
|
setp.lt.s32 %p129, %r366, 2139095040;
|
|
@%p129 bra $L__BB0_105;
|
|
|
|
setp.gtu.f32 %p130, %f238, 0f7F800000;
|
|
@%p130 bra $L__BB0_104;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f1577, %f212, 0f3EE66666;
|
|
bra.uni $L__BB0_105;
|
|
|
|
$L__BB0_102:
|
|
setp.neu.f32 %p131, %f238, 0f7F800000;
|
|
@%p131 bra $L__BB0_105;
|
|
|
|
selp.f32 %f1577, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_105:
|
|
setp.eq.f32 %p132, %f212, 0f3F800000;
|
|
mov.f32 %f964, 0f3F800000;
|
|
selp.f32 %f965, 0f3F800000, %f1577, %p132;
|
|
ld.const.u64 %rd89, [params+144];
|
|
cvta.to.global.u64 %rd21, %rd89;
|
|
ld.const.u32 %r367, [params+136];
|
|
mad.lo.s32 %r368, %r367, %r8, %r7;
|
|
cvt.u64.u32 %rd22, %r368;
|
|
min.f32 %f966, %f225, %f964;
|
|
mov.f32 %f967, 0f00000000;
|
|
max.f32 %f249, %f967, %f966;
|
|
min.f32 %f968, %f237, %f964;
|
|
max.f32 %f250, %f967, %f968;
|
|
min.f32 %f969, %f965, %f964;
|
|
max.f32 %f251, %f967, %f969;
|
|
mov.f32 %f970, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f971, %f970;
|
|
add.f32 %f972, %f971, %f971;
|
|
mov.f32 %f973, 0f3ED55555;
|
|
sub.f32 %f974, %f973, %f972;
|
|
abs.f32 %f252, %f974;
|
|
abs.f32 %f253, %f249;
|
|
setp.lt.f32 %p133, %f253, 0f00800000;
|
|
mul.f32 %f975, %f253, 0f4B800000;
|
|
selp.f32 %f976, %f975, %f253, %p133;
|
|
selp.f32 %f977, 0fC3170000, 0fC2FE0000, %p133;
|
|
mov.b32 %r369, %f976;
|
|
and.b32 %r370, %r369, 8388607;
|
|
or.b32 %r371, %r370, 1065353216;
|
|
mov.b32 %f978, %r371;
|
|
shr.u32 %r372, %r369, 23;
|
|
cvt.rn.f32.u32 %f979, %r372;
|
|
add.f32 %f980, %f977, %f979;
|
|
setp.gt.f32 %p134, %f978, 0f3FB504F3;
|
|
mul.f32 %f981, %f978, 0f3F000000;
|
|
add.f32 %f982, %f980, 0f3F800000;
|
|
selp.f32 %f983, %f982, %f980, %p134;
|
|
selp.f32 %f984, %f981, %f978, %p134;
|
|
add.f32 %f985, %f984, 0fBF800000;
|
|
add.f32 %f986, %f984, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f987, %f986;
|
|
add.f32 %f988, %f985, %f985;
|
|
mul.f32 %f989, %f988, %f987;
|
|
mul.f32 %f990, %f989, %f989;
|
|
mov.f32 %f991, 0f3C4CAF63;
|
|
mov.f32 %f992, 0f3B18F0FE;
|
|
fma.rn.f32 %f993, %f992, %f990, %f991;
|
|
mov.f32 %f994, 0f3DAAAABD;
|
|
fma.rn.f32 %f995, %f993, %f990, %f994;
|
|
mul.rn.f32 %f996, %f995, %f990;
|
|
mul.rn.f32 %f997, %f996, %f989;
|
|
sub.f32 %f998, %f985, %f989;
|
|
add.f32 %f999, %f998, %f998;
|
|
neg.f32 %f1000, %f989;
|
|
fma.rn.f32 %f1001, %f1000, %f985, %f999;
|
|
mul.rn.f32 %f1002, %f987, %f1001;
|
|
add.f32 %f1003, %f997, %f989;
|
|
sub.f32 %f1004, %f989, %f1003;
|
|
add.f32 %f1005, %f997, %f1004;
|
|
add.f32 %f1006, %f1002, %f1005;
|
|
add.f32 %f1007, %f1003, %f1006;
|
|
sub.f32 %f1008, %f1003, %f1007;
|
|
add.f32 %f1009, %f1006, %f1008;
|
|
mov.f32 %f1010, 0f3F317200;
|
|
mul.rn.f32 %f1011, %f983, %f1010;
|
|
mov.f32 %f1012, 0f35BFBE8E;
|
|
mul.rn.f32 %f1013, %f983, %f1012;
|
|
add.f32 %f1014, %f1011, %f1007;
|
|
sub.f32 %f1015, %f1011, %f1014;
|
|
add.f32 %f1016, %f1007, %f1015;
|
|
add.f32 %f1017, %f1009, %f1016;
|
|
add.f32 %f1018, %f1013, %f1017;
|
|
add.f32 %f1019, %f1014, %f1018;
|
|
sub.f32 %f1020, %f1014, %f1019;
|
|
add.f32 %f1021, %f1018, %f1020;
|
|
mul.rn.f32 %f1022, %f973, %f1019;
|
|
neg.f32 %f1023, %f1022;
|
|
fma.rn.f32 %f1024, %f973, %f1019, %f1023;
|
|
fma.rn.f32 %f1025, %f973, %f1021, %f1024;
|
|
fma.rn.f32 %f1026, %f967, %f1019, %f1025;
|
|
add.rn.f32 %f1027, %f1022, %f1026;
|
|
neg.f32 %f1028, %f1027;
|
|
add.rn.f32 %f1029, %f1022, %f1028;
|
|
add.rn.f32 %f1030, %f1029, %f1026;
|
|
mov.b32 %r373, %f1027;
|
|
setp.eq.s32 %p135, %r373, 1118925336;
|
|
add.s32 %r374, %r373, -1;
|
|
mov.b32 %f1031, %r374;
|
|
add.f32 %f1032, %f1030, 0f37000000;
|
|
selp.f32 %f254, %f1032, %f1030, %p135;
|
|
selp.f32 %f1033, %f1031, %f1027, %p135;
|
|
mov.f32 %f1034, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1035, %f1033, %f1034;
|
|
cvt.rzi.f32.f32 %f1036, %f1035;
|
|
abs.f32 %f1037, %f1036;
|
|
setp.gt.f32 %p136, %f1037, 0f42FC0000;
|
|
mov.b32 %r375, %f1036;
|
|
and.b32 %r376, %r375, -2147483648;
|
|
or.b32 %r377, %r376, 1123811328;
|
|
mov.b32 %f1038, %r377;
|
|
selp.f32 %f1039, %f1038, %f1036, %p136;
|
|
mov.f32 %f1040, 0fBF317218;
|
|
fma.rn.f32 %f1041, %f1039, %f1040, %f1033;
|
|
mov.f32 %f1042, 0f3102E308;
|
|
fma.rn.f32 %f1043, %f1039, %f1042, %f1041;
|
|
mul.f32 %f1044, %f1043, 0f3FB8AA3B;
|
|
add.f32 %f1045, %f1039, 0f4B40007F;
|
|
mov.b32 %r378, %f1045;
|
|
shl.b32 %r379, %r378, 23;
|
|
mov.b32 %f1046, %r379;
|
|
ex2.approx.ftz.f32 %f1047, %f1044;
|
|
mul.f32 %f255, %f1047, %f1046;
|
|
setp.eq.f32 %p137, %f255, 0f7F800000;
|
|
mov.f32 %f1578, 0f7F800000;
|
|
@%p137 bra $L__BB0_107;
|
|
|
|
fma.rn.f32 %f1578, %f255, %f254, %f255;
|
|
|
|
$L__BB0_107:
|
|
setp.lt.f32 %p138, %f249, 0f00000000;
|
|
setp.eq.f32 %p139, %f252, 0f3F800000;
|
|
and.pred %p7, %p138, %p139;
|
|
setp.eq.f32 %p140, %f249, 0f00000000;
|
|
@%p140 bra $L__BB0_111;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_111:
|
|
add.f32 %f1052, %f249, %f249;
|
|
selp.f32 %f1580, %f1052, 0f00000000, %p139;
|
|
bra.uni $L__BB0_112;
|
|
|
|
$L__BB0_108:
|
|
mov.b32 %r380, %f1578;
|
|
xor.b32 %r381, %r380, -2147483648;
|
|
mov.b32 %f1048, %r381;
|
|
selp.f32 %f1580, %f1048, %f1578, %p7;
|
|
setp.geu.f32 %p141, %f249, 0f00000000;
|
|
@%p141 bra $L__BB0_112;
|
|
|
|
mov.f32 %f1049, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1050, %f1049;
|
|
setp.eq.f32 %p142, %f1050, 0f3ED55555;
|
|
@%p142 bra $L__BB0_112;
|
|
|
|
mov.f32 %f1580, 0f7FFFFFFF;
|
|
|
|
$L__BB0_112:
|
|
add.f32 %f1053, %f253, 0f3ED55555;
|
|
mov.b32 %r382, %f1053;
|
|
setp.lt.s32 %p144, %r382, 2139095040;
|
|
@%p144 bra $L__BB0_117;
|
|
|
|
setp.gtu.f32 %p145, %f253, 0f7F800000;
|
|
@%p145 bra $L__BB0_116;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_116:
|
|
add.f32 %f1580, %f249, 0f3ED55555;
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_114:
|
|
setp.neu.f32 %p146, %f253, 0f7F800000;
|
|
@%p146 bra $L__BB0_117;
|
|
|
|
selp.f32 %f1580, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_117:
|
|
abs.f32 %f264, %f250;
|
|
setp.lt.f32 %p147, %f264, 0f00800000;
|
|
mul.f32 %f1055, %f264, 0f4B800000;
|
|
selp.f32 %f1056, %f1055, %f264, %p147;
|
|
selp.f32 %f1057, 0fC3170000, 0fC2FE0000, %p147;
|
|
mov.b32 %r383, %f1056;
|
|
and.b32 %r384, %r383, 8388607;
|
|
or.b32 %r385, %r384, 1065353216;
|
|
mov.b32 %f1058, %r385;
|
|
shr.u32 %r386, %r383, 23;
|
|
cvt.rn.f32.u32 %f1059, %r386;
|
|
add.f32 %f1060, %f1057, %f1059;
|
|
setp.gt.f32 %p148, %f1058, 0f3FB504F3;
|
|
mul.f32 %f1061, %f1058, 0f3F000000;
|
|
add.f32 %f1062, %f1060, 0f3F800000;
|
|
selp.f32 %f1063, %f1062, %f1060, %p148;
|
|
selp.f32 %f1064, %f1061, %f1058, %p148;
|
|
add.f32 %f1065, %f1064, 0fBF800000;
|
|
add.f32 %f1066, %f1064, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1067, %f1066;
|
|
add.f32 %f1068, %f1065, %f1065;
|
|
mul.f32 %f1069, %f1068, %f1067;
|
|
mul.f32 %f1070, %f1069, %f1069;
|
|
mov.f32 %f1071, 0f3C4CAF63;
|
|
mov.f32 %f1072, 0f3B18F0FE;
|
|
fma.rn.f32 %f1073, %f1072, %f1070, %f1071;
|
|
mov.f32 %f1074, 0f3DAAAABD;
|
|
fma.rn.f32 %f1075, %f1073, %f1070, %f1074;
|
|
mul.rn.f32 %f1076, %f1075, %f1070;
|
|
mul.rn.f32 %f1077, %f1076, %f1069;
|
|
sub.f32 %f1078, %f1065, %f1069;
|
|
add.f32 %f1079, %f1078, %f1078;
|
|
neg.f32 %f1080, %f1069;
|
|
fma.rn.f32 %f1081, %f1080, %f1065, %f1079;
|
|
mul.rn.f32 %f1082, %f1067, %f1081;
|
|
add.f32 %f1083, %f1077, %f1069;
|
|
sub.f32 %f1084, %f1069, %f1083;
|
|
add.f32 %f1085, %f1077, %f1084;
|
|
add.f32 %f1086, %f1082, %f1085;
|
|
add.f32 %f1087, %f1083, %f1086;
|
|
sub.f32 %f1088, %f1083, %f1087;
|
|
add.f32 %f1089, %f1086, %f1088;
|
|
mov.f32 %f1090, 0f3F317200;
|
|
mul.rn.f32 %f1091, %f1063, %f1090;
|
|
mov.f32 %f1092, 0f35BFBE8E;
|
|
mul.rn.f32 %f1093, %f1063, %f1092;
|
|
add.f32 %f1094, %f1091, %f1087;
|
|
sub.f32 %f1095, %f1091, %f1094;
|
|
add.f32 %f1096, %f1087, %f1095;
|
|
add.f32 %f1097, %f1089, %f1096;
|
|
add.f32 %f1098, %f1093, %f1097;
|
|
add.f32 %f1099, %f1094, %f1098;
|
|
sub.f32 %f1100, %f1094, %f1099;
|
|
add.f32 %f1101, %f1098, %f1100;
|
|
mov.f32 %f1102, 0f3ED55555;
|
|
mul.rn.f32 %f1103, %f1102, %f1099;
|
|
neg.f32 %f1104, %f1103;
|
|
fma.rn.f32 %f1105, %f1102, %f1099, %f1104;
|
|
fma.rn.f32 %f1106, %f1102, %f1101, %f1105;
|
|
mov.f32 %f1107, 0f00000000;
|
|
fma.rn.f32 %f1108, %f1107, %f1099, %f1106;
|
|
add.rn.f32 %f1109, %f1103, %f1108;
|
|
neg.f32 %f1110, %f1109;
|
|
add.rn.f32 %f1111, %f1103, %f1110;
|
|
add.rn.f32 %f1112, %f1111, %f1108;
|
|
mov.b32 %r387, %f1109;
|
|
setp.eq.s32 %p149, %r387, 1118925336;
|
|
add.s32 %r388, %r387, -1;
|
|
mov.b32 %f1113, %r388;
|
|
add.f32 %f1114, %f1112, 0f37000000;
|
|
selp.f32 %f265, %f1114, %f1112, %p149;
|
|
selp.f32 %f1115, %f1113, %f1109, %p149;
|
|
mov.f32 %f1116, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1117, %f1115, %f1116;
|
|
cvt.rzi.f32.f32 %f1118, %f1117;
|
|
abs.f32 %f1119, %f1118;
|
|
setp.gt.f32 %p150, %f1119, 0f42FC0000;
|
|
mov.b32 %r389, %f1118;
|
|
and.b32 %r390, %r389, -2147483648;
|
|
or.b32 %r391, %r390, 1123811328;
|
|
mov.b32 %f1120, %r391;
|
|
selp.f32 %f1121, %f1120, %f1118, %p150;
|
|
mov.f32 %f1122, 0fBF317218;
|
|
fma.rn.f32 %f1123, %f1121, %f1122, %f1115;
|
|
mov.f32 %f1124, 0f3102E308;
|
|
fma.rn.f32 %f1125, %f1121, %f1124, %f1123;
|
|
mul.f32 %f1126, %f1125, 0f3FB8AA3B;
|
|
add.f32 %f1127, %f1121, 0f4B40007F;
|
|
mov.b32 %r392, %f1127;
|
|
shl.b32 %r393, %r392, 23;
|
|
mov.b32 %f1128, %r393;
|
|
ex2.approx.ftz.f32 %f1129, %f1126;
|
|
mul.f32 %f266, %f1129, %f1128;
|
|
setp.eq.f32 %p151, %f266, 0f7F800000;
|
|
mov.f32 %f1581, 0f7F800000;
|
|
@%p151 bra $L__BB0_119;
|
|
|
|
fma.rn.f32 %f1581, %f266, %f265, %f266;
|
|
|
|
$L__BB0_119:
|
|
setp.lt.f32 %p152, %f250, 0f00000000;
|
|
and.pred %p8, %p152, %p139;
|
|
setp.eq.f32 %p154, %f250, 0f00000000;
|
|
@%p154 bra $L__BB0_123;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_123:
|
|
add.f32 %f1134, %f250, %f250;
|
|
selp.f32 %f1583, %f1134, 0f00000000, %p139;
|
|
bra.uni $L__BB0_124;
|
|
|
|
$L__BB0_120:
|
|
mov.b32 %r394, %f1581;
|
|
xor.b32 %r395, %r394, -2147483648;
|
|
mov.b32 %f1130, %r395;
|
|
selp.f32 %f1583, %f1130, %f1581, %p8;
|
|
setp.geu.f32 %p155, %f250, 0f00000000;
|
|
@%p155 bra $L__BB0_124;
|
|
|
|
mov.f32 %f1131, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1132, %f1131;
|
|
setp.eq.f32 %p156, %f1132, 0f3ED55555;
|
|
@%p156 bra $L__BB0_124;
|
|
|
|
mov.f32 %f1583, 0f7FFFFFFF;
|
|
|
|
$L__BB0_124:
|
|
add.f32 %f1135, %f264, 0f3ED55555;
|
|
mov.b32 %r396, %f1135;
|
|
setp.lt.s32 %p158, %r396, 2139095040;
|
|
@%p158 bra $L__BB0_129;
|
|
|
|
setp.gtu.f32 %p159, %f264, 0f7F800000;
|
|
@%p159 bra $L__BB0_128;
|
|
bra.uni $L__BB0_126;
|
|
|
|
$L__BB0_128:
|
|
add.f32 %f1583, %f250, 0f3ED55555;
|
|
bra.uni $L__BB0_129;
|
|
|
|
$L__BB0_126:
|
|
setp.neu.f32 %p160, %f264, 0f7F800000;
|
|
@%p160 bra $L__BB0_129;
|
|
|
|
selp.f32 %f1583, 0fFF800000, 0f7F800000, %p8;
|
|
|
|
$L__BB0_129:
|
|
abs.f32 %f275, %f251;
|
|
setp.lt.f32 %p161, %f275, 0f00800000;
|
|
mul.f32 %f1137, %f275, 0f4B800000;
|
|
selp.f32 %f1138, %f1137, %f275, %p161;
|
|
selp.f32 %f1139, 0fC3170000, 0fC2FE0000, %p161;
|
|
mov.b32 %r397, %f1138;
|
|
and.b32 %r398, %r397, 8388607;
|
|
or.b32 %r399, %r398, 1065353216;
|
|
mov.b32 %f1140, %r399;
|
|
shr.u32 %r400, %r397, 23;
|
|
cvt.rn.f32.u32 %f1141, %r400;
|
|
add.f32 %f1142, %f1139, %f1141;
|
|
setp.gt.f32 %p162, %f1140, 0f3FB504F3;
|
|
mul.f32 %f1143, %f1140, 0f3F000000;
|
|
add.f32 %f1144, %f1142, 0f3F800000;
|
|
selp.f32 %f1145, %f1144, %f1142, %p162;
|
|
selp.f32 %f1146, %f1143, %f1140, %p162;
|
|
add.f32 %f1147, %f1146, 0fBF800000;
|
|
add.f32 %f1148, %f1146, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1149, %f1148;
|
|
add.f32 %f1150, %f1147, %f1147;
|
|
mul.f32 %f1151, %f1150, %f1149;
|
|
mul.f32 %f1152, %f1151, %f1151;
|
|
mov.f32 %f1153, 0f3C4CAF63;
|
|
mov.f32 %f1154, 0f3B18F0FE;
|
|
fma.rn.f32 %f1155, %f1154, %f1152, %f1153;
|
|
mov.f32 %f1156, 0f3DAAAABD;
|
|
fma.rn.f32 %f1157, %f1155, %f1152, %f1156;
|
|
mul.rn.f32 %f1158, %f1157, %f1152;
|
|
mul.rn.f32 %f1159, %f1158, %f1151;
|
|
sub.f32 %f1160, %f1147, %f1151;
|
|
add.f32 %f1161, %f1160, %f1160;
|
|
neg.f32 %f1162, %f1151;
|
|
fma.rn.f32 %f1163, %f1162, %f1147, %f1161;
|
|
mul.rn.f32 %f1164, %f1149, %f1163;
|
|
add.f32 %f1165, %f1159, %f1151;
|
|
sub.f32 %f1166, %f1151, %f1165;
|
|
add.f32 %f1167, %f1159, %f1166;
|
|
add.f32 %f1168, %f1164, %f1167;
|
|
add.f32 %f1169, %f1165, %f1168;
|
|
sub.f32 %f1170, %f1165, %f1169;
|
|
add.f32 %f1171, %f1168, %f1170;
|
|
mov.f32 %f1172, 0f3F317200;
|
|
mul.rn.f32 %f1173, %f1145, %f1172;
|
|
mov.f32 %f1174, 0f35BFBE8E;
|
|
mul.rn.f32 %f1175, %f1145, %f1174;
|
|
add.f32 %f1176, %f1173, %f1169;
|
|
sub.f32 %f1177, %f1173, %f1176;
|
|
add.f32 %f1178, %f1169, %f1177;
|
|
add.f32 %f1179, %f1171, %f1178;
|
|
add.f32 %f1180, %f1175, %f1179;
|
|
add.f32 %f1181, %f1176, %f1180;
|
|
sub.f32 %f1182, %f1176, %f1181;
|
|
add.f32 %f1183, %f1180, %f1182;
|
|
mov.f32 %f1184, 0f3ED55555;
|
|
mul.rn.f32 %f1185, %f1184, %f1181;
|
|
neg.f32 %f1186, %f1185;
|
|
fma.rn.f32 %f1187, %f1184, %f1181, %f1186;
|
|
fma.rn.f32 %f1188, %f1184, %f1183, %f1187;
|
|
mov.f32 %f1189, 0f00000000;
|
|
fma.rn.f32 %f1190, %f1189, %f1181, %f1188;
|
|
add.rn.f32 %f1191, %f1185, %f1190;
|
|
neg.f32 %f1192, %f1191;
|
|
add.rn.f32 %f1193, %f1185, %f1192;
|
|
add.rn.f32 %f1194, %f1193, %f1190;
|
|
mov.b32 %r401, %f1191;
|
|
setp.eq.s32 %p163, %r401, 1118925336;
|
|
add.s32 %r402, %r401, -1;
|
|
mov.b32 %f1195, %r402;
|
|
add.f32 %f1196, %f1194, 0f37000000;
|
|
selp.f32 %f276, %f1196, %f1194, %p163;
|
|
selp.f32 %f1197, %f1195, %f1191, %p163;
|
|
mov.f32 %f1198, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1199, %f1197, %f1198;
|
|
cvt.rzi.f32.f32 %f1200, %f1199;
|
|
abs.f32 %f1201, %f1200;
|
|
setp.gt.f32 %p164, %f1201, 0f42FC0000;
|
|
mov.b32 %r403, %f1200;
|
|
and.b32 %r404, %r403, -2147483648;
|
|
or.b32 %r405, %r404, 1123811328;
|
|
mov.b32 %f1202, %r405;
|
|
selp.f32 %f1203, %f1202, %f1200, %p164;
|
|
mov.f32 %f1204, 0fBF317218;
|
|
fma.rn.f32 %f1205, %f1203, %f1204, %f1197;
|
|
mov.f32 %f1206, 0f3102E308;
|
|
fma.rn.f32 %f1207, %f1203, %f1206, %f1205;
|
|
mul.f32 %f1208, %f1207, 0f3FB8AA3B;
|
|
add.f32 %f1209, %f1203, 0f4B40007F;
|
|
mov.b32 %r406, %f1209;
|
|
shl.b32 %r407, %r406, 23;
|
|
mov.b32 %f1210, %r407;
|
|
ex2.approx.ftz.f32 %f1211, %f1208;
|
|
mul.f32 %f277, %f1211, %f1210;
|
|
setp.eq.f32 %p165, %f277, 0f7F800000;
|
|
mov.f32 %f1584, 0f7F800000;
|
|
@%p165 bra $L__BB0_131;
|
|
|
|
fma.rn.f32 %f1584, %f277, %f276, %f277;
|
|
|
|
$L__BB0_131:
|
|
setp.lt.f32 %p166, %f251, 0f00000000;
|
|
and.pred %p9, %p166, %p139;
|
|
setp.eq.f32 %p168, %f251, 0f00000000;
|
|
@%p168 bra $L__BB0_135;
|
|
bra.uni $L__BB0_132;
|
|
|
|
$L__BB0_135:
|
|
add.f32 %f1216, %f251, %f251;
|
|
selp.f32 %f1586, %f1216, 0f00000000, %p139;
|
|
bra.uni $L__BB0_136;
|
|
|
|
$L__BB0_132:
|
|
mov.b32 %r408, %f1584;
|
|
xor.b32 %r409, %r408, -2147483648;
|
|
mov.b32 %f1212, %r409;
|
|
selp.f32 %f1586, %f1212, %f1584, %p9;
|
|
setp.geu.f32 %p169, %f251, 0f00000000;
|
|
@%p169 bra $L__BB0_136;
|
|
|
|
mov.f32 %f1213, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1214, %f1213;
|
|
setp.eq.f32 %p170, %f1214, 0f3ED55555;
|
|
@%p170 bra $L__BB0_136;
|
|
|
|
mov.f32 %f1586, 0f7FFFFFFF;
|
|
|
|
$L__BB0_136:
|
|
add.f32 %f1217, %f275, 0f3ED55555;
|
|
mov.b32 %r410, %f1217;
|
|
setp.lt.s32 %p172, %r410, 2139095040;
|
|
@%p172 bra $L__BB0_141;
|
|
|
|
setp.gtu.f32 %p173, %f275, 0f7F800000;
|
|
@%p173 bra $L__BB0_140;
|
|
bra.uni $L__BB0_138;
|
|
|
|
$L__BB0_140:
|
|
add.f32 %f1586, %f251, 0f3ED55555;
|
|
bra.uni $L__BB0_141;
|
|
|
|
$L__BB0_138:
|
|
setp.neu.f32 %p174, %f275, 0f7F800000;
|
|
@%p174 bra $L__BB0_141;
|
|
|
|
selp.f32 %f1586, 0fFF800000, 0f7F800000, %p9;
|
|
|
|
$L__BB0_141:
|
|
fma.rn.f32 %f1218, %f1580, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p175, %f249, 0f3F800000;
|
|
mov.f32 %f1219, 0f3F800000;
|
|
selp.f32 %f1220, 0f3F7FFFFF, %f1218, %p175;
|
|
mul.f32 %f1221, %f249, 0f414EB852;
|
|
setp.lt.f32 %p176, %f249, 0f3B4D2E1C;
|
|
selp.f32 %f1222, %f1221, %f1220, %p176;
|
|
fma.rn.f32 %f1223, %f1583, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p177, %f250, 0f3F800000;
|
|
selp.f32 %f1224, 0f3F7FFFFF, %f1223, %p177;
|
|
mul.f32 %f1225, %f250, 0f414EB852;
|
|
setp.lt.f32 %p178, %f250, 0f3B4D2E1C;
|
|
selp.f32 %f1226, %f1225, %f1224, %p178;
|
|
fma.rn.f32 %f1227, %f1586, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p179, %f251, 0f3F800000;
|
|
selp.f32 %f1228, 0f3F7FFFFF, %f1227, %p179;
|
|
mul.f32 %f1229, %f251, 0f414EB852;
|
|
setp.lt.f32 %p180, %f251, 0f3B4D2E1C;
|
|
selp.f32 %f1230, %f1229, %f1228, %p180;
|
|
min.f32 %f1231, %f1222, %f1219;
|
|
mov.f32 %f1232, 0f00000000;
|
|
max.f32 %f1233, %f1232, %f1231;
|
|
mul.f32 %f1234, %f1233, 0f43800000;
|
|
cvt.rzi.u32.f32 %r411, %f1234;
|
|
min.u32 %r412, %r411, 255;
|
|
min.f32 %f1235, %f1226, %f1219;
|
|
max.f32 %f1236, %f1232, %f1235;
|
|
mul.f32 %f1237, %f1236, 0f43800000;
|
|
cvt.rzi.u32.f32 %r413, %f1237;
|
|
min.u32 %r414, %r413, 255;
|
|
min.f32 %f1238, %f1230, %f1219;
|
|
max.f32 %f1239, %f1232, %f1238;
|
|
mul.f32 %f1240, %f1239, 0f43800000;
|
|
cvt.rzi.u32.f32 %r415, %f1240;
|
|
min.u32 %r416, %r415, 255;
|
|
shl.b64 %rd90, %rd22, 2;
|
|
add.s64 %rd91, %rd21, %rd90;
|
|
cvt.u16.u32 %rs18, %r416;
|
|
cvt.u16.u32 %rs19, %r414;
|
|
cvt.u16.u32 %rs20, %r412;
|
|
mov.u16 %rs21, 255;
|
|
st.global.v4.u8 [%rd91], {%rs20, %rs19, %rs18, %rs21};
|
|
|
|
$L__BB0_142:
|
|
and.b32 %r417, %r54, 4;
|
|
setp.eq.s32 %p181, %r417, 0;
|
|
ld.const.u32 %r483, [params+108];
|
|
@%p181 bra $L__BB0_146;
|
|
|
|
setp.eq.s32 %p182, %r483, 0;
|
|
ld.const.u64 %rd92, [params+224];
|
|
cvta.to.global.u64 %rd93, %rd92;
|
|
ld.const.u32 %r418, [params+216];
|
|
mad.lo.s32 %r419, %r418, %r8, %r7;
|
|
mul.wide.u32 %rd94, %r419, 8;
|
|
add.s64 %rd23, %rd93, %rd94;
|
|
@%p182 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs29, %rs30, %rs31, %rs32}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1241, %rs29;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1242, %rs30;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1243, %rs31;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1244, %f209, %f1241;
|
|
add.f32 %f1245, %f210, %f1242;
|
|
add.f32 %f1246, %f212, %f1243;
|
|
mov.f32 %f1247, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f1246;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs26, %f1245;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs25, %f1244;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f1247;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs25, %rs26, %rs27, %rs28};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1251, 0f3F800000;
|
|
mov.u32 %r483, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f1251;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f212;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f210;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f209;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs33, %rs34, %rs35, %rs36};
|
|
|
|
$L__BB0_146:
|
|
selp.f32 %f1252, 0f40800000, 0f3F800000, %p208;
|
|
mul.f32 %f1253, %f1252, %f1564;
|
|
mul.f32 %f286, %f1252, %f1563;
|
|
mul.f32 %f287, %f1252, %f1562;
|
|
mul.f32 %f288, %f1252, %f1561;
|
|
mul.f32 %f289, %f1252, %f1560;
|
|
mul.f32 %f290, %f1252, %f1559;
|
|
mul.f32 %f291, %f1252, %f1558;
|
|
mul.f32 %f292, %f1252, %f1557;
|
|
mul.f32 %f293, %f1252, %f1556;
|
|
mul.f32 %f1254, %f1253, %f711;
|
|
mul.f32 %f1255, %f1253, %f712;
|
|
mul.f32 %f1256, %f1253, %f211;
|
|
mul.f32 %f294, %f1254, 0f3F558750;
|
|
mul.f32 %f295, %f1255, 0f3F558750;
|
|
mul.f32 %f296, %f1256, 0f3F558750;
|
|
ld.const.u64 %rd95, [params+256];
|
|
cvta.to.global.u64 %rd96, %rd95;
|
|
ld.const.u32 %r421, [params+248];
|
|
mad.lo.s32 %r422, %r421, %r8, %r7;
|
|
mul.wide.u32 %rd97, %r422, 8;
|
|
add.s64 %rd24, %rd96, %rd97;
|
|
setp.eq.s32 %p183, %r483, 0;
|
|
@%p183 bra $L__BB0_148;
|
|
|
|
ld.global.v4.u16 {%rs44, %rs45, %rs46, %rs47}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1257, %rs44;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1258, %rs45;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1259, %rs46;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1260, %f294, %f1257;
|
|
add.f32 %f1261, %f295, %f1258;
|
|
add.f32 %f1262, %f296, %f1259;
|
|
mov.f32 %f1263, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f1262;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f1261;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f1260;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f1263;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs40, %rs41, %rs42, %rs43};
|
|
bra.uni $L__BB0_149;
|
|
|
|
$L__BB0_148:
|
|
mov.f32 %f1267, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f1267;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f296;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f295;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f294;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs48, %rs49, %rs50, %rs51};
|
|
|
|
$L__BB0_149:
|
|
mul.f32 %f1268, %f286, %f711;
|
|
mul.f32 %f297, %f1268, 0f3FB8EBD1;
|
|
mul.f32 %f1269, %f286, %f712;
|
|
mul.f32 %f298, %f1269, 0f3FB8EBD1;
|
|
mul.f32 %f1270, %f286, %f211;
|
|
mul.f32 %f299, %f1270, 0f3FB8EBD1;
|
|
ld.const.u64 %rd98, [params+272];
|
|
cvta.to.global.u64 %rd99, %rd98;
|
|
ld.const.u32 %r423, [params+264];
|
|
mad.lo.s32 %r424, %r423, %r8, %r7;
|
|
mul.wide.u32 %rd100, %r424, 8;
|
|
add.s64 %rd25, %rd99, %rd100;
|
|
@%p183 bra $L__BB0_151;
|
|
|
|
ld.global.v4.u16 {%rs59, %rs60, %rs61, %rs62}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1271, %rs59;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1272, %rs60;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1273, %rs61;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1274, %f297, %f1271;
|
|
add.f32 %f1275, %f298, %f1272;
|
|
add.f32 %f1276, %f299, %f1273;
|
|
mov.f32 %f1277, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1276;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f1275;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f1274;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f1277;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs55, %rs56, %rs57, %rs58};
|
|
bra.uni $L__BB0_152;
|
|
|
|
$L__BB0_151:
|
|
mov.f32 %f1281, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f1281;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f299;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f298;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f297;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs63, %rs64, %rs65, %rs66};
|
|
|
|
$L__BB0_152:
|
|
mul.f32 %f1282, %f287, %f711;
|
|
mul.f32 %f300, %f1282, 0f3FB8EBD1;
|
|
mul.f32 %f1283, %f287, %f712;
|
|
mul.f32 %f301, %f1283, 0f3FB8EBD1;
|
|
mul.f32 %f1284, %f287, %f211;
|
|
mul.f32 %f302, %f1284, 0f3FB8EBD1;
|
|
ld.const.u64 %rd101, [params+288];
|
|
cvta.to.global.u64 %rd102, %rd101;
|
|
ld.const.u32 %r425, [params+280];
|
|
mad.lo.s32 %r426, %r425, %r8, %r7;
|
|
mul.wide.u32 %rd103, %r426, 8;
|
|
add.s64 %rd26, %rd102, %rd103;
|
|
@%p183 bra $L__BB0_154;
|
|
|
|
ld.global.v4.u16 {%rs74, %rs75, %rs76, %rs77}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1285, %rs74;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1286, %rs75;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1287, %rs76;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1288, %f300, %f1285;
|
|
add.f32 %f1289, %f301, %f1286;
|
|
add.f32 %f1290, %f302, %f1287;
|
|
mov.f32 %f1291, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1290;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f1289;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1288;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1291;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs70, %rs71, %rs72, %rs73};
|
|
bra.uni $L__BB0_155;
|
|
|
|
$L__BB0_154:
|
|
mov.f32 %f1295, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f1295;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f302;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f301;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f300;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs78, %rs79, %rs80, %rs81};
|
|
|
|
$L__BB0_155:
|
|
mul.f32 %f1296, %f288, %f711;
|
|
mul.f32 %f303, %f1296, 0f3FB8EBD1;
|
|
mul.f32 %f1297, %f288, %f712;
|
|
mul.f32 %f304, %f1297, 0f3FB8EBD1;
|
|
mul.f32 %f1298, %f288, %f211;
|
|
mul.f32 %f305, %f1298, 0f3FB8EBD1;
|
|
ld.const.u64 %rd104, [params+304];
|
|
cvta.to.global.u64 %rd105, %rd104;
|
|
ld.const.u32 %r427, [params+296];
|
|
mad.lo.s32 %r428, %r427, %r8, %r7;
|
|
mul.wide.u32 %rd106, %r428, 8;
|
|
add.s64 %rd27, %rd105, %rd106;
|
|
@%p183 bra $L__BB0_157;
|
|
|
|
ld.global.v4.u16 {%rs89, %rs90, %rs91, %rs92}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1299, %rs89;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1300, %rs90;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1301, %rs91;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1302, %f303, %f1299;
|
|
add.f32 %f1303, %f304, %f1300;
|
|
add.f32 %f1304, %f305, %f1301;
|
|
mov.f32 %f1305, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1304;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1303;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1302;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1305;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs85, %rs86, %rs87, %rs88};
|
|
bra.uni $L__BB0_158;
|
|
|
|
$L__BB0_157:
|
|
mov.f32 %f1309, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f1309;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f305;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f304;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f303;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs93, %rs94, %rs95, %rs96};
|
|
|
|
$L__BB0_158:
|
|
mul.f32 %f1310, %f289, %f711;
|
|
mul.f32 %f306, %f1310, 0f404EBF87;
|
|
mul.f32 %f1311, %f289, %f712;
|
|
mul.f32 %f307, %f1311, 0f404EBF87;
|
|
mul.f32 %f1312, %f289, %f211;
|
|
mul.f32 %f308, %f1312, 0f404EBF87;
|
|
ld.const.u64 %rd107, [params+320];
|
|
cvta.to.global.u64 %rd108, %rd107;
|
|
ld.const.u32 %r429, [params+312];
|
|
mad.lo.s32 %r430, %r429, %r8, %r7;
|
|
mul.wide.u32 %rd109, %r430, 8;
|
|
add.s64 %rd28, %rd108, %rd109;
|
|
@%p183 bra $L__BB0_160;
|
|
|
|
ld.global.v4.u16 {%rs104, %rs105, %rs106, %rs107}, [%rd28];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1313, %rs104;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1314, %rs105;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1315, %rs106;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1316, %f306, %f1313;
|
|
add.f32 %f1317, %f307, %f1314;
|
|
add.f32 %f1318, %f308, %f1315;
|
|
mov.f32 %f1319, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs102, %f1318;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs101, %f1317;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs100, %f1316;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs103, %f1319;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd28], {%rs100, %rs101, %rs102, %rs103};
|
|
bra.uni $L__BB0_161;
|
|
|
|
$L__BB0_160:
|
|
mov.f32 %f1323, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs111, %f1323;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs110, %f308;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs109, %f307;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f306;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd28], {%rs108, %rs109, %rs110, %rs111};
|
|
|
|
$L__BB0_161:
|
|
mul.f32 %f1324, %f290, %f711;
|
|
mul.f32 %f309, %f1324, 0f404EBF87;
|
|
mul.f32 %f1325, %f290, %f712;
|
|
mul.f32 %f310, %f1325, 0f404EBF87;
|
|
mul.f32 %f1326, %f290, %f211;
|
|
mul.f32 %f311, %f1326, 0f404EBF87;
|
|
ld.const.u64 %rd110, [params+336];
|
|
cvta.to.global.u64 %rd111, %rd110;
|
|
ld.const.u32 %r431, [params+328];
|
|
mad.lo.s32 %r432, %r431, %r8, %r7;
|
|
mul.wide.u32 %rd112, %r432, 8;
|
|
add.s64 %rd29, %rd111, %rd112;
|
|
@%p183 bra $L__BB0_163;
|
|
|
|
ld.global.v4.u16 {%rs119, %rs120, %rs121, %rs122}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1327, %rs119;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1328, %rs120;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1329, %rs121;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1330, %f309, %f1327;
|
|
add.f32 %f1331, %f310, %f1328;
|
|
add.f32 %f1332, %f311, %f1329;
|
|
mov.f32 %f1333, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs117, %f1332;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs116, %f1331;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1330;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs118, %f1333;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd29], {%rs115, %rs116, %rs117, %rs118};
|
|
bra.uni $L__BB0_164;
|
|
|
|
$L__BB0_163:
|
|
mov.f32 %f1337, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs126, %f1337;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs125, %f311;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs124, %f310;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f309;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd29], {%rs123, %rs124, %rs125, %rs126};
|
|
|
|
$L__BB0_164:
|
|
mul.f32 %f1338, %f291, %f711;
|
|
mul.f32 %f312, %f1338, 0f40330C94;
|
|
mul.f32 %f1339, %f291, %f712;
|
|
mul.f32 %f313, %f1339, 0f40330C94;
|
|
mul.f32 %f1340, %f291, %f211;
|
|
mul.f32 %f314, %f1340, 0f40330C94;
|
|
ld.const.u64 %rd113, [params+352];
|
|
cvta.to.global.u64 %rd114, %rd113;
|
|
ld.const.u32 %r433, [params+344];
|
|
mad.lo.s32 %r434, %r433, %r8, %r7;
|
|
mul.wide.u32 %rd115, %r434, 8;
|
|
add.s64 %rd30, %rd114, %rd115;
|
|
@%p183 bra $L__BB0_166;
|
|
|
|
ld.global.v4.u16 {%rs134, %rs135, %rs136, %rs137}, [%rd30];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1341, %rs134;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1342, %rs135;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1343, %rs136;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1344, %f312, %f1341;
|
|
add.f32 %f1345, %f313, %f1342;
|
|
add.f32 %f1346, %f314, %f1343;
|
|
mov.f32 %f1347, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs132, %f1346;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs131, %f1345;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1344;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs133, %f1347;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd30], {%rs130, %rs131, %rs132, %rs133};
|
|
bra.uni $L__BB0_167;
|
|
|
|
$L__BB0_166:
|
|
mov.f32 %f1351, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs141, %f1351;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs140, %f314;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs139, %f313;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f312;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd30], {%rs138, %rs139, %rs140, %rs141};
|
|
|
|
$L__BB0_167:
|
|
mul.f32 %f1352, %f292, %f711;
|
|
mul.f32 %f315, %f1352, 0f404EBF87;
|
|
mul.f32 %f1353, %f292, %f712;
|
|
mul.f32 %f316, %f1353, 0f404EBF87;
|
|
mul.f32 %f1354, %f292, %f211;
|
|
mul.f32 %f317, %f1354, 0f404EBF87;
|
|
ld.const.u64 %rd116, [params+368];
|
|
cvta.to.global.u64 %rd117, %rd116;
|
|
ld.const.u32 %r435, [params+360];
|
|
mad.lo.s32 %r436, %r435, %r8, %r7;
|
|
mul.wide.u32 %rd118, %r436, 8;
|
|
add.s64 %rd31, %rd117, %rd118;
|
|
@%p183 bra $L__BB0_169;
|
|
|
|
ld.global.v4.u16 {%rs149, %rs150, %rs151, %rs152}, [%rd31];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1355, %rs149;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1356, %rs150;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1357, %rs151;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1358, %f315, %f1355;
|
|
add.f32 %f1359, %f316, %f1356;
|
|
add.f32 %f1360, %f317, %f1357;
|
|
mov.f32 %f1361, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs147, %f1360;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs146, %f1359;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1358;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs148, %f1361;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd31], {%rs145, %rs146, %rs147, %rs148};
|
|
bra.uni $L__BB0_170;
|
|
|
|
$L__BB0_169:
|
|
mov.f32 %f1365, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs156, %f1365;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs155, %f317;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs154, %f316;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f315;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd31], {%rs153, %rs154, %rs155, %rs156};
|
|
|
|
$L__BB0_170:
|
|
mul.f32 %f1366, %f293, %f711;
|
|
mul.f32 %f318, %f1366, 0f3FCEBF87;
|
|
mul.f32 %f1367, %f293, %f712;
|
|
mul.f32 %f319, %f1367, 0f3FCEBF87;
|
|
mul.f32 %f1368, %f293, %f211;
|
|
mul.f32 %f320, %f1368, 0f3FCEBF87;
|
|
ld.const.u64 %rd119, [params+384];
|
|
cvta.to.global.u64 %rd120, %rd119;
|
|
ld.const.u32 %r437, [params+376];
|
|
mad.lo.s32 %r438, %r437, %r8, %r7;
|
|
mul.wide.u32 %rd121, %r438, 8;
|
|
add.s64 %rd32, %rd120, %rd121;
|
|
@%p183 bra $L__BB0_172;
|
|
|
|
ld.global.v4.u16 {%rs164, %rs165, %rs166, %rs167}, [%rd32];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1369, %rs164;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1370, %rs165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1371, %rs166;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1372, %f318, %f1369;
|
|
add.f32 %f1373, %f319, %f1370;
|
|
add.f32 %f1374, %f320, %f1371;
|
|
mov.f32 %f1375, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs162, %f1374;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs161, %f1373;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1372;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs163, %f1375;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd32], {%rs160, %rs161, %rs162, %rs163};
|
|
bra.uni $L__BB0_208;
|
|
|
|
$L__BB0_172:
|
|
mov.f32 %f1379, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs171, %f1379;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs170, %f320;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs169, %f319;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs168, %f318;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd32], {%rs168, %rs169, %rs170, %rs171};
|
|
|
|
$L__BB0_208:
|
|
ret;
|
|
|
|
}
|
|
|