2912 lines
76 KiB
Plaintext
2912 lines
76 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<165>;
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.reg .b16 %rs<322>;
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.reg .f32 %f<1460>;
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.reg .b32 %r<381>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<148>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r58), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r59), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+540];
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shl.b32 %r4, %r3, 1;
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ld.const.u64 %rd38, [params+400];
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cvta.to.global.u64 %rd39, %rd38;
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ld.const.u32 %r64, [params+392];
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mad.lo.s32 %r65, %r64, %r59, %r58;
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mul.wide.u32 %rd40, %r65, 4;
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add.s64 %rd2, %rd39, %rd40;
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ld.global.v2.u8 {%rs7, %rs321}, [%rd2];
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or.b16 %rs9, %rs7, %rs321;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p7, %rs10, 0;
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@%p7 bra $L__BB0_2;
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ld.global.u8 %rs320, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs320, [%rd2+2];
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setp.eq.s16 %p8, %rs320, 0;
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mov.f32 %f1313, 0f00000000;
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mov.u16 %rs321, 0;
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mov.f32 %f1314, %f1313;
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mov.f32 %f1315, %f1313;
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@%p8 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f342, %rs7;
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div.rn.f32 %f343, %f342, 0f437F0000;
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fma.rn.f32 %f344, %f343, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs321, 255;
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cvt.rn.f32.u16 %f345, %rs13;
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div.rn.f32 %f346, %f345, 0f437F0000;
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fma.rn.f32 %f347, %f346, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f348, %rs320;
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div.rn.f32 %f349, %f348, 0f437F0000;
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fma.rn.f32 %f350, %f349, 0f40000000, 0fBF800000;
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mul.f32 %f351, %f347, %f347;
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fma.rn.f32 %f352, %f344, %f344, %f351;
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fma.rn.f32 %f353, %f350, %f350, %f352;
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sqrt.rn.f32 %f354, %f353;
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rcp.rn.f32 %f355, %f354;
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mul.f32 %f1315, %f355, %f350;
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mul.f32 %f1314, %f355, %f347;
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mul.f32 %f1313, %f344, %f355;
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$L__BB0_4:
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ld.const.v2.u32 {%r66, %r67}, [params];
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add.s32 %r5, %r66, %r58;
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add.s32 %r6, %r67, %r59;
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setp.eq.f32 %p9, %f1313, 0f00000000;
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setp.eq.f32 %p10, %f1314, 0f00000000;
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and.pred %p11, %p9, %p10;
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setp.eq.f32 %p12, %f1315, 0f00000000;
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and.pred %p13, %p12, %p11;
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@%p13 bra $L__BB0_141;
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bra.uni $L__BB0_5;
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$L__BB0_141:
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ld.const.u32 %r55, [params+104];
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and.b32 %r326, %r55, 1;
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setp.eq.b32 %p149, %r326, 1;
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mov.pred %p150, 0;
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xor.pred %p151, %p149, %p150;
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not.pred %p152, %p151;
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@%p152 bra $L__BB0_143;
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ld.const.u64 %rd110, [params+144];
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cvta.to.global.u64 %rd111, %rd110;
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ld.const.u32 %r327, [params+136];
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mad.lo.s32 %r328, %r327, %r6, %r5;
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mul.wide.u32 %rd112, %r328, 4;
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add.s64 %rd113, %rd111, %rd112;
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mov.u16 %rs169, 0;
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st.global.v4.u8 [%rd113], {%rs169, %rs169, %rs169, %rs169};
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$L__BB0_143:
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and.b32 %r329, %r55, 4;
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setp.eq.s32 %p153, %r329, 0;
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ld.const.u32 %r380, [params+108];
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@%p153 bra $L__BB0_147;
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setp.eq.s32 %p154, %r380, 0;
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ld.const.u64 %rd114, [params+224];
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cvta.to.global.u64 %rd115, %rd114;
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ld.const.u32 %r330, [params+216];
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mad.lo.s32 %r331, %r330, %r6, %r5;
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mul.wide.u32 %rd116, %r331, 8;
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add.s64 %rd27, %rd115, %rd116;
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@%p154 bra $L__BB0_146;
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ld.global.v4.u16 {%rs176, %rs177, %rs178, %rs179}, [%rd27];
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// begin inline asm
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{ cvt.f32.f16 %f1220, %rs176;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1221, %rs177;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1222, %rs178;}
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// end inline asm
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add.f32 %f1223, %f1220, 0f00000000;
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add.f32 %f1224, %f1221, 0f00000000;
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add.f32 %f1225, %f1222, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs175, %f1225;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs174, %f1224;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs173, %f1223;}
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// end inline asm
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mov.u16 %rs180, 0;
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st.global.v4.u16 [%rd27], {%rs173, %rs174, %rs175, %rs180};
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bra.uni $L__BB0_147;
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$L__BB0_5:
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ld.const.u64 %rd41, [params+432];
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cvta.to.global.u64 %rd42, %rd41;
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ld.const.u32 %r70, [params+424];
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mad.lo.s32 %r71, %r70, %r59, %r58;
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mul.wide.u32 %rd43, %r71, 12;
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add.s64 %rd44, %rd42, %rd43;
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ld.global.f32 %f386, [%rd44];
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mul.f32 %f387, %f386, 0f3456BF95;
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ld.global.f32 %f388, [%rd44+4];
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mul.f32 %f389, %f388, 0f3456BF95;
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ld.global.f32 %f390, [%rd44+8];
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mul.f32 %f391, %f390, 0f3456BF95;
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abs.f32 %f392, %f1313;
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div.rn.f32 %f393, %f387, %f392;
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abs.f32 %f394, %f1314;
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div.rn.f32 %f395, %f389, %f394;
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abs.f32 %f396, %f1315;
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div.rn.f32 %f397, %f391, %f396;
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abs.f32 %f398, %f393;
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abs.f32 %f399, %f395;
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abs.f32 %f400, %f397;
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mov.f32 %f401, 0f38D1B717;
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max.f32 %f402, %f398, %f401;
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max.f32 %f403, %f399, %f401;
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max.f32 %f404, %f400, %f401;
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fma.rn.f32 %f10, %f1313, %f402, %f386;
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fma.rn.f32 %f11, %f1314, %f403, %f388;
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fma.rn.f32 %f12, %f1315, %f404, %f390;
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setp.gt.f32 %p14, %f392, %f396;
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neg.f32 %f405, %f1314;
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selp.f32 %f406, %f405, 0f00000000, %p14;
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mov.f32 %f1382, 0f00000000;
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neg.f32 %f407, %f1315;
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selp.f32 %f408, %f1313, %f407, %p14;
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selp.f32 %f409, 0f00000000, %f1314, %p14;
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mul.f32 %f410, %f408, %f408;
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fma.rn.f32 %f411, %f406, %f406, %f410;
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fma.rn.f32 %f412, %f409, %f409, %f411;
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sqrt.rn.f32 %f413, %f412;
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rcp.rn.f32 %f414, %f413;
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mul.f32 %f13, %f406, %f414;
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mul.f32 %f14, %f408, %f414;
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mul.f32 %f15, %f409, %f414;
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ld.const.u64 %rd45, [params+128];
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cvta.to.global.u64 %rd46, %rd45;
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ld.const.u32 %r72, [params+120];
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mad.lo.s32 %r73, %r72, %r59, %r58;
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mul.wide.u32 %rd47, %r73, 4;
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add.s64 %rd3, %rd46, %rd47;
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setp.lt.s32 %p15, %r3, 1;
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mov.f32 %f1383, %f1382;
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mov.f32 %f1384, %f1382;
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mov.f32 %f1385, %f1382;
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mov.f32 %f1386, %f1382;
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mov.f32 %f1387, %f1382;
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mov.f32 %f1388, %f1382;
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mov.f32 %f1389, %f1382;
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mov.f32 %f1390, %f1382;
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mov.f32 %f1391, %f1382;
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mov.f32 %f1392, %f1382;
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mov.f32 %f1393, %f1382;
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mov.f32 %f1394, %f1382;
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mov.f32 %f1395, %f1382;
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mov.f32 %f1396, %f1382;
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mov.f32 %f1397, %f1382;
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mov.f32 %f1398, %f1382;
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mov.f32 %f1399, %f1382;
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mov.f32 %f1400, %f1382;
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mov.f32 %f1401, %f1382;
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mov.f32 %f1402, %f1382;
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mov.f32 %f1403, %f1382;
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mov.f32 %f1404, %f1382;
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mov.f32 %f1405, %f1382;
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mov.f32 %f1406, %f1382;
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mov.f32 %f1407, %f1382;
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mov.f32 %f1408, %f1382;
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mov.f32 %f1409, %f1382;
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mov.f32 %f1410, %f1382;
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mov.f32 %f1411, %f1382;
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@%p15 bra $L__BB0_36;
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ld.const.u32 %r7, [params+588];
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cvt.rn.f32.s32 %f445, %r4;
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rcp.rn.f32 %f16, %f445;
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ld.global.u32 %r370, [%rd3];
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mul.f32 %f17, %f10, 0f3456BF95;
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mul.f32 %f18, %f11, 0f3456BF95;
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mul.f32 %f19, %f12, 0f3456BF95;
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ld.const.u64 %rd4, [params+592];
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ld.const.u64 %rd5, [params+96];
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mul.f32 %f446, %f1313, %f14;
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mul.f32 %f447, %f1314, %f13;
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sub.f32 %f20, %f447, %f446;
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mul.f32 %f448, %f1315, %f13;
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mul.f32 %f449, %f1313, %f15;
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sub.f32 %f21, %f449, %f448;
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mul.f32 %f450, %f1314, %f15;
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mul.f32 %f451, %f1315, %f14;
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sub.f32 %f22, %f451, %f450;
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mov.u32 %r74, 0;
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add.s64 %rd6, %rd1, 24;
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abs.f32 %f516, %f17;
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abs.f32 %f517, %f18;
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max.f32 %f518, %f516, %f517;
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abs.f32 %f519, %f19;
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max.f32 %f520, %f518, %f519;
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mov.u32 %r367, %r74;
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$L__BB0_7:
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mov.u32 %r369, %r74;
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$L__BB0_8:
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cvt.rn.f32.s32 %f1311, %r367;
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mad.lo.s32 %r76, %r370, 1664525, 1013904223;
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and.b32 %r77, %r76, 16777215;
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cvt.rn.f32.u32 %f452, %r77;
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fma.rn.f32 %f453, %f452, 0f33800000, %f1311;
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mul.f32 %f454, %f16, %f453;
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mad.lo.s32 %r370, %r76, 1664525, 1013904223;
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and.b32 %r78, %r370, 16777215;
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cvt.rn.f32.u32 %f455, %r78;
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cvt.rn.f32.s32 %f456, %r369;
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fma.rn.f32 %f457, %f455, 0f33800000, %f456;
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mul.f32 %f458, %f16, %f457;
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fma.rn.f32 %f459, %f16, %f453, %f454;
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mov.f32 %f460, 0f3F800000;
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sub.f32 %f84, %f460, %f459;
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mul.f32 %f461, %f84, %f84;
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sub.f32 %f462, %f460, %f461;
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mov.f32 %f463, 0f00000000;
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max.f32 %f464, %f463, %f462;
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sqrt.rn.f32 %f85, %f464;
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mul.f32 %f86, %f458, 0f40C90FDB;
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mul.f32 %f465, %f86, 0f3F22F983;
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cvt.rni.s32.f32 %r374, %f465;
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cvt.rn.f32.s32 %f466, %r374;
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mov.f32 %f467, 0fBFC90FDA;
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fma.rn.f32 %f468, %f466, %f467, %f86;
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mov.f32 %f469, 0fB3A22168;
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fma.rn.f32 %f470, %f466, %f469, %f468;
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mov.f32 %f471, 0fA7C234C5;
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fma.rn.f32 %f1379, %f466, %f471, %f470;
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abs.f32 %f88, %f86;
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setp.ltu.f32 %p16, %f88, 0f47CE4780;
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mov.f32 %f1376, %f1379;
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@%p16 bra $L__BB0_16;
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setp.eq.f32 %p17, %f88, 0f7F800000;
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@%p17 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f474, 0f00000000;
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mul.rn.f32 %f1376, %f86, %f474;
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mov.u32 %r374, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r15, %f86;
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bfe.u32 %r80, %r15, 23, 8;
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mov.u64 %rd144, 0;
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mov.u32 %r371, 0;
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mov.u64 %rd145, %rd144;
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$L__BB0_11:
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.pragma "nounroll";
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mov.b32 %r353, %f86;
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shl.b32 %r352, %r353, 8;
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or.b32 %r351, %r352, -2147483648;
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shl.b64 %rd50, %rd144, 2;
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mov.u64 %rd51, __cudart_i2opi_f;
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add.s64 %rd52, %rd51, %rd50;
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ld.global.nc.u32 %r82, [%rd52];
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mad.wide.u32 %rd53, %r82, %r351, %rd145;
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shr.u64 %rd145, %rd53, 32;
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add.s64 %rd54, %rd1, %rd50;
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st.local.u32 [%rd54], %rd53;
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add.s32 %r371, %r371, 1;
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cvt.s64.s32 %rd144, %r371;
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setp.ne.s32 %p18, %r371, 6;
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@%p18 bra $L__BB0_11;
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add.s32 %r358, %r80, -128;
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mov.b32 %r357, %f86;
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bfe.u32 %r356, %r357, 23, 8;
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add.s32 %r355, %r356, -128;
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shr.u32 %r354, %r355, 5;
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st.local.u32 [%rd6], %rd145;
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mov.u32 %r84, 6;
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sub.s32 %r85, %r84, %r354;
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mul.wide.s32 %rd55, %r85, 4;
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add.s64 %rd56, %rd1, %rd55;
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ld.local.u32 %r372, [%rd56];
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ld.local.u32 %r373, [%rd56+-4];
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and.b32 %r24, %r355, 31;
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setp.eq.s32 %p19, %r24, 0;
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@%p19 bra $L__BB0_14;
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mov.b32 %r366, %f86;
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bfe.u32 %r365, %r366, 23, 8;
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add.s32 %r364, %r365, -128;
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shr.u32 %r363, %r364, 5;
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mov.u32 %r362, 4;
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sub.s32 %r361, %r362, %r363;
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mov.u32 %r86, 32;
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sub.s32 %r87, %r86, %r24;
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shr.u32 %r88, %r373, %r87;
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shl.b32 %r89, %r372, %r24;
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add.s32 %r372, %r88, %r89;
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mul.wide.s32 %rd57, %r361, 4;
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add.s64 %rd58, %rd1, %rd57;
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ld.local.u32 %r90, [%rd58];
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shr.u32 %r91, %r90, %r87;
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shl.b32 %r92, %r373, %r24;
|
|
add.s32 %r373, %r91, %r92;
|
|
|
|
$L__BB0_14:
|
|
mov.b32 %r359, %f86;
|
|
and.b32 %r93, %r359, -2147483648;
|
|
shr.u32 %r94, %r373, 30;
|
|
shl.b32 %r95, %r372, 2;
|
|
or.b32 %r96, %r94, %r95;
|
|
shr.u32 %r97, %r96, 31;
|
|
shr.u32 %r98, %r372, 30;
|
|
add.s32 %r99, %r97, %r98;
|
|
neg.s32 %r100, %r99;
|
|
setp.eq.s32 %p20, %r93, 0;
|
|
selp.b32 %r374, %r99, %r100, %p20;
|
|
setp.ne.s32 %p21, %r97, 0;
|
|
xor.b32 %r101, %r93, -2147483648;
|
|
selp.b32 %r102, %r101, %r93, %p21;
|
|
selp.b32 %r103, -1, 0, %p21;
|
|
xor.b32 %r104, %r96, %r103;
|
|
shl.b32 %r105, %r373, 2;
|
|
xor.b32 %r106, %r105, %r103;
|
|
cvt.u64.u32 %rd59, %r104;
|
|
cvt.u64.u32 %rd60, %r106;
|
|
bfi.b64 %rd61, %rd59, %rd60, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd61;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f472, %fd2;
|
|
setp.eq.s32 %p22, %r102, 0;
|
|
neg.f32 %f473, %f472;
|
|
selp.f32 %f1376, %f472, %f473, %p22;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r31, %r374, 1;
|
|
and.b32 %r32, %r31, 1;
|
|
setp.eq.s32 %p23, %r32, 0;
|
|
selp.f32 %f92, %f1376, 0f3F800000, %p23;
|
|
mul.rn.f32 %f93, %f1376, %f1376;
|
|
mov.f32 %f1377, 0fB94D4153;
|
|
@%p23 bra $L__BB0_18;
|
|
|
|
mov.f32 %f476, 0fBAB607ED;
|
|
mov.f32 %f477, 0f37CBAC00;
|
|
fma.rn.f32 %f1377, %f477, %f93, %f476;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f478, 0f3C0885E4, 0f3D2AAABB, %p23;
|
|
fma.rn.f32 %f479, %f1377, %f93, %f478;
|
|
selp.f32 %f480, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
|
|
fma.rn.f32 %f481, %f479, %f93, %f480;
|
|
mov.f32 %f482, 0f00000000;
|
|
fma.rn.f32 %f483, %f93, %f92, %f482;
|
|
fma.rn.f32 %f1378, %f481, %f483, %f92;
|
|
and.b32 %r108, %r31, 2;
|
|
setp.eq.s32 %p25, %r108, 0;
|
|
@%p25 bra $L__BB0_20;
|
|
|
|
mov.f32 %f485, 0fBF800000;
|
|
fma.rn.f32 %f1378, %f1378, %f485, %f482;
|
|
|
|
$L__BB0_20:
|
|
mul.f32 %f1310, %f86, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r378, %f1310;
|
|
setp.ltu.f32 %p164, %f88, 0f47CE4780;
|
|
@%p164 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p27, %f88, 0f7F800000;
|
|
@%p27 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f488, 0f00000000;
|
|
mul.rn.f32 %f1379, %f86, %f488;
|
|
mov.u32 %r378, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r33, %f86;
|
|
bfe.u32 %r110, %r33, 23, 8;
|
|
add.s32 %r34, %r110, -128;
|
|
shl.b32 %r111, %r33, 8;
|
|
or.b32 %r35, %r111, -2147483648;
|
|
shr.u32 %r36, %r34, 5;
|
|
mov.u64 %rd146, 0;
|
|
mov.u32 %r375, 0;
|
|
mov.u64 %rd147, %rd146;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd64, %rd146, 2;
|
|
mov.u64 %rd65, __cudart_i2opi_f;
|
|
add.s64 %rd66, %rd65, %rd64;
|
|
ld.global.nc.u32 %r112, [%rd66];
|
|
mad.wide.u32 %rd67, %r112, %r35, %rd147;
|
|
shr.u64 %rd147, %rd67, 32;
|
|
add.s64 %rd68, %rd1, %rd64;
|
|
st.local.u32 [%rd68], %rd67;
|
|
add.s32 %r375, %r375, 1;
|
|
cvt.s64.s32 %rd146, %r375;
|
|
setp.ne.s32 %p28, %r375, 6;
|
|
@%p28 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd6], %rd147;
|
|
mov.u32 %r113, 4;
|
|
sub.s32 %r39, %r113, %r36;
|
|
mov.u32 %r114, 6;
|
|
sub.s32 %r115, %r114, %r36;
|
|
mul.wide.s32 %rd69, %r115, 4;
|
|
add.s64 %rd70, %rd1, %rd69;
|
|
ld.local.u32 %r376, [%rd70];
|
|
ld.local.u32 %r377, [%rd70+-4];
|
|
and.b32 %r42, %r34, 31;
|
|
setp.eq.s32 %p29, %r42, 0;
|
|
@%p29 bra $L__BB0_26;
|
|
|
|
mov.u32 %r116, 32;
|
|
sub.s32 %r117, %r116, %r42;
|
|
shr.u32 %r118, %r377, %r117;
|
|
shl.b32 %r119, %r376, %r42;
|
|
add.s32 %r376, %r118, %r119;
|
|
mul.wide.s32 %rd71, %r39, 4;
|
|
add.s64 %rd72, %rd1, %rd71;
|
|
ld.local.u32 %r120, [%rd72];
|
|
shr.u32 %r121, %r120, %r117;
|
|
shl.b32 %r122, %r377, %r42;
|
|
add.s32 %r377, %r121, %r122;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r123, %r33, -2147483648;
|
|
shr.u32 %r124, %r377, 30;
|
|
shl.b32 %r125, %r376, 2;
|
|
or.b32 %r126, %r124, %r125;
|
|
shr.u32 %r127, %r126, 31;
|
|
shr.u32 %r128, %r376, 30;
|
|
add.s32 %r129, %r127, %r128;
|
|
neg.s32 %r130, %r129;
|
|
setp.eq.s32 %p30, %r123, 0;
|
|
selp.b32 %r378, %r129, %r130, %p30;
|
|
setp.ne.s32 %p31, %r127, 0;
|
|
xor.b32 %r131, %r123, -2147483648;
|
|
selp.b32 %r132, %r131, %r123, %p31;
|
|
selp.b32 %r133, -1, 0, %p31;
|
|
xor.b32 %r134, %r126, %r133;
|
|
shl.b32 %r135, %r377, 2;
|
|
xor.b32 %r136, %r135, %r133;
|
|
cvt.u64.u32 %rd73, %r134;
|
|
cvt.u64.u32 %rd74, %r136;
|
|
bfi.b64 %rd75, %rd73, %rd74, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd75;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f486, %fd4;
|
|
setp.eq.s32 %p32, %r132, 0;
|
|
neg.f32 %f487, %f486;
|
|
selp.f32 %f1379, %f486, %f487, %p32;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f102, %f85, %f1378;
|
|
and.b32 %r49, %r378, 1;
|
|
setp.eq.s32 %p33, %r49, 0;
|
|
mul.rn.f32 %f104, %f1379, %f1379;
|
|
mov.f32 %f1380, 0fB94D4153;
|
|
@%p33 bra $L__BB0_30;
|
|
|
|
mov.f32 %f490, 0fBAB607ED;
|
|
mov.f32 %f491, 0f37CBAC00;
|
|
fma.rn.f32 %f1380, %f491, %f104, %f490;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f1312, %f1379, 0f3F800000, %p33;
|
|
selp.f32 %f492, 0f3C0885E4, 0f3D2AAABB, %p33;
|
|
fma.rn.f32 %f493, %f1380, %f104, %f492;
|
|
selp.f32 %f494, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
|
|
fma.rn.f32 %f495, %f493, %f104, %f494;
|
|
mov.f32 %f496, 0f00000000;
|
|
fma.rn.f32 %f497, %f104, %f1312, %f496;
|
|
fma.rn.f32 %f1381, %f495, %f497, %f1312;
|
|
and.b32 %r138, %r378, 2;
|
|
setp.eq.s32 %p35, %r138, 0;
|
|
@%p35 bra $L__BB0_32;
|
|
|
|
mov.f32 %f499, 0fBF800000;
|
|
fma.rn.f32 %f1381, %f1381, %f499, %f496;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f500, %f85, %f1381;
|
|
mul.f32 %f501, %f13, %f500;
|
|
mul.f32 %f502, %f14, %f500;
|
|
mul.f32 %f503, %f15, %f500;
|
|
fma.rn.f32 %f504, %f22, %f102, %f501;
|
|
fma.rn.f32 %f505, %f21, %f102, %f502;
|
|
fma.rn.f32 %f506, %f20, %f102, %f503;
|
|
fma.rn.f32 %f110, %f1313, %f84, %f504;
|
|
fma.rn.f32 %f111, %f1314, %f84, %f505;
|
|
fma.rn.f32 %f112, %f1315, %f84, %f506;
|
|
setp.leu.f32 %p36, %f111, 0f00000000;
|
|
setp.ne.s32 %p37, %r7, 0;
|
|
and.pred %p38, %p37, %p36;
|
|
@%p38 bra $L__BB0_34;
|
|
|
|
mov.f32 %f521, 0f38D1B717;
|
|
max.f32 %f513, %f520, %f521;
|
|
neg.f32 %f522, %f110;
|
|
neg.f32 %f523, %f111;
|
|
neg.f32 %f524, %f112;
|
|
tex.cube.v4.f32.f32 {%f525, %f526, %f527, %f528}, [%rd4, {%f524, %f523, %f522, %f522}];
|
|
mov.b32 %r178, %f525;
|
|
mov.b32 %r179, %f526;
|
|
mov.b32 %r180, %f527;
|
|
mov.f32 %f514, 0f6C4ECB8F;
|
|
mov.f32 %f515, 0f00000000;
|
|
mov.u32 %r175, 2;
|
|
mov.u32 %r176, 1;
|
|
mov.u32 %r177, 3;
|
|
mov.u32 %r209, 0;
|
|
// begin inline asm
|
|
call(%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168,%r169,%r170),_optix_trace_typed_32,(%r209,%rd5,%f10,%f11,%f12,%f110,%f111,%f112,%f513,%f514,%f515,%r176,%r209,%r176,%r175,%r176,%r177,%r178,%r179,%r180,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209,%r209);
|
|
// end inline asm
|
|
mov.b32 %f529, %r139;
|
|
mov.b32 %f530, %r140;
|
|
mov.b32 %f531, %r141;
|
|
mul.f32 %f532, %f1314, %f111;
|
|
fma.rn.f32 %f533, %f1313, %f110, %f532;
|
|
fma.rn.f32 %f534, %f1315, %f112, %f533;
|
|
add.f32 %f1406, %f1406, %f529;
|
|
add.f32 %f1407, %f1407, %f530;
|
|
add.f32 %f1408, %f1408, %f531;
|
|
fma.rn.f32 %f1403, %f111, %f529, %f1403;
|
|
fma.rn.f32 %f1404, %f111, %f530, %f1404;
|
|
fma.rn.f32 %f1405, %f111, %f531, %f1405;
|
|
fma.rn.f32 %f1400, %f112, %f529, %f1400;
|
|
fma.rn.f32 %f1401, %f112, %f530, %f1401;
|
|
fma.rn.f32 %f1402, %f112, %f531, %f1402;
|
|
fma.rn.f32 %f1397, %f110, %f529, %f1397;
|
|
fma.rn.f32 %f1398, %f110, %f530, %f1398;
|
|
fma.rn.f32 %f1399, %f110, %f531, %f1399;
|
|
mul.f32 %f535, %f110, %f111;
|
|
fma.rn.f32 %f1394, %f535, %f529, %f1394;
|
|
fma.rn.f32 %f1395, %f535, %f530, %f1395;
|
|
fma.rn.f32 %f1396, %f535, %f531, %f1396;
|
|
mul.f32 %f536, %f111, %f112;
|
|
fma.rn.f32 %f1391, %f536, %f529, %f1391;
|
|
fma.rn.f32 %f1392, %f536, %f530, %f1392;
|
|
fma.rn.f32 %f1393, %f536, %f531, %f1393;
|
|
fma.rn.f32 %f537, %f112, %f112, 0fBEAAAAAB;
|
|
fma.rn.f32 %f1388, %f537, %f529, %f1388;
|
|
fma.rn.f32 %f1389, %f537, %f530, %f1389;
|
|
fma.rn.f32 %f1390, %f537, %f531, %f1390;
|
|
mul.f32 %f538, %f110, %f112;
|
|
fma.rn.f32 %f1385, %f538, %f529, %f1385;
|
|
fma.rn.f32 %f1386, %f538, %f530, %f1386;
|
|
fma.rn.f32 %f1387, %f538, %f531, %f1387;
|
|
mul.f32 %f539, %f111, %f111;
|
|
mul.f32 %f540, %f110, %f110;
|
|
sub.f32 %f541, %f540, %f539;
|
|
fma.rn.f32 %f1382, %f541, %f529, %f1382;
|
|
fma.rn.f32 %f1383, %f541, %f530, %f1383;
|
|
fma.rn.f32 %f1384, %f541, %f531, %f1384;
|
|
cvt.sat.f32.f32 %f542, %f534;
|
|
fma.rn.f32 %f1409, %f542, %f529, %f1409;
|
|
fma.rn.f32 %f1410, %f542, %f530, %f1410;
|
|
fma.rn.f32 %f1411, %f542, %f531, %f1411;
|
|
|
|
$L__BB0_34:
|
|
add.s32 %r369, %r369, 1;
|
|
setp.lt.s32 %p39, %r369, %r4;
|
|
@%p39 bra $L__BB0_8;
|
|
|
|
add.s32 %r367, %r367, 1;
|
|
setp.lt.s32 %p40, %r367, %r4;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_36:
|
|
mul.lo.s32 %r210, %r4, %r4;
|
|
cvt.rn.f32.s32 %f543, %r210;
|
|
rcp.rn.f32 %f544, %f543;
|
|
mul.f32 %f545, %f544, %f1409;
|
|
mul.f32 %f546, %f544, %f1410;
|
|
mul.f32 %f547, %f544, %f1411;
|
|
mul.f32 %f203, %f544, %f1406;
|
|
mul.f32 %f204, %f544, %f1407;
|
|
mul.f32 %f205, %f544, %f1408;
|
|
mul.f32 %f206, %f544, %f1403;
|
|
mul.f32 %f207, %f544, %f1404;
|
|
mul.f32 %f208, %f544, %f1405;
|
|
mul.f32 %f209, %f544, %f1400;
|
|
mul.f32 %f210, %f544, %f1401;
|
|
mul.f32 %f211, %f544, %f1402;
|
|
mul.f32 %f212, %f544, %f1397;
|
|
mul.f32 %f213, %f544, %f1398;
|
|
mul.f32 %f214, %f544, %f1399;
|
|
mul.f32 %f215, %f544, %f1394;
|
|
mul.f32 %f216, %f544, %f1395;
|
|
mul.f32 %f217, %f544, %f1396;
|
|
mul.f32 %f218, %f544, %f1391;
|
|
mul.f32 %f219, %f544, %f1392;
|
|
mul.f32 %f220, %f544, %f1393;
|
|
mul.f32 %f221, %f544, %f1388;
|
|
mul.f32 %f222, %f544, %f1389;
|
|
mul.f32 %f223, %f544, %f1390;
|
|
mul.f32 %f224, %f544, %f1385;
|
|
mul.f32 %f225, %f544, %f1386;
|
|
mul.f32 %f226, %f544, %f1387;
|
|
mul.f32 %f227, %f544, %f1382;
|
|
mul.f32 %f228, %f544, %f1383;
|
|
mul.f32 %f229, %f544, %f1384;
|
|
fma.rn.f32 %f548, %f544, %f1409, %f545;
|
|
fma.rn.f32 %f549, %f544, %f1410, %f546;
|
|
fma.rn.f32 %f550, %f544, %f1411, %f547;
|
|
ld.const.v4.f32 {%f551, %f552, %f553, %f554}, [params+576];
|
|
mul.f32 %f233, %f548, %f551;
|
|
mul.f32 %f234, %f549, %f552;
|
|
mul.f32 %f235, %f550, %f553;
|
|
ld.const.u32 %r52, [params+104];
|
|
and.b32 %r211, %r52, 1;
|
|
setp.eq.b32 %p41, %r211, 1;
|
|
mov.pred %p42, 0;
|
|
xor.pred %p43, %p41, %p42;
|
|
not.pred %p44, %p43;
|
|
@%p44 bra $L__BB0_110;
|
|
|
|
mov.f32 %f556, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f557, %f556;
|
|
add.f32 %f558, %f557, %f557;
|
|
mov.f32 %f559, 0f3EE66666;
|
|
sub.f32 %f560, %f559, %f558;
|
|
abs.f32 %f236, %f560;
|
|
abs.f32 %f237, %f233;
|
|
setp.lt.f32 %p45, %f237, 0f00800000;
|
|
mul.f32 %f561, %f237, 0f4B800000;
|
|
selp.f32 %f562, %f561, %f237, %p45;
|
|
selp.f32 %f563, 0fC3170000, 0fC2FE0000, %p45;
|
|
mov.b32 %r212, %f562;
|
|
and.b32 %r213, %r212, 8388607;
|
|
or.b32 %r214, %r213, 1065353216;
|
|
mov.b32 %f564, %r214;
|
|
shr.u32 %r215, %r212, 23;
|
|
cvt.rn.f32.u32 %f565, %r215;
|
|
add.f32 %f566, %f563, %f565;
|
|
setp.gt.f32 %p46, %f564, 0f3FB504F3;
|
|
mul.f32 %f567, %f564, 0f3F000000;
|
|
add.f32 %f568, %f566, 0f3F800000;
|
|
selp.f32 %f569, %f568, %f566, %p46;
|
|
selp.f32 %f570, %f567, %f564, %p46;
|
|
add.f32 %f571, %f570, 0fBF800000;
|
|
add.f32 %f572, %f570, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f573, %f572;
|
|
add.f32 %f574, %f571, %f571;
|
|
mul.f32 %f575, %f574, %f573;
|
|
mul.f32 %f576, %f575, %f575;
|
|
mov.f32 %f577, 0f3C4CAF63;
|
|
mov.f32 %f578, 0f3B18F0FE;
|
|
fma.rn.f32 %f579, %f578, %f576, %f577;
|
|
mov.f32 %f580, 0f3DAAAABD;
|
|
fma.rn.f32 %f581, %f579, %f576, %f580;
|
|
mul.rn.f32 %f582, %f581, %f576;
|
|
mul.rn.f32 %f583, %f582, %f575;
|
|
sub.f32 %f584, %f571, %f575;
|
|
add.f32 %f585, %f584, %f584;
|
|
neg.f32 %f586, %f575;
|
|
fma.rn.f32 %f587, %f586, %f571, %f585;
|
|
mul.rn.f32 %f588, %f573, %f587;
|
|
add.f32 %f589, %f583, %f575;
|
|
sub.f32 %f590, %f575, %f589;
|
|
add.f32 %f591, %f583, %f590;
|
|
add.f32 %f592, %f588, %f591;
|
|
add.f32 %f593, %f589, %f592;
|
|
sub.f32 %f594, %f589, %f593;
|
|
add.f32 %f595, %f592, %f594;
|
|
mov.f32 %f596, 0f3F317200;
|
|
mul.rn.f32 %f597, %f569, %f596;
|
|
mov.f32 %f598, 0f35BFBE8E;
|
|
mul.rn.f32 %f599, %f569, %f598;
|
|
add.f32 %f600, %f597, %f593;
|
|
sub.f32 %f601, %f597, %f600;
|
|
add.f32 %f602, %f593, %f601;
|
|
add.f32 %f603, %f595, %f602;
|
|
add.f32 %f604, %f599, %f603;
|
|
add.f32 %f605, %f600, %f604;
|
|
sub.f32 %f606, %f600, %f605;
|
|
add.f32 %f607, %f604, %f606;
|
|
mul.rn.f32 %f608, %f559, %f605;
|
|
neg.f32 %f609, %f608;
|
|
fma.rn.f32 %f610, %f559, %f605, %f609;
|
|
fma.rn.f32 %f611, %f559, %f607, %f610;
|
|
mov.f32 %f612, 0f00000000;
|
|
fma.rn.f32 %f613, %f612, %f605, %f611;
|
|
add.rn.f32 %f614, %f608, %f613;
|
|
neg.f32 %f615, %f614;
|
|
add.rn.f32 %f616, %f608, %f615;
|
|
add.rn.f32 %f617, %f616, %f613;
|
|
mov.b32 %r216, %f614;
|
|
setp.eq.s32 %p47, %r216, 1118925336;
|
|
add.s32 %r217, %r216, -1;
|
|
mov.b32 %f618, %r217;
|
|
add.f32 %f619, %f617, 0f37000000;
|
|
selp.f32 %f238, %f619, %f617, %p47;
|
|
selp.f32 %f620, %f618, %f614, %p47;
|
|
mov.f32 %f621, 0f3FB8AA3B;
|
|
mul.rn.f32 %f622, %f620, %f621;
|
|
cvt.rzi.f32.f32 %f623, %f622;
|
|
abs.f32 %f624, %f623;
|
|
setp.gt.f32 %p48, %f624, 0f42FC0000;
|
|
mov.b32 %r218, %f623;
|
|
and.b32 %r219, %r218, -2147483648;
|
|
or.b32 %r220, %r219, 1123811328;
|
|
mov.b32 %f625, %r220;
|
|
selp.f32 %f626, %f625, %f623, %p48;
|
|
mov.f32 %f627, 0fBF317218;
|
|
fma.rn.f32 %f628, %f626, %f627, %f620;
|
|
mov.f32 %f629, 0f3102E308;
|
|
fma.rn.f32 %f630, %f626, %f629, %f628;
|
|
mul.f32 %f631, %f630, 0f3FB8AA3B;
|
|
add.f32 %f632, %f626, 0f4B40007F;
|
|
mov.b32 %r221, %f632;
|
|
shl.b32 %r222, %r221, 23;
|
|
mov.b32 %f633, %r222;
|
|
ex2.approx.ftz.f32 %f634, %f631;
|
|
mul.f32 %f239, %f634, %f633;
|
|
setp.eq.f32 %p49, %f239, 0f7F800000;
|
|
mov.f32 %f1442, 0f7F800000;
|
|
@%p49 bra $L__BB0_39;
|
|
|
|
fma.rn.f32 %f1442, %f239, %f238, %f239;
|
|
|
|
$L__BB0_39:
|
|
setp.lt.f32 %p50, %f233, 0f00000000;
|
|
setp.eq.f32 %p51, %f236, 0f3F800000;
|
|
and.pred %p1, %p50, %p51;
|
|
setp.eq.f32 %p52, %f233, 0f00000000;
|
|
@%p52 bra $L__BB0_43;
|
|
bra.uni $L__BB0_40;
|
|
|
|
$L__BB0_43:
|
|
add.f32 %f639, %f233, %f233;
|
|
selp.f32 %f1444, %f639, 0f00000000, %p51;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_146:
|
|
mov.f32 %f1228, 0f00000000;
|
|
mov.u32 %r380, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs183, %f1228;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs182, %f1228;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs181, %f1228;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs184, 0;
|
|
st.global.v4.u16 [%rd27], {%rs181, %rs182, %rs183, %rs184};
|
|
|
|
$L__BB0_147:
|
|
ld.const.u64 %rd117, [params+256];
|
|
cvta.to.global.u64 %rd118, %rd117;
|
|
ld.const.u32 %r333, [params+248];
|
|
mad.lo.s32 %r334, %r333, %r6, %r5;
|
|
mul.wide.u32 %rd119, %r334, 8;
|
|
add.s64 %rd28, %rd118, %rd119;
|
|
setp.eq.s32 %p155, %r380, 0;
|
|
@%p155 bra $L__BB0_149;
|
|
|
|
ld.global.v4.u16 {%rs191, %rs192, %rs193, %rs194}, [%rd28];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1229, %rs191;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1230, %rs192;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1231, %rs193;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1232, %f1229, 0f00000000;
|
|
add.f32 %f1233, %f1230, 0f00000000;
|
|
add.f32 %f1234, %f1231, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs190, %f1234;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs189, %f1233;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs188, %f1232;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs195, 0;
|
|
st.global.v4.u16 [%rd28], {%rs188, %rs189, %rs190, %rs195};
|
|
bra.uni $L__BB0_150;
|
|
|
|
$L__BB0_149:
|
|
mov.f32 %f1237, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs198, %f1237;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs197, %f1237;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs196, %f1237;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs199, 0;
|
|
st.global.v4.u16 [%rd28], {%rs196, %rs197, %rs198, %rs199};
|
|
|
|
$L__BB0_150:
|
|
ld.const.u64 %rd120, [params+272];
|
|
cvta.to.global.u64 %rd121, %rd120;
|
|
ld.const.u32 %r335, [params+264];
|
|
mad.lo.s32 %r336, %r335, %r6, %r5;
|
|
mul.wide.u32 %rd122, %r336, 8;
|
|
add.s64 %rd29, %rd121, %rd122;
|
|
@%p155 bra $L__BB0_152;
|
|
|
|
ld.global.v4.u16 {%rs206, %rs207, %rs208, %rs209}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1238, %rs206;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1239, %rs207;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1240, %rs208;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1241, %f1238, 0f00000000;
|
|
add.f32 %f1242, %f1239, 0f00000000;
|
|
add.f32 %f1243, %f1240, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs205, %f1243;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs204, %f1242;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs203, %f1241;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs210, 0;
|
|
st.global.v4.u16 [%rd29], {%rs203, %rs204, %rs205, %rs210};
|
|
bra.uni $L__BB0_153;
|
|
|
|
$L__BB0_152:
|
|
mov.f32 %f1246, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs213, %f1246;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs212, %f1246;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs211, %f1246;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs214, 0;
|
|
st.global.v4.u16 [%rd29], {%rs211, %rs212, %rs213, %rs214};
|
|
|
|
$L__BB0_153:
|
|
ld.const.u64 %rd123, [params+288];
|
|
cvta.to.global.u64 %rd124, %rd123;
|
|
ld.const.u32 %r337, [params+280];
|
|
mad.lo.s32 %r338, %r337, %r6, %r5;
|
|
mul.wide.u32 %rd125, %r338, 8;
|
|
add.s64 %rd30, %rd124, %rd125;
|
|
@%p155 bra $L__BB0_155;
|
|
|
|
ld.global.v4.u16 {%rs221, %rs222, %rs223, %rs224}, [%rd30];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1247, %rs221;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1248, %rs222;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1249, %rs223;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1250, %f1247, 0f00000000;
|
|
add.f32 %f1251, %f1248, 0f00000000;
|
|
add.f32 %f1252, %f1249, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs220, %f1252;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs219, %f1251;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs218, %f1250;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs225, 0;
|
|
st.global.v4.u16 [%rd30], {%rs218, %rs219, %rs220, %rs225};
|
|
bra.uni $L__BB0_156;
|
|
|
|
$L__BB0_155:
|
|
mov.f32 %f1255, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs228, %f1255;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs227, %f1255;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs226, %f1255;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs229, 0;
|
|
st.global.v4.u16 [%rd30], {%rs226, %rs227, %rs228, %rs229};
|
|
|
|
$L__BB0_156:
|
|
ld.const.u64 %rd126, [params+304];
|
|
cvta.to.global.u64 %rd127, %rd126;
|
|
ld.const.u32 %r339, [params+296];
|
|
mad.lo.s32 %r340, %r339, %r6, %r5;
|
|
mul.wide.u32 %rd128, %r340, 8;
|
|
add.s64 %rd31, %rd127, %rd128;
|
|
@%p155 bra $L__BB0_158;
|
|
|
|
ld.global.v4.u16 {%rs236, %rs237, %rs238, %rs239}, [%rd31];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1256, %rs236;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1257, %rs237;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1258, %rs238;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1259, %f1256, 0f00000000;
|
|
add.f32 %f1260, %f1257, 0f00000000;
|
|
add.f32 %f1261, %f1258, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs235, %f1261;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs234, %f1260;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs233, %f1259;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs240, 0;
|
|
st.global.v4.u16 [%rd31], {%rs233, %rs234, %rs235, %rs240};
|
|
bra.uni $L__BB0_159;
|
|
|
|
$L__BB0_158:
|
|
mov.f32 %f1264, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs243, %f1264;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs242, %f1264;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs241, %f1264;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs244, 0;
|
|
st.global.v4.u16 [%rd31], {%rs241, %rs242, %rs243, %rs244};
|
|
|
|
$L__BB0_159:
|
|
ld.const.u64 %rd129, [params+320];
|
|
cvta.to.global.u64 %rd130, %rd129;
|
|
ld.const.u32 %r341, [params+312];
|
|
mad.lo.s32 %r342, %r341, %r6, %r5;
|
|
mul.wide.u32 %rd131, %r342, 8;
|
|
add.s64 %rd32, %rd130, %rd131;
|
|
@%p155 bra $L__BB0_161;
|
|
|
|
ld.global.v4.u16 {%rs251, %rs252, %rs253, %rs254}, [%rd32];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1265, %rs251;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1266, %rs252;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1267, %rs253;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1268, %f1265, 0f00000000;
|
|
add.f32 %f1269, %f1266, 0f00000000;
|
|
add.f32 %f1270, %f1267, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs250, %f1270;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs249, %f1269;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs248, %f1268;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs255, 0;
|
|
st.global.v4.u16 [%rd32], {%rs248, %rs249, %rs250, %rs255};
|
|
bra.uni $L__BB0_162;
|
|
|
|
$L__BB0_161:
|
|
mov.f32 %f1273, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs258, %f1273;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs257, %f1273;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs256, %f1273;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs259, 0;
|
|
st.global.v4.u16 [%rd32], {%rs256, %rs257, %rs258, %rs259};
|
|
|
|
$L__BB0_162:
|
|
ld.const.u64 %rd132, [params+336];
|
|
cvta.to.global.u64 %rd133, %rd132;
|
|
ld.const.u32 %r343, [params+328];
|
|
mad.lo.s32 %r344, %r343, %r6, %r5;
|
|
mul.wide.u32 %rd134, %r344, 8;
|
|
add.s64 %rd33, %rd133, %rd134;
|
|
@%p155 bra $L__BB0_164;
|
|
|
|
ld.global.v4.u16 {%rs266, %rs267, %rs268, %rs269}, [%rd33];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1274, %rs266;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1275, %rs267;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1276, %rs268;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1277, %f1274, 0f00000000;
|
|
add.f32 %f1278, %f1275, 0f00000000;
|
|
add.f32 %f1279, %f1276, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs265, %f1279;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs264, %f1278;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs263, %f1277;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs270, 0;
|
|
st.global.v4.u16 [%rd33], {%rs263, %rs264, %rs265, %rs270};
|
|
bra.uni $L__BB0_165;
|
|
|
|
$L__BB0_164:
|
|
mov.f32 %f1282, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs273, %f1282;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs272, %f1282;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs271, %f1282;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs274, 0;
|
|
st.global.v4.u16 [%rd33], {%rs271, %rs272, %rs273, %rs274};
|
|
|
|
$L__BB0_165:
|
|
ld.const.u64 %rd135, [params+352];
|
|
cvta.to.global.u64 %rd136, %rd135;
|
|
ld.const.u32 %r345, [params+344];
|
|
mad.lo.s32 %r346, %r345, %r6, %r5;
|
|
mul.wide.u32 %rd137, %r346, 8;
|
|
add.s64 %rd34, %rd136, %rd137;
|
|
@%p155 bra $L__BB0_167;
|
|
|
|
ld.global.v4.u16 {%rs281, %rs282, %rs283, %rs284}, [%rd34];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1283, %rs281;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1284, %rs282;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1285, %rs283;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1286, %f1283, 0f00000000;
|
|
add.f32 %f1287, %f1284, 0f00000000;
|
|
add.f32 %f1288, %f1285, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs280, %f1288;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs279, %f1287;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs278, %f1286;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs285, 0;
|
|
st.global.v4.u16 [%rd34], {%rs278, %rs279, %rs280, %rs285};
|
|
bra.uni $L__BB0_168;
|
|
|
|
$L__BB0_167:
|
|
mov.f32 %f1291, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs288, %f1291;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs287, %f1291;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs286, %f1291;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs289, 0;
|
|
st.global.v4.u16 [%rd34], {%rs286, %rs287, %rs288, %rs289};
|
|
|
|
$L__BB0_168:
|
|
ld.const.u64 %rd138, [params+368];
|
|
cvta.to.global.u64 %rd139, %rd138;
|
|
ld.const.u32 %r347, [params+360];
|
|
mad.lo.s32 %r348, %r347, %r6, %r5;
|
|
mul.wide.u32 %rd140, %r348, 8;
|
|
add.s64 %rd35, %rd139, %rd140;
|
|
@%p155 bra $L__BB0_170;
|
|
|
|
ld.global.v4.u16 {%rs296, %rs297, %rs298, %rs299}, [%rd35];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1292, %rs296;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1293, %rs297;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1294, %rs298;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1295, %f1292, 0f00000000;
|
|
add.f32 %f1296, %f1293, 0f00000000;
|
|
add.f32 %f1297, %f1294, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs295, %f1297;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs294, %f1296;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs293, %f1295;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs300, 0;
|
|
st.global.v4.u16 [%rd35], {%rs293, %rs294, %rs295, %rs300};
|
|
bra.uni $L__BB0_171;
|
|
|
|
$L__BB0_170:
|
|
mov.f32 %f1300, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs303, %f1300;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs302, %f1300;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs301, %f1300;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs304, 0;
|
|
st.global.v4.u16 [%rd35], {%rs301, %rs302, %rs303, %rs304};
|
|
|
|
$L__BB0_171:
|
|
ld.const.u64 %rd141, [params+384];
|
|
cvta.to.global.u64 %rd142, %rd141;
|
|
ld.const.u32 %r349, [params+376];
|
|
mad.lo.s32 %r350, %r349, %r6, %r5;
|
|
mul.wide.u32 %rd143, %r350, 8;
|
|
add.s64 %rd36, %rd142, %rd143;
|
|
@%p155 bra $L__BB0_173;
|
|
|
|
ld.global.v4.u16 {%rs311, %rs312, %rs313, %rs314}, [%rd36];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1301, %rs311;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1302, %rs312;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1303, %rs313;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1304, %f1301, 0f00000000;
|
|
add.f32 %f1305, %f1302, 0f00000000;
|
|
add.f32 %f1306, %f1303, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs310, %f1306;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs309, %f1305;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs308, %f1304;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs315, 0;
|
|
st.global.v4.u16 [%rd36], {%rs308, %rs309, %rs310, %rs315};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_173:
|
|
mov.f32 %f1309, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs318, %f1309;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs317, %f1309;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs316, %f1309;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs319, 0;
|
|
st.global.v4.u16 [%rd36], {%rs316, %rs317, %rs318, %rs319};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_40:
|
|
mov.b32 %r223, %f1442;
|
|
xor.b32 %r224, %r223, -2147483648;
|
|
mov.b32 %f635, %r224;
|
|
selp.f32 %f1444, %f635, %f1442, %p1;
|
|
setp.geu.f32 %p53, %f233, 0f00000000;
|
|
@%p53 bra $L__BB0_44;
|
|
|
|
mov.f32 %f636, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f637, %f636;
|
|
setp.eq.f32 %p54, %f637, 0f3EE66666;
|
|
@%p54 bra $L__BB0_44;
|
|
|
|
mov.f32 %f1444, 0f7FFFFFFF;
|
|
|
|
$L__BB0_44:
|
|
add.f32 %f640, %f237, 0f3EE66666;
|
|
mov.b32 %r225, %f640;
|
|
setp.lt.s32 %p56, %r225, 2139095040;
|
|
@%p56 bra $L__BB0_49;
|
|
|
|
setp.gtu.f32 %p57, %f237, 0f7F800000;
|
|
@%p57 bra $L__BB0_48;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f1444, %f233, 0f3EE66666;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_46:
|
|
setp.neu.f32 %p58, %f237, 0f7F800000;
|
|
@%p58 bra $L__BB0_49;
|
|
|
|
selp.f32 %f1444, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_49:
|
|
setp.eq.f32 %p59, %f233, 0f3F800000;
|
|
selp.f32 %f248, 0f3F800000, %f1444, %p59;
|
|
abs.f32 %f249, %f234;
|
|
setp.lt.f32 %p60, %f249, 0f00800000;
|
|
mul.f32 %f642, %f249, 0f4B800000;
|
|
selp.f32 %f643, %f642, %f249, %p60;
|
|
selp.f32 %f644, 0fC3170000, 0fC2FE0000, %p60;
|
|
mov.b32 %r226, %f643;
|
|
and.b32 %r227, %r226, 8388607;
|
|
or.b32 %r228, %r227, 1065353216;
|
|
mov.b32 %f645, %r228;
|
|
shr.u32 %r229, %r226, 23;
|
|
cvt.rn.f32.u32 %f646, %r229;
|
|
add.f32 %f647, %f644, %f646;
|
|
setp.gt.f32 %p61, %f645, 0f3FB504F3;
|
|
mul.f32 %f648, %f645, 0f3F000000;
|
|
add.f32 %f649, %f647, 0f3F800000;
|
|
selp.f32 %f650, %f649, %f647, %p61;
|
|
selp.f32 %f651, %f648, %f645, %p61;
|
|
add.f32 %f652, %f651, 0fBF800000;
|
|
add.f32 %f653, %f651, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f654, %f653;
|
|
add.f32 %f655, %f652, %f652;
|
|
mul.f32 %f656, %f655, %f654;
|
|
mul.f32 %f657, %f656, %f656;
|
|
mov.f32 %f658, 0f3C4CAF63;
|
|
mov.f32 %f659, 0f3B18F0FE;
|
|
fma.rn.f32 %f660, %f659, %f657, %f658;
|
|
mov.f32 %f661, 0f3DAAAABD;
|
|
fma.rn.f32 %f662, %f660, %f657, %f661;
|
|
mul.rn.f32 %f663, %f662, %f657;
|
|
mul.rn.f32 %f664, %f663, %f656;
|
|
sub.f32 %f665, %f652, %f656;
|
|
add.f32 %f666, %f665, %f665;
|
|
neg.f32 %f667, %f656;
|
|
fma.rn.f32 %f668, %f667, %f652, %f666;
|
|
mul.rn.f32 %f669, %f654, %f668;
|
|
add.f32 %f670, %f664, %f656;
|
|
sub.f32 %f671, %f656, %f670;
|
|
add.f32 %f672, %f664, %f671;
|
|
add.f32 %f673, %f669, %f672;
|
|
add.f32 %f674, %f670, %f673;
|
|
sub.f32 %f675, %f670, %f674;
|
|
add.f32 %f676, %f673, %f675;
|
|
mov.f32 %f677, 0f3F317200;
|
|
mul.rn.f32 %f678, %f650, %f677;
|
|
mov.f32 %f679, 0f35BFBE8E;
|
|
mul.rn.f32 %f680, %f650, %f679;
|
|
add.f32 %f681, %f678, %f674;
|
|
sub.f32 %f682, %f678, %f681;
|
|
add.f32 %f683, %f674, %f682;
|
|
add.f32 %f684, %f676, %f683;
|
|
add.f32 %f685, %f680, %f684;
|
|
add.f32 %f686, %f681, %f685;
|
|
sub.f32 %f687, %f681, %f686;
|
|
add.f32 %f688, %f685, %f687;
|
|
mov.f32 %f689, 0f3EE66666;
|
|
mul.rn.f32 %f690, %f689, %f686;
|
|
neg.f32 %f691, %f690;
|
|
fma.rn.f32 %f692, %f689, %f686, %f691;
|
|
fma.rn.f32 %f693, %f689, %f688, %f692;
|
|
mov.f32 %f694, 0f00000000;
|
|
fma.rn.f32 %f695, %f694, %f686, %f693;
|
|
add.rn.f32 %f696, %f690, %f695;
|
|
neg.f32 %f697, %f696;
|
|
add.rn.f32 %f698, %f690, %f697;
|
|
add.rn.f32 %f699, %f698, %f695;
|
|
mov.b32 %r230, %f696;
|
|
setp.eq.s32 %p62, %r230, 1118925336;
|
|
add.s32 %r231, %r230, -1;
|
|
mov.b32 %f700, %r231;
|
|
add.f32 %f701, %f699, 0f37000000;
|
|
selp.f32 %f250, %f701, %f699, %p62;
|
|
selp.f32 %f702, %f700, %f696, %p62;
|
|
mov.f32 %f703, 0f3FB8AA3B;
|
|
mul.rn.f32 %f704, %f702, %f703;
|
|
cvt.rzi.f32.f32 %f705, %f704;
|
|
abs.f32 %f706, %f705;
|
|
setp.gt.f32 %p63, %f706, 0f42FC0000;
|
|
mov.b32 %r232, %f705;
|
|
and.b32 %r233, %r232, -2147483648;
|
|
or.b32 %r234, %r233, 1123811328;
|
|
mov.b32 %f707, %r234;
|
|
selp.f32 %f708, %f707, %f705, %p63;
|
|
mov.f32 %f709, 0fBF317218;
|
|
fma.rn.f32 %f710, %f708, %f709, %f702;
|
|
mov.f32 %f711, 0f3102E308;
|
|
fma.rn.f32 %f712, %f708, %f711, %f710;
|
|
mul.f32 %f713, %f712, 0f3FB8AA3B;
|
|
add.f32 %f714, %f708, 0f4B40007F;
|
|
mov.b32 %r235, %f714;
|
|
shl.b32 %r236, %r235, 23;
|
|
mov.b32 %f715, %r236;
|
|
ex2.approx.ftz.f32 %f716, %f713;
|
|
mul.f32 %f251, %f716, %f715;
|
|
setp.eq.f32 %p64, %f251, 0f7F800000;
|
|
mov.f32 %f1445, 0f7F800000;
|
|
@%p64 bra $L__BB0_51;
|
|
|
|
fma.rn.f32 %f1445, %f251, %f250, %f251;
|
|
|
|
$L__BB0_51:
|
|
setp.lt.f32 %p65, %f234, 0f00000000;
|
|
and.pred %p2, %p65, %p51;
|
|
setp.eq.f32 %p67, %f234, 0f00000000;
|
|
@%p67 bra $L__BB0_55;
|
|
bra.uni $L__BB0_52;
|
|
|
|
$L__BB0_55:
|
|
add.f32 %f721, %f234, %f234;
|
|
selp.f32 %f1447, %f721, 0f00000000, %p51;
|
|
bra.uni $L__BB0_56;
|
|
|
|
$L__BB0_52:
|
|
mov.b32 %r237, %f1445;
|
|
xor.b32 %r238, %r237, -2147483648;
|
|
mov.b32 %f717, %r238;
|
|
selp.f32 %f1447, %f717, %f1445, %p2;
|
|
setp.geu.f32 %p68, %f234, 0f00000000;
|
|
@%p68 bra $L__BB0_56;
|
|
|
|
mov.f32 %f718, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f719, %f718;
|
|
setp.eq.f32 %p69, %f719, 0f3EE66666;
|
|
@%p69 bra $L__BB0_56;
|
|
|
|
mov.f32 %f1447, 0f7FFFFFFF;
|
|
|
|
$L__BB0_56:
|
|
add.f32 %f722, %f249, 0f3EE66666;
|
|
mov.b32 %r239, %f722;
|
|
setp.lt.s32 %p71, %r239, 2139095040;
|
|
@%p71 bra $L__BB0_61;
|
|
|
|
setp.gtu.f32 %p72, %f249, 0f7F800000;
|
|
@%p72 bra $L__BB0_60;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_60:
|
|
add.f32 %f1447, %f234, 0f3EE66666;
|
|
bra.uni $L__BB0_61;
|
|
|
|
$L__BB0_58:
|
|
setp.neu.f32 %p73, %f249, 0f7F800000;
|
|
@%p73 bra $L__BB0_61;
|
|
|
|
selp.f32 %f1447, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_61:
|
|
setp.eq.f32 %p74, %f234, 0f3F800000;
|
|
selp.f32 %f260, 0f3F800000, %f1447, %p74;
|
|
abs.f32 %f261, %f235;
|
|
setp.lt.f32 %p75, %f261, 0f00800000;
|
|
mul.f32 %f724, %f261, 0f4B800000;
|
|
selp.f32 %f725, %f724, %f261, %p75;
|
|
selp.f32 %f726, 0fC3170000, 0fC2FE0000, %p75;
|
|
mov.b32 %r240, %f725;
|
|
and.b32 %r241, %r240, 8388607;
|
|
or.b32 %r242, %r241, 1065353216;
|
|
mov.b32 %f727, %r242;
|
|
shr.u32 %r243, %r240, 23;
|
|
cvt.rn.f32.u32 %f728, %r243;
|
|
add.f32 %f729, %f726, %f728;
|
|
setp.gt.f32 %p76, %f727, 0f3FB504F3;
|
|
mul.f32 %f730, %f727, 0f3F000000;
|
|
add.f32 %f731, %f729, 0f3F800000;
|
|
selp.f32 %f732, %f731, %f729, %p76;
|
|
selp.f32 %f733, %f730, %f727, %p76;
|
|
add.f32 %f734, %f733, 0fBF800000;
|
|
add.f32 %f735, %f733, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f736, %f735;
|
|
add.f32 %f737, %f734, %f734;
|
|
mul.f32 %f738, %f737, %f736;
|
|
mul.f32 %f739, %f738, %f738;
|
|
mov.f32 %f740, 0f3C4CAF63;
|
|
mov.f32 %f741, 0f3B18F0FE;
|
|
fma.rn.f32 %f742, %f741, %f739, %f740;
|
|
mov.f32 %f743, 0f3DAAAABD;
|
|
fma.rn.f32 %f744, %f742, %f739, %f743;
|
|
mul.rn.f32 %f745, %f744, %f739;
|
|
mul.rn.f32 %f746, %f745, %f738;
|
|
sub.f32 %f747, %f734, %f738;
|
|
add.f32 %f748, %f747, %f747;
|
|
neg.f32 %f749, %f738;
|
|
fma.rn.f32 %f750, %f749, %f734, %f748;
|
|
mul.rn.f32 %f751, %f736, %f750;
|
|
add.f32 %f752, %f746, %f738;
|
|
sub.f32 %f753, %f738, %f752;
|
|
add.f32 %f754, %f746, %f753;
|
|
add.f32 %f755, %f751, %f754;
|
|
add.f32 %f756, %f752, %f755;
|
|
sub.f32 %f757, %f752, %f756;
|
|
add.f32 %f758, %f755, %f757;
|
|
mov.f32 %f759, 0f3F317200;
|
|
mul.rn.f32 %f760, %f732, %f759;
|
|
mov.f32 %f761, 0f35BFBE8E;
|
|
mul.rn.f32 %f762, %f732, %f761;
|
|
add.f32 %f763, %f760, %f756;
|
|
sub.f32 %f764, %f760, %f763;
|
|
add.f32 %f765, %f756, %f764;
|
|
add.f32 %f766, %f758, %f765;
|
|
add.f32 %f767, %f762, %f766;
|
|
add.f32 %f768, %f763, %f767;
|
|
sub.f32 %f769, %f763, %f768;
|
|
add.f32 %f770, %f767, %f769;
|
|
mov.f32 %f771, 0f3EE66666;
|
|
mul.rn.f32 %f772, %f771, %f768;
|
|
neg.f32 %f773, %f772;
|
|
fma.rn.f32 %f774, %f771, %f768, %f773;
|
|
fma.rn.f32 %f775, %f771, %f770, %f774;
|
|
mov.f32 %f776, 0f00000000;
|
|
fma.rn.f32 %f777, %f776, %f768, %f775;
|
|
add.rn.f32 %f778, %f772, %f777;
|
|
neg.f32 %f779, %f778;
|
|
add.rn.f32 %f780, %f772, %f779;
|
|
add.rn.f32 %f781, %f780, %f777;
|
|
mov.b32 %r244, %f778;
|
|
setp.eq.s32 %p77, %r244, 1118925336;
|
|
add.s32 %r245, %r244, -1;
|
|
mov.b32 %f782, %r245;
|
|
add.f32 %f783, %f781, 0f37000000;
|
|
selp.f32 %f262, %f783, %f781, %p77;
|
|
selp.f32 %f784, %f782, %f778, %p77;
|
|
mov.f32 %f785, 0f3FB8AA3B;
|
|
mul.rn.f32 %f786, %f784, %f785;
|
|
cvt.rzi.f32.f32 %f787, %f786;
|
|
abs.f32 %f788, %f787;
|
|
setp.gt.f32 %p78, %f788, 0f42FC0000;
|
|
mov.b32 %r246, %f787;
|
|
and.b32 %r247, %r246, -2147483648;
|
|
or.b32 %r248, %r247, 1123811328;
|
|
mov.b32 %f789, %r248;
|
|
selp.f32 %f790, %f789, %f787, %p78;
|
|
mov.f32 %f791, 0fBF317218;
|
|
fma.rn.f32 %f792, %f790, %f791, %f784;
|
|
mov.f32 %f793, 0f3102E308;
|
|
fma.rn.f32 %f794, %f790, %f793, %f792;
|
|
mul.f32 %f795, %f794, 0f3FB8AA3B;
|
|
add.f32 %f796, %f790, 0f4B40007F;
|
|
mov.b32 %r249, %f796;
|
|
shl.b32 %r250, %r249, 23;
|
|
mov.b32 %f797, %r250;
|
|
ex2.approx.ftz.f32 %f798, %f795;
|
|
mul.f32 %f263, %f798, %f797;
|
|
setp.eq.f32 %p79, %f263, 0f7F800000;
|
|
mov.f32 %f1448, 0f7F800000;
|
|
@%p79 bra $L__BB0_63;
|
|
|
|
fma.rn.f32 %f1448, %f263, %f262, %f263;
|
|
|
|
$L__BB0_63:
|
|
setp.lt.f32 %p80, %f235, 0f00000000;
|
|
and.pred %p3, %p80, %p51;
|
|
setp.eq.f32 %p82, %f235, 0f00000000;
|
|
@%p82 bra $L__BB0_67;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_67:
|
|
add.f32 %f803, %f235, %f235;
|
|
selp.f32 %f1450, %f803, 0f00000000, %p51;
|
|
bra.uni $L__BB0_68;
|
|
|
|
$L__BB0_64:
|
|
mov.b32 %r251, %f1448;
|
|
xor.b32 %r252, %r251, -2147483648;
|
|
mov.b32 %f799, %r252;
|
|
selp.f32 %f1450, %f799, %f1448, %p3;
|
|
setp.geu.f32 %p83, %f235, 0f00000000;
|
|
@%p83 bra $L__BB0_68;
|
|
|
|
mov.f32 %f800, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f801, %f800;
|
|
setp.eq.f32 %p84, %f801, 0f3EE66666;
|
|
@%p84 bra $L__BB0_68;
|
|
|
|
mov.f32 %f1450, 0f7FFFFFFF;
|
|
|
|
$L__BB0_68:
|
|
add.f32 %f804, %f261, 0f3EE66666;
|
|
mov.b32 %r253, %f804;
|
|
setp.lt.s32 %p86, %r253, 2139095040;
|
|
@%p86 bra $L__BB0_73;
|
|
|
|
setp.gtu.f32 %p87, %f261, 0f7F800000;
|
|
@%p87 bra $L__BB0_72;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_72:
|
|
add.f32 %f1450, %f235, 0f3EE66666;
|
|
bra.uni $L__BB0_73;
|
|
|
|
$L__BB0_70:
|
|
setp.neu.f32 %p88, %f261, 0f7F800000;
|
|
@%p88 bra $L__BB0_73;
|
|
|
|
selp.f32 %f1450, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_73:
|
|
setp.eq.f32 %p89, %f235, 0f3F800000;
|
|
mov.f32 %f806, 0f3F800000;
|
|
selp.f32 %f807, 0f3F800000, %f1450, %p89;
|
|
ld.const.u64 %rd77, [params+144];
|
|
cvta.to.global.u64 %rd15, %rd77;
|
|
ld.const.u32 %r254, [params+136];
|
|
mad.lo.s32 %r255, %r254, %r6, %r5;
|
|
cvt.u64.u32 %rd16, %r255;
|
|
min.f32 %f808, %f248, %f806;
|
|
mov.f32 %f809, 0f00000000;
|
|
max.f32 %f272, %f809, %f808;
|
|
min.f32 %f810, %f260, %f806;
|
|
max.f32 %f273, %f809, %f810;
|
|
min.f32 %f811, %f807, %f806;
|
|
max.f32 %f274, %f809, %f811;
|
|
mov.f32 %f812, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f813, %f812;
|
|
add.f32 %f814, %f813, %f813;
|
|
mov.f32 %f815, 0f3ED55555;
|
|
sub.f32 %f816, %f815, %f814;
|
|
abs.f32 %f275, %f816;
|
|
abs.f32 %f276, %f272;
|
|
setp.lt.f32 %p90, %f276, 0f00800000;
|
|
mul.f32 %f817, %f276, 0f4B800000;
|
|
selp.f32 %f818, %f817, %f276, %p90;
|
|
selp.f32 %f819, 0fC3170000, 0fC2FE0000, %p90;
|
|
mov.b32 %r256, %f818;
|
|
and.b32 %r257, %r256, 8388607;
|
|
or.b32 %r258, %r257, 1065353216;
|
|
mov.b32 %f820, %r258;
|
|
shr.u32 %r259, %r256, 23;
|
|
cvt.rn.f32.u32 %f821, %r259;
|
|
add.f32 %f822, %f819, %f821;
|
|
setp.gt.f32 %p91, %f820, 0f3FB504F3;
|
|
mul.f32 %f823, %f820, 0f3F000000;
|
|
add.f32 %f824, %f822, 0f3F800000;
|
|
selp.f32 %f825, %f824, %f822, %p91;
|
|
selp.f32 %f826, %f823, %f820, %p91;
|
|
add.f32 %f827, %f826, 0fBF800000;
|
|
add.f32 %f828, %f826, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f829, %f828;
|
|
add.f32 %f830, %f827, %f827;
|
|
mul.f32 %f831, %f830, %f829;
|
|
mul.f32 %f832, %f831, %f831;
|
|
mov.f32 %f833, 0f3C4CAF63;
|
|
mov.f32 %f834, 0f3B18F0FE;
|
|
fma.rn.f32 %f835, %f834, %f832, %f833;
|
|
mov.f32 %f836, 0f3DAAAABD;
|
|
fma.rn.f32 %f837, %f835, %f832, %f836;
|
|
mul.rn.f32 %f838, %f837, %f832;
|
|
mul.rn.f32 %f839, %f838, %f831;
|
|
sub.f32 %f840, %f827, %f831;
|
|
add.f32 %f841, %f840, %f840;
|
|
neg.f32 %f842, %f831;
|
|
fma.rn.f32 %f843, %f842, %f827, %f841;
|
|
mul.rn.f32 %f844, %f829, %f843;
|
|
add.f32 %f845, %f839, %f831;
|
|
sub.f32 %f846, %f831, %f845;
|
|
add.f32 %f847, %f839, %f846;
|
|
add.f32 %f848, %f844, %f847;
|
|
add.f32 %f849, %f845, %f848;
|
|
sub.f32 %f850, %f845, %f849;
|
|
add.f32 %f851, %f848, %f850;
|
|
mov.f32 %f852, 0f3F317200;
|
|
mul.rn.f32 %f853, %f825, %f852;
|
|
mov.f32 %f854, 0f35BFBE8E;
|
|
mul.rn.f32 %f855, %f825, %f854;
|
|
add.f32 %f856, %f853, %f849;
|
|
sub.f32 %f857, %f853, %f856;
|
|
add.f32 %f858, %f849, %f857;
|
|
add.f32 %f859, %f851, %f858;
|
|
add.f32 %f860, %f855, %f859;
|
|
add.f32 %f861, %f856, %f860;
|
|
sub.f32 %f862, %f856, %f861;
|
|
add.f32 %f863, %f860, %f862;
|
|
mul.rn.f32 %f864, %f815, %f861;
|
|
neg.f32 %f865, %f864;
|
|
fma.rn.f32 %f866, %f815, %f861, %f865;
|
|
fma.rn.f32 %f867, %f815, %f863, %f866;
|
|
fma.rn.f32 %f868, %f809, %f861, %f867;
|
|
add.rn.f32 %f869, %f864, %f868;
|
|
neg.f32 %f870, %f869;
|
|
add.rn.f32 %f871, %f864, %f870;
|
|
add.rn.f32 %f872, %f871, %f868;
|
|
mov.b32 %r260, %f869;
|
|
setp.eq.s32 %p92, %r260, 1118925336;
|
|
add.s32 %r261, %r260, -1;
|
|
mov.b32 %f873, %r261;
|
|
add.f32 %f874, %f872, 0f37000000;
|
|
selp.f32 %f277, %f874, %f872, %p92;
|
|
selp.f32 %f875, %f873, %f869, %p92;
|
|
mov.f32 %f876, 0f3FB8AA3B;
|
|
mul.rn.f32 %f877, %f875, %f876;
|
|
cvt.rzi.f32.f32 %f878, %f877;
|
|
abs.f32 %f879, %f878;
|
|
setp.gt.f32 %p93, %f879, 0f42FC0000;
|
|
mov.b32 %r262, %f878;
|
|
and.b32 %r263, %r262, -2147483648;
|
|
or.b32 %r264, %r263, 1123811328;
|
|
mov.b32 %f880, %r264;
|
|
selp.f32 %f881, %f880, %f878, %p93;
|
|
mov.f32 %f882, 0fBF317218;
|
|
fma.rn.f32 %f883, %f881, %f882, %f875;
|
|
mov.f32 %f884, 0f3102E308;
|
|
fma.rn.f32 %f885, %f881, %f884, %f883;
|
|
mul.f32 %f886, %f885, 0f3FB8AA3B;
|
|
add.f32 %f887, %f881, 0f4B40007F;
|
|
mov.b32 %r265, %f887;
|
|
shl.b32 %r266, %r265, 23;
|
|
mov.b32 %f888, %r266;
|
|
ex2.approx.ftz.f32 %f889, %f886;
|
|
mul.f32 %f278, %f889, %f888;
|
|
setp.eq.f32 %p94, %f278, 0f7F800000;
|
|
mov.f32 %f1451, 0f7F800000;
|
|
@%p94 bra $L__BB0_75;
|
|
|
|
fma.rn.f32 %f1451, %f278, %f277, %f278;
|
|
|
|
$L__BB0_75:
|
|
setp.lt.f32 %p95, %f272, 0f00000000;
|
|
setp.eq.f32 %p96, %f275, 0f3F800000;
|
|
and.pred %p4, %p95, %p96;
|
|
setp.eq.f32 %p97, %f272, 0f00000000;
|
|
@%p97 bra $L__BB0_79;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_79:
|
|
add.f32 %f894, %f272, %f272;
|
|
selp.f32 %f1453, %f894, 0f00000000, %p96;
|
|
bra.uni $L__BB0_80;
|
|
|
|
$L__BB0_76:
|
|
mov.b32 %r267, %f1451;
|
|
xor.b32 %r268, %r267, -2147483648;
|
|
mov.b32 %f890, %r268;
|
|
selp.f32 %f1453, %f890, %f1451, %p4;
|
|
setp.geu.f32 %p98, %f272, 0f00000000;
|
|
@%p98 bra $L__BB0_80;
|
|
|
|
mov.f32 %f891, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f892, %f891;
|
|
setp.eq.f32 %p99, %f892, 0f3ED55555;
|
|
@%p99 bra $L__BB0_80;
|
|
|
|
mov.f32 %f1453, 0f7FFFFFFF;
|
|
|
|
$L__BB0_80:
|
|
add.f32 %f895, %f276, 0f3ED55555;
|
|
mov.b32 %r269, %f895;
|
|
setp.lt.s32 %p101, %r269, 2139095040;
|
|
@%p101 bra $L__BB0_85;
|
|
|
|
setp.gtu.f32 %p102, %f276, 0f7F800000;
|
|
@%p102 bra $L__BB0_84;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_84:
|
|
add.f32 %f1453, %f272, 0f3ED55555;
|
|
bra.uni $L__BB0_85;
|
|
|
|
$L__BB0_82:
|
|
setp.neu.f32 %p103, %f276, 0f7F800000;
|
|
@%p103 bra $L__BB0_85;
|
|
|
|
selp.f32 %f1453, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_85:
|
|
abs.f32 %f287, %f273;
|
|
setp.lt.f32 %p104, %f287, 0f00800000;
|
|
mul.f32 %f897, %f287, 0f4B800000;
|
|
selp.f32 %f898, %f897, %f287, %p104;
|
|
selp.f32 %f899, 0fC3170000, 0fC2FE0000, %p104;
|
|
mov.b32 %r270, %f898;
|
|
and.b32 %r271, %r270, 8388607;
|
|
or.b32 %r272, %r271, 1065353216;
|
|
mov.b32 %f900, %r272;
|
|
shr.u32 %r273, %r270, 23;
|
|
cvt.rn.f32.u32 %f901, %r273;
|
|
add.f32 %f902, %f899, %f901;
|
|
setp.gt.f32 %p105, %f900, 0f3FB504F3;
|
|
mul.f32 %f903, %f900, 0f3F000000;
|
|
add.f32 %f904, %f902, 0f3F800000;
|
|
selp.f32 %f905, %f904, %f902, %p105;
|
|
selp.f32 %f906, %f903, %f900, %p105;
|
|
add.f32 %f907, %f906, 0fBF800000;
|
|
add.f32 %f908, %f906, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f909, %f908;
|
|
add.f32 %f910, %f907, %f907;
|
|
mul.f32 %f911, %f910, %f909;
|
|
mul.f32 %f912, %f911, %f911;
|
|
mov.f32 %f913, 0f3C4CAF63;
|
|
mov.f32 %f914, 0f3B18F0FE;
|
|
fma.rn.f32 %f915, %f914, %f912, %f913;
|
|
mov.f32 %f916, 0f3DAAAABD;
|
|
fma.rn.f32 %f917, %f915, %f912, %f916;
|
|
mul.rn.f32 %f918, %f917, %f912;
|
|
mul.rn.f32 %f919, %f918, %f911;
|
|
sub.f32 %f920, %f907, %f911;
|
|
add.f32 %f921, %f920, %f920;
|
|
neg.f32 %f922, %f911;
|
|
fma.rn.f32 %f923, %f922, %f907, %f921;
|
|
mul.rn.f32 %f924, %f909, %f923;
|
|
add.f32 %f925, %f919, %f911;
|
|
sub.f32 %f926, %f911, %f925;
|
|
add.f32 %f927, %f919, %f926;
|
|
add.f32 %f928, %f924, %f927;
|
|
add.f32 %f929, %f925, %f928;
|
|
sub.f32 %f930, %f925, %f929;
|
|
add.f32 %f931, %f928, %f930;
|
|
mov.f32 %f932, 0f3F317200;
|
|
mul.rn.f32 %f933, %f905, %f932;
|
|
mov.f32 %f934, 0f35BFBE8E;
|
|
mul.rn.f32 %f935, %f905, %f934;
|
|
add.f32 %f936, %f933, %f929;
|
|
sub.f32 %f937, %f933, %f936;
|
|
add.f32 %f938, %f929, %f937;
|
|
add.f32 %f939, %f931, %f938;
|
|
add.f32 %f940, %f935, %f939;
|
|
add.f32 %f941, %f936, %f940;
|
|
sub.f32 %f942, %f936, %f941;
|
|
add.f32 %f943, %f940, %f942;
|
|
mov.f32 %f944, 0f3ED55555;
|
|
mul.rn.f32 %f945, %f944, %f941;
|
|
neg.f32 %f946, %f945;
|
|
fma.rn.f32 %f947, %f944, %f941, %f946;
|
|
fma.rn.f32 %f948, %f944, %f943, %f947;
|
|
mov.f32 %f949, 0f00000000;
|
|
fma.rn.f32 %f950, %f949, %f941, %f948;
|
|
add.rn.f32 %f951, %f945, %f950;
|
|
neg.f32 %f952, %f951;
|
|
add.rn.f32 %f953, %f945, %f952;
|
|
add.rn.f32 %f954, %f953, %f950;
|
|
mov.b32 %r274, %f951;
|
|
setp.eq.s32 %p106, %r274, 1118925336;
|
|
add.s32 %r275, %r274, -1;
|
|
mov.b32 %f955, %r275;
|
|
add.f32 %f956, %f954, 0f37000000;
|
|
selp.f32 %f288, %f956, %f954, %p106;
|
|
selp.f32 %f957, %f955, %f951, %p106;
|
|
mov.f32 %f958, 0f3FB8AA3B;
|
|
mul.rn.f32 %f959, %f957, %f958;
|
|
cvt.rzi.f32.f32 %f960, %f959;
|
|
abs.f32 %f961, %f960;
|
|
setp.gt.f32 %p107, %f961, 0f42FC0000;
|
|
mov.b32 %r276, %f960;
|
|
and.b32 %r277, %r276, -2147483648;
|
|
or.b32 %r278, %r277, 1123811328;
|
|
mov.b32 %f962, %r278;
|
|
selp.f32 %f963, %f962, %f960, %p107;
|
|
mov.f32 %f964, 0fBF317218;
|
|
fma.rn.f32 %f965, %f963, %f964, %f957;
|
|
mov.f32 %f966, 0f3102E308;
|
|
fma.rn.f32 %f967, %f963, %f966, %f965;
|
|
mul.f32 %f968, %f967, 0f3FB8AA3B;
|
|
add.f32 %f969, %f963, 0f4B40007F;
|
|
mov.b32 %r279, %f969;
|
|
shl.b32 %r280, %r279, 23;
|
|
mov.b32 %f970, %r280;
|
|
ex2.approx.ftz.f32 %f971, %f968;
|
|
mul.f32 %f289, %f971, %f970;
|
|
setp.eq.f32 %p108, %f289, 0f7F800000;
|
|
mov.f32 %f1454, 0f7F800000;
|
|
@%p108 bra $L__BB0_87;
|
|
|
|
fma.rn.f32 %f1454, %f289, %f288, %f289;
|
|
|
|
$L__BB0_87:
|
|
setp.lt.f32 %p109, %f273, 0f00000000;
|
|
and.pred %p5, %p109, %p96;
|
|
setp.eq.f32 %p111, %f273, 0f00000000;
|
|
@%p111 bra $L__BB0_91;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_91:
|
|
add.f32 %f976, %f273, %f273;
|
|
selp.f32 %f1456, %f976, 0f00000000, %p96;
|
|
bra.uni $L__BB0_92;
|
|
|
|
$L__BB0_88:
|
|
mov.b32 %r281, %f1454;
|
|
xor.b32 %r282, %r281, -2147483648;
|
|
mov.b32 %f972, %r282;
|
|
selp.f32 %f1456, %f972, %f1454, %p5;
|
|
setp.geu.f32 %p112, %f273, 0f00000000;
|
|
@%p112 bra $L__BB0_92;
|
|
|
|
mov.f32 %f973, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f974, %f973;
|
|
setp.eq.f32 %p113, %f974, 0f3ED55555;
|
|
@%p113 bra $L__BB0_92;
|
|
|
|
mov.f32 %f1456, 0f7FFFFFFF;
|
|
|
|
$L__BB0_92:
|
|
add.f32 %f977, %f287, 0f3ED55555;
|
|
mov.b32 %r283, %f977;
|
|
setp.lt.s32 %p115, %r283, 2139095040;
|
|
@%p115 bra $L__BB0_97;
|
|
|
|
setp.gtu.f32 %p116, %f287, 0f7F800000;
|
|
@%p116 bra $L__BB0_96;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_96:
|
|
add.f32 %f1456, %f273, 0f3ED55555;
|
|
bra.uni $L__BB0_97;
|
|
|
|
$L__BB0_94:
|
|
setp.neu.f32 %p117, %f287, 0f7F800000;
|
|
@%p117 bra $L__BB0_97;
|
|
|
|
selp.f32 %f1456, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_97:
|
|
abs.f32 %f298, %f274;
|
|
setp.lt.f32 %p118, %f298, 0f00800000;
|
|
mul.f32 %f979, %f298, 0f4B800000;
|
|
selp.f32 %f980, %f979, %f298, %p118;
|
|
selp.f32 %f981, 0fC3170000, 0fC2FE0000, %p118;
|
|
mov.b32 %r284, %f980;
|
|
and.b32 %r285, %r284, 8388607;
|
|
or.b32 %r286, %r285, 1065353216;
|
|
mov.b32 %f982, %r286;
|
|
shr.u32 %r287, %r284, 23;
|
|
cvt.rn.f32.u32 %f983, %r287;
|
|
add.f32 %f984, %f981, %f983;
|
|
setp.gt.f32 %p119, %f982, 0f3FB504F3;
|
|
mul.f32 %f985, %f982, 0f3F000000;
|
|
add.f32 %f986, %f984, 0f3F800000;
|
|
selp.f32 %f987, %f986, %f984, %p119;
|
|
selp.f32 %f988, %f985, %f982, %p119;
|
|
add.f32 %f989, %f988, 0fBF800000;
|
|
add.f32 %f990, %f988, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f991, %f990;
|
|
add.f32 %f992, %f989, %f989;
|
|
mul.f32 %f993, %f992, %f991;
|
|
mul.f32 %f994, %f993, %f993;
|
|
mov.f32 %f995, 0f3C4CAF63;
|
|
mov.f32 %f996, 0f3B18F0FE;
|
|
fma.rn.f32 %f997, %f996, %f994, %f995;
|
|
mov.f32 %f998, 0f3DAAAABD;
|
|
fma.rn.f32 %f999, %f997, %f994, %f998;
|
|
mul.rn.f32 %f1000, %f999, %f994;
|
|
mul.rn.f32 %f1001, %f1000, %f993;
|
|
sub.f32 %f1002, %f989, %f993;
|
|
add.f32 %f1003, %f1002, %f1002;
|
|
neg.f32 %f1004, %f993;
|
|
fma.rn.f32 %f1005, %f1004, %f989, %f1003;
|
|
mul.rn.f32 %f1006, %f991, %f1005;
|
|
add.f32 %f1007, %f1001, %f993;
|
|
sub.f32 %f1008, %f993, %f1007;
|
|
add.f32 %f1009, %f1001, %f1008;
|
|
add.f32 %f1010, %f1006, %f1009;
|
|
add.f32 %f1011, %f1007, %f1010;
|
|
sub.f32 %f1012, %f1007, %f1011;
|
|
add.f32 %f1013, %f1010, %f1012;
|
|
mov.f32 %f1014, 0f3F317200;
|
|
mul.rn.f32 %f1015, %f987, %f1014;
|
|
mov.f32 %f1016, 0f35BFBE8E;
|
|
mul.rn.f32 %f1017, %f987, %f1016;
|
|
add.f32 %f1018, %f1015, %f1011;
|
|
sub.f32 %f1019, %f1015, %f1018;
|
|
add.f32 %f1020, %f1011, %f1019;
|
|
add.f32 %f1021, %f1013, %f1020;
|
|
add.f32 %f1022, %f1017, %f1021;
|
|
add.f32 %f1023, %f1018, %f1022;
|
|
sub.f32 %f1024, %f1018, %f1023;
|
|
add.f32 %f1025, %f1022, %f1024;
|
|
mov.f32 %f1026, 0f3ED55555;
|
|
mul.rn.f32 %f1027, %f1026, %f1023;
|
|
neg.f32 %f1028, %f1027;
|
|
fma.rn.f32 %f1029, %f1026, %f1023, %f1028;
|
|
fma.rn.f32 %f1030, %f1026, %f1025, %f1029;
|
|
mov.f32 %f1031, 0f00000000;
|
|
fma.rn.f32 %f1032, %f1031, %f1023, %f1030;
|
|
add.rn.f32 %f1033, %f1027, %f1032;
|
|
neg.f32 %f1034, %f1033;
|
|
add.rn.f32 %f1035, %f1027, %f1034;
|
|
add.rn.f32 %f1036, %f1035, %f1032;
|
|
mov.b32 %r288, %f1033;
|
|
setp.eq.s32 %p120, %r288, 1118925336;
|
|
add.s32 %r289, %r288, -1;
|
|
mov.b32 %f1037, %r289;
|
|
add.f32 %f1038, %f1036, 0f37000000;
|
|
selp.f32 %f299, %f1038, %f1036, %p120;
|
|
selp.f32 %f1039, %f1037, %f1033, %p120;
|
|
mov.f32 %f1040, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1041, %f1039, %f1040;
|
|
cvt.rzi.f32.f32 %f1042, %f1041;
|
|
abs.f32 %f1043, %f1042;
|
|
setp.gt.f32 %p121, %f1043, 0f42FC0000;
|
|
mov.b32 %r290, %f1042;
|
|
and.b32 %r291, %r290, -2147483648;
|
|
or.b32 %r292, %r291, 1123811328;
|
|
mov.b32 %f1044, %r292;
|
|
selp.f32 %f1045, %f1044, %f1042, %p121;
|
|
mov.f32 %f1046, 0fBF317218;
|
|
fma.rn.f32 %f1047, %f1045, %f1046, %f1039;
|
|
mov.f32 %f1048, 0f3102E308;
|
|
fma.rn.f32 %f1049, %f1045, %f1048, %f1047;
|
|
mul.f32 %f1050, %f1049, 0f3FB8AA3B;
|
|
add.f32 %f1051, %f1045, 0f4B40007F;
|
|
mov.b32 %r293, %f1051;
|
|
shl.b32 %r294, %r293, 23;
|
|
mov.b32 %f1052, %r294;
|
|
ex2.approx.ftz.f32 %f1053, %f1050;
|
|
mul.f32 %f300, %f1053, %f1052;
|
|
setp.eq.f32 %p122, %f300, 0f7F800000;
|
|
mov.f32 %f1457, 0f7F800000;
|
|
@%p122 bra $L__BB0_99;
|
|
|
|
fma.rn.f32 %f1457, %f300, %f299, %f300;
|
|
|
|
$L__BB0_99:
|
|
setp.lt.f32 %p123, %f274, 0f00000000;
|
|
and.pred %p6, %p123, %p96;
|
|
setp.eq.f32 %p125, %f274, 0f00000000;
|
|
@%p125 bra $L__BB0_103;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_103:
|
|
add.f32 %f1058, %f274, %f274;
|
|
selp.f32 %f1459, %f1058, 0f00000000, %p96;
|
|
bra.uni $L__BB0_104;
|
|
|
|
$L__BB0_100:
|
|
mov.b32 %r295, %f1457;
|
|
xor.b32 %r296, %r295, -2147483648;
|
|
mov.b32 %f1054, %r296;
|
|
selp.f32 %f1459, %f1054, %f1457, %p6;
|
|
setp.geu.f32 %p126, %f274, 0f00000000;
|
|
@%p126 bra $L__BB0_104;
|
|
|
|
mov.f32 %f1055, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1056, %f1055;
|
|
setp.eq.f32 %p127, %f1056, 0f3ED55555;
|
|
@%p127 bra $L__BB0_104;
|
|
|
|
mov.f32 %f1459, 0f7FFFFFFF;
|
|
|
|
$L__BB0_104:
|
|
add.f32 %f1059, %f298, 0f3ED55555;
|
|
mov.b32 %r297, %f1059;
|
|
setp.lt.s32 %p129, %r297, 2139095040;
|
|
@%p129 bra $L__BB0_109;
|
|
|
|
setp.gtu.f32 %p130, %f298, 0f7F800000;
|
|
@%p130 bra $L__BB0_108;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_108:
|
|
add.f32 %f1459, %f274, 0f3ED55555;
|
|
bra.uni $L__BB0_109;
|
|
|
|
$L__BB0_106:
|
|
setp.neu.f32 %p131, %f298, 0f7F800000;
|
|
@%p131 bra $L__BB0_109;
|
|
|
|
selp.f32 %f1459, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_109:
|
|
fma.rn.f32 %f1060, %f1453, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p132, %f272, 0f3F800000;
|
|
mov.f32 %f1061, 0f3F800000;
|
|
selp.f32 %f1062, 0f3F7FFFFF, %f1060, %p132;
|
|
mul.f32 %f1063, %f272, 0f414EB852;
|
|
setp.lt.f32 %p133, %f272, 0f3B4D2E1C;
|
|
selp.f32 %f1064, %f1063, %f1062, %p133;
|
|
fma.rn.f32 %f1065, %f1456, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p134, %f273, 0f3F800000;
|
|
selp.f32 %f1066, 0f3F7FFFFF, %f1065, %p134;
|
|
mul.f32 %f1067, %f273, 0f414EB852;
|
|
setp.lt.f32 %p135, %f273, 0f3B4D2E1C;
|
|
selp.f32 %f1068, %f1067, %f1066, %p135;
|
|
fma.rn.f32 %f1069, %f1459, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p136, %f274, 0f3F800000;
|
|
selp.f32 %f1070, 0f3F7FFFFF, %f1069, %p136;
|
|
mul.f32 %f1071, %f274, 0f414EB852;
|
|
setp.lt.f32 %p137, %f274, 0f3B4D2E1C;
|
|
selp.f32 %f1072, %f1071, %f1070, %p137;
|
|
min.f32 %f1073, %f1064, %f1061;
|
|
mov.f32 %f1074, 0f00000000;
|
|
max.f32 %f1075, %f1074, %f1073;
|
|
mul.f32 %f1076, %f1075, 0f43800000;
|
|
cvt.rzi.u32.f32 %r298, %f1076;
|
|
min.u32 %r299, %r298, 255;
|
|
min.f32 %f1077, %f1068, %f1061;
|
|
max.f32 %f1078, %f1074, %f1077;
|
|
mul.f32 %f1079, %f1078, 0f43800000;
|
|
cvt.rzi.u32.f32 %r300, %f1079;
|
|
min.u32 %r301, %r300, 255;
|
|
min.f32 %f1080, %f1072, %f1061;
|
|
max.f32 %f1081, %f1074, %f1080;
|
|
mul.f32 %f1082, %f1081, 0f43800000;
|
|
cvt.rzi.u32.f32 %r302, %f1082;
|
|
min.u32 %r303, %r302, 255;
|
|
shl.b64 %rd78, %rd16, 2;
|
|
add.s64 %rd79, %rd15, %rd78;
|
|
cvt.u16.u32 %rs15, %r303;
|
|
cvt.u16.u32 %rs16, %r301;
|
|
cvt.u16.u32 %rs17, %r299;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v4.u8 [%rd79], {%rs17, %rs16, %rs15, %rs18};
|
|
|
|
$L__BB0_110:
|
|
and.b32 %r304, %r52, 4;
|
|
setp.eq.s32 %p138, %r304, 0;
|
|
ld.const.u32 %r379, [params+108];
|
|
@%p138 bra $L__BB0_114;
|
|
|
|
setp.eq.s32 %p139, %r379, 0;
|
|
ld.const.u64 %rd80, [params+224];
|
|
cvta.to.global.u64 %rd81, %rd80;
|
|
ld.const.u32 %r305, [params+216];
|
|
mad.lo.s32 %r306, %r305, %r6, %r5;
|
|
mul.wide.u32 %rd82, %r306, 8;
|
|
add.s64 %rd17, %rd81, %rd82;
|
|
@%p139 bra $L__BB0_113;
|
|
|
|
ld.global.v4.u16 {%rs26, %rs27, %rs28, %rs29}, [%rd17];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1083, %rs26;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1084, %rs27;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1085, %rs28;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1086, %f233, %f1083;
|
|
add.f32 %f1087, %f234, %f1084;
|
|
add.f32 %f1088, %f235, %f1085;
|
|
mov.f32 %f1089, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs24, %f1088;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs23, %f1087;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs22, %f1086;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs25, %f1089;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd17], {%rs22, %rs23, %rs24, %rs25};
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_113:
|
|
mov.f32 %f1093, 0f3F800000;
|
|
mov.u32 %r379, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f1093;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs32, %f235;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs31, %f234;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f233;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd17], {%rs30, %rs31, %rs32, %rs33};
|
|
|
|
$L__BB0_114:
|
|
mul.f32 %f309, %f551, 0f40800000;
|
|
mul.f32 %f1094, %f203, %f309;
|
|
mul.f32 %f310, %f552, 0f40800000;
|
|
mul.f32 %f1095, %f204, %f310;
|
|
mul.f32 %f311, %f553, 0f40800000;
|
|
mul.f32 %f1096, %f205, %f311;
|
|
mul.f32 %f312, %f1094, 0f3F558750;
|
|
mul.f32 %f313, %f1095, 0f3F558750;
|
|
mul.f32 %f314, %f1096, 0f3F558750;
|
|
ld.const.u64 %rd83, [params+256];
|
|
cvta.to.global.u64 %rd84, %rd83;
|
|
ld.const.u32 %r308, [params+248];
|
|
mad.lo.s32 %r309, %r308, %r6, %r5;
|
|
mul.wide.u32 %rd85, %r309, 8;
|
|
add.s64 %rd18, %rd84, %rd85;
|
|
setp.eq.s32 %p140, %r379, 0;
|
|
@%p140 bra $L__BB0_116;
|
|
|
|
ld.global.v4.u16 {%rs41, %rs42, %rs43, %rs44}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1097, %rs41;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1098, %rs42;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1099, %rs43;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1100, %f312, %f1097;
|
|
add.f32 %f1101, %f313, %f1098;
|
|
add.f32 %f1102, %f314, %f1099;
|
|
mov.f32 %f1103, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs39, %f1102;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f1101;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f1100;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f1103;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs37, %rs38, %rs39, %rs40};
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_116:
|
|
mov.f32 %f1107, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f1107;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs47, %f314;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs46, %f313;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs45, %f312;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs45, %rs46, %rs47, %rs48};
|
|
|
|
$L__BB0_117:
|
|
mul.f32 %f1108, %f206, %f309;
|
|
mul.f32 %f315, %f1108, 0f3FB8EBD1;
|
|
mul.f32 %f1109, %f207, %f310;
|
|
mul.f32 %f316, %f1109, 0f3FB8EBD1;
|
|
mul.f32 %f1110, %f208, %f311;
|
|
mul.f32 %f317, %f1110, 0f3FB8EBD1;
|
|
ld.const.u64 %rd86, [params+272];
|
|
cvta.to.global.u64 %rd87, %rd86;
|
|
ld.const.u32 %r310, [params+264];
|
|
mad.lo.s32 %r311, %r310, %r6, %r5;
|
|
mul.wide.u32 %rd88, %r311, 8;
|
|
add.s64 %rd19, %rd87, %rd88;
|
|
@%p140 bra $L__BB0_119;
|
|
|
|
ld.global.v4.u16 {%rs56, %rs57, %rs58, %rs59}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1111, %rs56;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1112, %rs57;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1113, %rs58;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1114, %f315, %f1111;
|
|
add.f32 %f1115, %f316, %f1112;
|
|
add.f32 %f1116, %f317, %f1113;
|
|
mov.f32 %f1117, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f1116;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f1115;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f1114;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f1117;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs52, %rs53, %rs54, %rs55};
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_119:
|
|
mov.f32 %f1121, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f1121;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f317;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f316;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f315;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs60, %rs61, %rs62, %rs63};
|
|
|
|
$L__BB0_120:
|
|
mul.f32 %f1122, %f209, %f309;
|
|
mul.f32 %f318, %f1122, 0f3FB8EBD1;
|
|
mul.f32 %f1123, %f210, %f310;
|
|
mul.f32 %f319, %f1123, 0f3FB8EBD1;
|
|
mul.f32 %f1124, %f211, %f311;
|
|
mul.f32 %f320, %f1124, 0f3FB8EBD1;
|
|
ld.const.u64 %rd89, [params+288];
|
|
cvta.to.global.u64 %rd90, %rd89;
|
|
ld.const.u32 %r312, [params+280];
|
|
mad.lo.s32 %r313, %r312, %r6, %r5;
|
|
mul.wide.u32 %rd91, %r313, 8;
|
|
add.s64 %rd20, %rd90, %rd91;
|
|
@%p140 bra $L__BB0_122;
|
|
|
|
ld.global.v4.u16 {%rs71, %rs72, %rs73, %rs74}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1125, %rs71;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1126, %rs72;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1127, %rs73;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1128, %f318, %f1125;
|
|
add.f32 %f1129, %f319, %f1126;
|
|
add.f32 %f1130, %f320, %f1127;
|
|
mov.f32 %f1131, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f1130;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1129;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f1128;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1131;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs67, %rs68, %rs69, %rs70};
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_122:
|
|
mov.f32 %f1135, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f1135;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f320;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f319;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f318;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs75, %rs76, %rs77, %rs78};
|
|
|
|
$L__BB0_123:
|
|
mul.f32 %f1136, %f212, %f309;
|
|
mul.f32 %f321, %f1136, 0f3FB8EBD1;
|
|
mul.f32 %f1137, %f213, %f310;
|
|
mul.f32 %f322, %f1137, 0f3FB8EBD1;
|
|
mul.f32 %f1138, %f214, %f311;
|
|
mul.f32 %f323, %f1138, 0f3FB8EBD1;
|
|
ld.const.u64 %rd92, [params+304];
|
|
cvta.to.global.u64 %rd93, %rd92;
|
|
ld.const.u32 %r314, [params+296];
|
|
mad.lo.s32 %r315, %r314, %r6, %r5;
|
|
mul.wide.u32 %rd94, %r315, 8;
|
|
add.s64 %rd21, %rd93, %rd94;
|
|
@%p140 bra $L__BB0_125;
|
|
|
|
ld.global.v4.u16 {%rs86, %rs87, %rs88, %rs89}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1139, %rs86;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1140, %rs87;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1141, %rs88;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1142, %f321, %f1139;
|
|
add.f32 %f1143, %f322, %f1140;
|
|
add.f32 %f1144, %f323, %f1141;
|
|
mov.f32 %f1145, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1144;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1143;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f1142;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1145;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs82, %rs83, %rs84, %rs85};
|
|
bra.uni $L__BB0_126;
|
|
|
|
$L__BB0_125:
|
|
mov.f32 %f1149, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f1149;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f323;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f322;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f321;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs90, %rs91, %rs92, %rs93};
|
|
|
|
$L__BB0_126:
|
|
mul.f32 %f1150, %f215, %f309;
|
|
mul.f32 %f324, %f1150, 0f404EBF87;
|
|
mul.f32 %f1151, %f216, %f310;
|
|
mul.f32 %f325, %f1151, 0f404EBF87;
|
|
mul.f32 %f1152, %f217, %f311;
|
|
mul.f32 %f326, %f1152, 0f404EBF87;
|
|
ld.const.u64 %rd95, [params+320];
|
|
cvta.to.global.u64 %rd96, %rd95;
|
|
ld.const.u32 %r316, [params+312];
|
|
mad.lo.s32 %r317, %r316, %r6, %r5;
|
|
mul.wide.u32 %rd97, %r317, 8;
|
|
add.s64 %rd22, %rd96, %rd97;
|
|
@%p140 bra $L__BB0_128;
|
|
|
|
ld.global.v4.u16 {%rs101, %rs102, %rs103, %rs104}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1153, %rs101;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1154, %rs102;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1155, %rs103;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1156, %f324, %f1153;
|
|
add.f32 %f1157, %f325, %f1154;
|
|
add.f32 %f1158, %f326, %f1155;
|
|
mov.f32 %f1159, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs99, %f1158;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs98, %f1157;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f1156;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs100, %f1159;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs97, %rs98, %rs99, %rs100};
|
|
bra.uni $L__BB0_129;
|
|
|
|
$L__BB0_128:
|
|
mov.f32 %f1163, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f1163;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f326;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f325;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs105, %f324;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs105, %rs106, %rs107, %rs108};
|
|
|
|
$L__BB0_129:
|
|
mul.f32 %f1164, %f218, %f309;
|
|
mul.f32 %f327, %f1164, 0f404EBF87;
|
|
mul.f32 %f1165, %f219, %f310;
|
|
mul.f32 %f328, %f1165, 0f404EBF87;
|
|
mul.f32 %f1166, %f220, %f311;
|
|
mul.f32 %f329, %f1166, 0f404EBF87;
|
|
ld.const.u64 %rd98, [params+336];
|
|
cvta.to.global.u64 %rd99, %rd98;
|
|
ld.const.u32 %r318, [params+328];
|
|
mad.lo.s32 %r319, %r318, %r6, %r5;
|
|
mul.wide.u32 %rd100, %r319, 8;
|
|
add.s64 %rd23, %rd99, %rd100;
|
|
@%p140 bra $L__BB0_131;
|
|
|
|
ld.global.v4.u16 {%rs116, %rs117, %rs118, %rs119}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1167, %rs116;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1168, %rs117;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1169, %rs118;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1170, %f327, %f1167;
|
|
add.f32 %f1171, %f328, %f1168;
|
|
add.f32 %f1172, %f329, %f1169;
|
|
mov.f32 %f1173, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f1172;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1171;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs112, %f1170;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1173;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs112, %rs113, %rs114, %rs115};
|
|
bra.uni $L__BB0_132;
|
|
|
|
$L__BB0_131:
|
|
mov.f32 %f1177, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f1177;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f329;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f328;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f327;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs120, %rs121, %rs122, %rs123};
|
|
|
|
$L__BB0_132:
|
|
mul.f32 %f1178, %f221, %f309;
|
|
mul.f32 %f330, %f1178, 0f40330C94;
|
|
mul.f32 %f1179, %f222, %f310;
|
|
mul.f32 %f331, %f1179, 0f40330C94;
|
|
mul.f32 %f1180, %f223, %f311;
|
|
mul.f32 %f332, %f1180, 0f40330C94;
|
|
ld.const.u64 %rd101, [params+352];
|
|
cvta.to.global.u64 %rd102, %rd101;
|
|
ld.const.u32 %r320, [params+344];
|
|
mad.lo.s32 %r321, %r320, %r6, %r5;
|
|
mul.wide.u32 %rd103, %r321, 8;
|
|
add.s64 %rd24, %rd102, %rd103;
|
|
@%p140 bra $L__BB0_134;
|
|
|
|
ld.global.v4.u16 {%rs131, %rs132, %rs133, %rs134}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1181, %rs131;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1182, %rs132;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1183, %rs133;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1184, %f330, %f1181;
|
|
add.f32 %f1185, %f331, %f1182;
|
|
add.f32 %f1186, %f332, %f1183;
|
|
mov.f32 %f1187, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1186;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1185;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1184;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1187;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs127, %rs128, %rs129, %rs130};
|
|
bra.uni $L__BB0_135;
|
|
|
|
$L__BB0_134:
|
|
mov.f32 %f1191, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f1191;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f332;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f331;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f330;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs135, %rs136, %rs137, %rs138};
|
|
|
|
$L__BB0_135:
|
|
mul.f32 %f1192, %f224, %f309;
|
|
mul.f32 %f333, %f1192, 0f404EBF87;
|
|
mul.f32 %f1193, %f225, %f310;
|
|
mul.f32 %f334, %f1193, 0f404EBF87;
|
|
mul.f32 %f1194, %f226, %f311;
|
|
mul.f32 %f335, %f1194, 0f404EBF87;
|
|
ld.const.u64 %rd104, [params+368];
|
|
cvta.to.global.u64 %rd105, %rd104;
|
|
ld.const.u32 %r322, [params+360];
|
|
mad.lo.s32 %r323, %r322, %r6, %r5;
|
|
mul.wide.u32 %rd106, %r323, 8;
|
|
add.s64 %rd25, %rd105, %rd106;
|
|
@%p140 bra $L__BB0_137;
|
|
|
|
ld.global.v4.u16 {%rs146, %rs147, %rs148, %rs149}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1195, %rs146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1196, %rs147;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1197, %rs148;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1198, %f333, %f1195;
|
|
add.f32 %f1199, %f334, %f1196;
|
|
add.f32 %f1200, %f335, %f1197;
|
|
mov.f32 %f1201, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1200;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1199;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1198;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1201;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs142, %rs143, %rs144, %rs145};
|
|
bra.uni $L__BB0_138;
|
|
|
|
$L__BB0_137:
|
|
mov.f32 %f1205, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f1205;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f335;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f334;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f333;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs150, %rs151, %rs152, %rs153};
|
|
|
|
$L__BB0_138:
|
|
mul.f32 %f1206, %f227, %f309;
|
|
mul.f32 %f336, %f1206, 0f3FCEBF87;
|
|
mul.f32 %f1207, %f228, %f310;
|
|
mul.f32 %f337, %f1207, 0f3FCEBF87;
|
|
mul.f32 %f1208, %f229, %f311;
|
|
mul.f32 %f338, %f1208, 0f3FCEBF87;
|
|
ld.const.u64 %rd107, [params+384];
|
|
cvta.to.global.u64 %rd108, %rd107;
|
|
ld.const.u32 %r324, [params+376];
|
|
mad.lo.s32 %r325, %r324, %r6, %r5;
|
|
mul.wide.u32 %rd109, %r325, 8;
|
|
add.s64 %rd26, %rd108, %rd109;
|
|
@%p140 bra $L__BB0_140;
|
|
|
|
ld.global.v4.u16 {%rs161, %rs162, %rs163, %rs164}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1209, %rs161;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1210, %rs162;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1211, %rs163;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1212, %f336, %f1209;
|
|
add.f32 %f1213, %f337, %f1210;
|
|
add.f32 %f1214, %f338, %f1211;
|
|
mov.f32 %f1215, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1214;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1213;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1212;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1215;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs157, %rs158, %rs159, %rs160};
|
|
bra.uni $L__BB0_174;
|
|
|
|
$L__BB0_140:
|
|
mov.f32 %f1219, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs168, %f1219;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs167, %f338;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f337;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f336;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs165, %rs166, %rs167, %rs168};
|
|
|
|
$L__BB0_174:
|
|
ret;
|
|
|
|
}
|
|
|