3060 lines
79 KiB
Plaintext
3060 lines
79 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<181>;
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.reg .b16 %rs<328>;
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.reg .f32 %f<1295>;
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.reg .b32 %r<389>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<162>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r54), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r55), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u64 %rd41, [params+400];
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cvta.to.global.u64 %rd42, %rd41;
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ld.const.u32 %r60, [params+392];
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mad.lo.s32 %r61, %r60, %r55, %r54;
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mul.wide.u32 %rd43, %r61, 4;
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add.s64 %rd2, %rd42, %rd43;
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ld.global.v2.u8 {%rs7, %rs327}, [%rd2];
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or.b16 %rs9, %rs7, %rs327;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p8, %rs10, 0;
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@%p8 bra $L__BB0_2;
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ld.global.u8 %rs326, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs326, [%rd2+2];
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setp.eq.s16 %p9, %rs326, 0;
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mov.f32 %f1261, 0f00000000;
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mov.u16 %rs327, 0;
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mov.f32 %f1262, %f1261;
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mov.f32 %f1263, %f1261;
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@%p9 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f189, %rs7;
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div.rn.f32 %f190, %f189, 0f437F0000;
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fma.rn.f32 %f191, %f190, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs327, 255;
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cvt.rn.f32.u16 %f192, %rs13;
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div.rn.f32 %f193, %f192, 0f437F0000;
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fma.rn.f32 %f194, %f193, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f195, %rs326;
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div.rn.f32 %f196, %f195, 0f437F0000;
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fma.rn.f32 %f197, %f196, 0f40000000, 0fBF800000;
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mul.f32 %f198, %f194, %f194;
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fma.rn.f32 %f199, %f191, %f191, %f198;
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fma.rn.f32 %f200, %f197, %f197, %f199;
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sqrt.rn.f32 %f201, %f200;
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rcp.rn.f32 %f202, %f201;
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mul.f32 %f1263, %f202, %f197;
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mul.f32 %f1262, %f202, %f194;
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mul.f32 %f1261, %f191, %f202;
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$L__BB0_4:
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ld.const.v2.u32 {%r62, %r63}, [params];
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add.s32 %r3, %r62, %r54;
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add.s32 %r4, %r63, %r55;
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setp.eq.f32 %p10, %f1261, 0f00000000;
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setp.eq.f32 %p11, %f1262, 0f00000000;
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and.pred %p12, %p10, %p11;
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setp.eq.f32 %p13, %f1263, 0f00000000;
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and.pred %p14, %p13, %p12;
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@%p14 bra $L__BB0_155;
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bra.uni $L__BB0_5;
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$L__BB0_155:
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ld.const.u32 %r51, [params+104];
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and.b32 %r341, %r51, 1;
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setp.eq.b32 %p165, %r341, 1;
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mov.pred %p166, 0;
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xor.pred %p167, %p165, %p166;
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not.pred %p168, %p167;
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@%p168 bra $L__BB0_157;
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ld.const.u64 %rd113, [params+144];
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cvta.to.global.u64 %rd114, %rd113;
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ld.const.u32 %r342, [params+136];
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mad.lo.s32 %r343, %r342, %r4, %r3;
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mul.wide.u32 %rd115, %r343, 4;
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add.s64 %rd116, %rd114, %rd115;
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mov.u16 %rs173, 0;
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st.global.v4.u8 [%rd116], {%rs173, %rs173, %rs173, %rs173};
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$L__BB0_157:
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and.b32 %r344, %r51, 8;
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setp.eq.s32 %p169, %r344, 0;
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@%p169 bra $L__BB0_159;
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ld.const.u64 %rd117, [params+192];
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cvta.to.global.u64 %rd118, %rd117;
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ld.const.u32 %r345, [params+184];
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mad.lo.s32 %r346, %r345, %r4, %r3;
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mov.f32 %f1112, 0f00000000;
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cvt.rzi.u32.f32 %r347, %f1112;
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mul.wide.u32 %rd119, %r346, 2;
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add.s64 %rd120, %rd118, %rd119;
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mov.u16 %rs174, 0;
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cvt.u16.u32 %rs175, %r347;
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st.global.v2.u8 [%rd120], {%rs175, %rs174};
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$L__BB0_159:
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and.b32 %r348, %r51, 4;
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setp.eq.s32 %p170, %r348, 0;
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ld.const.u32 %r388, [params+108];
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@%p170 bra $L__BB0_163;
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setp.eq.s32 %p171, %r388, 0;
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ld.const.u64 %rd121, [params+224];
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cvta.to.global.u64 %rd122, %rd121;
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ld.const.u32 %r349, [params+216];
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mad.lo.s32 %r350, %r349, %r4, %r3;
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mul.wide.u32 %rd123, %r350, 8;
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add.s64 %rd30, %rd122, %rd123;
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@%p171 bra $L__BB0_162;
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ld.global.v4.u16 {%rs182, %rs183, %rs184, %rs185}, [%rd30];
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// begin inline asm
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{ cvt.f32.f16 %f1113, %rs182;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1114, %rs183;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1115, %rs184;}
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// end inline asm
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add.f32 %f1116, %f1113, 0f00000000;
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add.f32 %f1117, %f1114, 0f00000000;
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add.f32 %f1118, %f1115, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs181, %f1118;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs180, %f1117;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs179, %f1116;}
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// end inline asm
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mov.u16 %rs186, 0;
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st.global.v4.u16 [%rd30], {%rs179, %rs180, %rs181, %rs186};
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bra.uni $L__BB0_163;
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$L__BB0_5:
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ld.const.v4.f32 {%f204, %f205, %f206, %f207}, [params+512];
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neg.f32 %f208, %f205;
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neg.f32 %f209, %f206;
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mul.f32 %f210, %f1261, %f204;
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mul.f32 %f211, %f1262, %f208;
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sub.f32 %f212, %f211, %f210;
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mul.f32 %f213, %f1263, %f206;
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sub.f32 %f13, %f212, %f213;
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ld.const.u64 %rd44, [params+432];
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cvta.to.global.u64 %rd45, %rd44;
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ld.const.u32 %r66, [params+424];
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mad.lo.s32 %r67, %r66, %r55, %r54;
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mul.wide.u32 %rd46, %r67, 12;
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add.s64 %rd47, %rd45, %rd46;
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ld.global.f32 %f14, [%rd47];
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mul.f32 %f214, %f14, 0f3456BF95;
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ld.global.f32 %f15, [%rd47+4];
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mul.f32 %f215, %f15, 0f3456BF95;
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ld.global.f32 %f16, [%rd47+8];
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mul.f32 %f216, %f16, 0f3456BF95;
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abs.f32 %f217, %f1261;
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div.rn.f32 %f218, %f214, %f217;
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abs.f32 %f219, %f1262;
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div.rn.f32 %f220, %f215, %f219;
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abs.f32 %f221, %f1263;
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div.rn.f32 %f222, %f216, %f221;
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abs.f32 %f223, %f218;
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abs.f32 %f224, %f220;
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abs.f32 %f225, %f222;
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mov.f32 %f226, 0f38D1B717;
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max.f32 %f227, %f223, %f226;
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max.f32 %f228, %f224, %f226;
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max.f32 %f229, %f225, %f226;
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fma.rn.f32 %f17, %f1261, %f227, %f14;
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fma.rn.f32 %f18, %f1262, %f228, %f15;
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fma.rn.f32 %f19, %f1263, %f229, %f16;
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abs.f32 %f230, %f204;
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abs.f32 %f231, %f206;
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setp.gt.f32 %p15, %f230, %f231;
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selp.f32 %f232, %f208, 0f00000000, %p15;
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mov.f32 %f1265, 0f00000000;
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selp.f32 %f233, %f204, %f209, %p15;
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selp.f32 %f234, 0f00000000, %f205, %p15;
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mul.f32 %f235, %f233, %f233;
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fma.rn.f32 %f236, %f232, %f232, %f235;
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fma.rn.f32 %f237, %f234, %f234, %f236;
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sqrt.rn.f32 %f238, %f237;
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rcp.rn.f32 %f239, %f238;
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mul.f32 %f20, %f232, %f239;
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mul.f32 %f21, %f233, %f239;
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mul.f32 %f22, %f234, %f239;
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mul.f32 %f240, %f206, %f21;
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mul.f32 %f241, %f205, %f22;
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sub.f32 %f23, %f240, %f241;
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mul.f32 %f242, %f204, %f22;
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mul.f32 %f243, %f206, %f20;
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sub.f32 %f24, %f242, %f243;
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mul.f32 %f244, %f205, %f20;
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mul.f32 %f245, %f204, %f21;
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sub.f32 %f25, %f244, %f245;
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ld.const.u64 %rd48, [params+128];
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cvta.to.global.u64 %rd49, %rd48;
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ld.const.u32 %r68, [params+120];
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mad.lo.s32 %r69, %r68, %r55, %r54;
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mul.wide.u32 %rd50, %r69, 4;
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add.s64 %rd3, %rd49, %rd50;
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ld.const.u32 %r5, [params+540];
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setp.lt.s32 %p16, %r5, 1;
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@%p16 bra $L__BB0_34;
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cvt.rn.f32.s32 %f247, %r5;
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rcp.rn.f32 %f26, %f247;
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ld.global.u32 %r379, [%rd3];
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ld.const.f32 %f27, [params+536];
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ld.const.u8 %rs15, [params+104];
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and.b16 %rs16, %rs15, 32;
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setp.eq.s16 %p17, %rs16, 0;
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mov.u32 %r70, 0;
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selp.f32 %f28, 0f3F800000, 0f41200000, %p17;
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mul.f32 %f29, %f17, 0f3456BF95;
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mul.f32 %f30, %f18, 0f3456BF95;
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mul.f32 %f31, %f19, 0f3456BF95;
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ld.const.u64 %rd4, [params+96];
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add.s64 %rd5, %rd1, 24;
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mov.u64 %rd51, __cudart_i2opi_f;
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abs.f32 %f330, %f30;
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abs.f32 %f331, %f29;
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max.f32 %f332, %f331, %f330;
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abs.f32 %f333, %f31;
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max.f32 %f334, %f332, %f333;
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mov.u32 %r376, %r70;
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$L__BB0_7:
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cvt.rn.f32.s32 %f33, %r376;
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mov.u32 %r378, %r70;
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$L__BB0_8:
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mad.lo.s32 %r72, %r379, 1664525, 1013904223;
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and.b32 %r73, %r72, 16777215;
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cvt.rn.f32.u32 %f248, %r73;
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fma.rn.f32 %f249, %f248, 0f33800000, %f33;
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mul.f32 %f250, %f26, %f249;
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mad.lo.s32 %r379, %r72, 1664525, 1013904223;
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and.b32 %r74, %r379, 16777215;
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cvt.rn.f32.u32 %f251, %r74;
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cvt.rn.f32.s32 %f252, %r378;
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fma.rn.f32 %f253, %f251, 0f33800000, %f252;
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mul.f32 %f254, %f26, %f253;
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sqrt.rn.f32 %f35, %f250;
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mul.f32 %f36, %f254, 0f40C90FDB;
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mul.f32 %f255, %f36, 0f3F22F983;
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cvt.rni.s32.f32 %r386, %f255;
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cvt.rn.f32.s32 %f256, %r386;
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mov.f32 %f257, 0fBFC90FDA;
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fma.rn.f32 %f258, %f256, %f257, %f36;
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mov.f32 %f259, 0fB3A22168;
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fma.rn.f32 %f260, %f256, %f259, %f258;
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mov.f32 %f261, 0fA7C234C5;
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fma.rn.f32 %f1269, %f256, %f261, %f260;
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abs.f32 %f38, %f36;
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setp.ltu.f32 %p18, %f38, 0f47CE4780;
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mov.u32 %r383, %r386;
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mov.f32 %f1266, %f1269;
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@%p18 bra $L__BB0_16;
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setp.eq.f32 %p19, %f38, 0f7F800000;
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@%p19 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f264, 0f00000000;
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mul.rn.f32 %f1266, %f36, %f264;
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mov.u32 %r383, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r13, %f36;
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bfe.u32 %r76, %r13, 23, 8;
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add.s32 %r14, %r76, -128;
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shl.b32 %r77, %r13, 8;
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or.b32 %r15, %r77, -2147483648;
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shr.u32 %r16, %r14, 5;
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mov.u64 %rd159, 0;
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mov.u32 %r380, 0;
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mov.u64 %rd157, %rd1;
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mov.u64 %rd158, %rd51;
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$L__BB0_11:
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.pragma "nounroll";
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ld.global.nc.u32 %r78, [%rd158];
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mad.wide.u32 %rd53, %r78, %r15, %rd159;
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shr.u64 %rd159, %rd53, 32;
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st.local.u32 [%rd157], %rd53;
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add.s64 %rd158, %rd158, 4;
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add.s64 %rd157, %rd157, 4;
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add.s32 %r380, %r380, 1;
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setp.ne.s32 %p20, %r380, 6;
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@%p20 bra $L__BB0_11;
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st.local.u32 [%rd5], %rd159;
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mov.u32 %r79, 4;
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sub.s32 %r19, %r79, %r16;
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mov.u32 %r80, 6;
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sub.s32 %r81, %r80, %r16;
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mul.wide.s32 %rd54, %r81, 4;
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add.s64 %rd55, %rd1, %rd54;
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ld.local.u32 %r381, [%rd55];
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ld.local.u32 %r382, [%rd55+-4];
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and.b32 %r22, %r14, 31;
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setp.eq.s32 %p21, %r22, 0;
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@%p21 bra $L__BB0_14;
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mov.u32 %r82, 32;
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sub.s32 %r83, %r82, %r22;
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shr.u32 %r84, %r382, %r83;
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shl.b32 %r85, %r381, %r22;
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add.s32 %r381, %r84, %r85;
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mul.wide.s32 %rd56, %r19, 4;
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add.s64 %rd57, %rd1, %rd56;
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ld.local.u32 %r86, [%rd57];
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shr.u32 %r87, %r86, %r83;
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shl.b32 %r88, %r382, %r22;
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add.s32 %r382, %r87, %r88;
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$L__BB0_14:
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and.b32 %r89, %r13, -2147483648;
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shr.u32 %r90, %r382, 30;
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shl.b32 %r91, %r381, 2;
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or.b32 %r92, %r90, %r91;
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shr.u32 %r93, %r92, 31;
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shr.u32 %r94, %r381, 30;
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add.s32 %r95, %r93, %r94;
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neg.s32 %r96, %r95;
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setp.eq.s32 %p22, %r89, 0;
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selp.b32 %r383, %r95, %r96, %p22;
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setp.ne.s32 %p23, %r93, 0;
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xor.b32 %r97, %r89, -2147483648;
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selp.b32 %r98, %r97, %r89, %p23;
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selp.b32 %r99, -1, 0, %p23;
|
|
xor.b32 %r100, %r92, %r99;
|
|
shl.b32 %r101, %r382, 2;
|
|
xor.b32 %r102, %r101, %r99;
|
|
cvt.u64.u32 %rd58, %r100;
|
|
cvt.u64.u32 %rd59, %r102;
|
|
bfi.b64 %rd60, %rd58, %rd59, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd60;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f262, %fd2;
|
|
setp.eq.s32 %p24, %r98, 0;
|
|
neg.f32 %f263, %f262;
|
|
selp.f32 %f1266, %f262, %f263, %p24;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r29, %r383, 1;
|
|
and.b32 %r30, %r29, 1;
|
|
setp.eq.s32 %p25, %r30, 0;
|
|
selp.f32 %f42, %f1266, 0f3F800000, %p25;
|
|
mul.rn.f32 %f43, %f1266, %f1266;
|
|
mov.f32 %f1267, 0fB94D4153;
|
|
@%p25 bra $L__BB0_18;
|
|
|
|
mov.f32 %f266, 0fBAB607ED;
|
|
mov.f32 %f267, 0f37CBAC00;
|
|
fma.rn.f32 %f1267, %f267, %f43, %f266;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f268, 0f3C0885E4, 0f3D2AAABB, %p25;
|
|
fma.rn.f32 %f269, %f1267, %f43, %f268;
|
|
selp.f32 %f270, 0fBE2AAAA8, 0fBEFFFFFF, %p25;
|
|
fma.rn.f32 %f271, %f269, %f43, %f270;
|
|
mov.f32 %f272, 0f00000000;
|
|
fma.rn.f32 %f273, %f43, %f42, %f272;
|
|
fma.rn.f32 %f1268, %f271, %f273, %f42;
|
|
and.b32 %r104, %r29, 2;
|
|
setp.eq.s32 %p27, %r104, 0;
|
|
@%p27 bra $L__BB0_20;
|
|
|
|
mov.f32 %f275, 0fBF800000;
|
|
fma.rn.f32 %f1268, %f1268, %f275, %f272;
|
|
|
|
$L__BB0_20:
|
|
@%p18 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p29, %f38, 0f7F800000;
|
|
@%p29 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f278, 0f00000000;
|
|
mul.rn.f32 %f1269, %f36, %f278;
|
|
mov.u32 %r386, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r31, %f36;
|
|
bfe.u32 %r105, %r31, 23, 8;
|
|
add.s32 %r32, %r105, -128;
|
|
shl.b32 %r106, %r31, 8;
|
|
or.b32 %r33, %r106, -2147483648;
|
|
shr.u32 %r34, %r32, 5;
|
|
mov.u64 %rd160, 0;
|
|
mov.u64 %rd161, %rd160;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd63, %rd160, 2;
|
|
mov.u64 %rd64, __cudart_i2opi_f;
|
|
add.s64 %rd65, %rd64, %rd63;
|
|
ld.global.nc.u32 %r107, [%rd65];
|
|
mad.wide.u32 %rd66, %r107, %r33, %rd161;
|
|
shr.u64 %rd161, %rd66, 32;
|
|
add.s64 %rd67, %rd1, %rd63;
|
|
st.local.u32 [%rd67], %rd66;
|
|
cvt.u32.u64 %r108, %rd160;
|
|
add.s32 %r109, %r108, 1;
|
|
cvt.s64.s32 %rd160, %r109;
|
|
setp.ne.s32 %p30, %r109, 6;
|
|
@%p30 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd5], %rd161;
|
|
mov.u32 %r110, 4;
|
|
sub.s32 %r35, %r110, %r34;
|
|
mov.u32 %r111, 6;
|
|
sub.s32 %r112, %r111, %r34;
|
|
mul.wide.s32 %rd68, %r112, 4;
|
|
add.s64 %rd69, %rd1, %rd68;
|
|
ld.local.u32 %r384, [%rd69];
|
|
ld.local.u32 %r385, [%rd69+-4];
|
|
and.b32 %r38, %r32, 31;
|
|
setp.eq.s32 %p31, %r38, 0;
|
|
@%p31 bra $L__BB0_26;
|
|
|
|
mov.u32 %r113, 32;
|
|
sub.s32 %r114, %r113, %r38;
|
|
shr.u32 %r115, %r385, %r114;
|
|
shl.b32 %r116, %r384, %r38;
|
|
add.s32 %r384, %r115, %r116;
|
|
mul.wide.s32 %rd70, %r35, 4;
|
|
add.s64 %rd71, %rd1, %rd70;
|
|
ld.local.u32 %r117, [%rd71];
|
|
shr.u32 %r118, %r117, %r114;
|
|
shl.b32 %r119, %r385, %r38;
|
|
add.s32 %r385, %r118, %r119;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r120, %r31, -2147483648;
|
|
shr.u32 %r121, %r385, 30;
|
|
shl.b32 %r122, %r384, 2;
|
|
or.b32 %r123, %r121, %r122;
|
|
shr.u32 %r124, %r123, 31;
|
|
shr.u32 %r125, %r384, 30;
|
|
add.s32 %r126, %r124, %r125;
|
|
neg.s32 %r127, %r126;
|
|
setp.eq.s32 %p32, %r120, 0;
|
|
selp.b32 %r386, %r126, %r127, %p32;
|
|
setp.ne.s32 %p33, %r124, 0;
|
|
xor.b32 %r128, %r120, -2147483648;
|
|
selp.b32 %r129, %r128, %r120, %p33;
|
|
selp.b32 %r130, -1, 0, %p33;
|
|
xor.b32 %r131, %r123, %r130;
|
|
shl.b32 %r132, %r385, 2;
|
|
xor.b32 %r133, %r132, %r130;
|
|
cvt.u64.u32 %rd72, %r131;
|
|
cvt.u64.u32 %rd73, %r133;
|
|
bfi.b64 %rd74, %rd72, %rd73, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd74;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f276, %fd4;
|
|
setp.eq.s32 %p34, %r129, 0;
|
|
neg.f32 %f277, %f276;
|
|
selp.f32 %f1269, %f276, %f277, %p34;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f52, %f35, %f1268;
|
|
and.b32 %r45, %r386, 1;
|
|
setp.eq.s32 %p35, %r45, 0;
|
|
selp.f32 %f53, %f1269, 0f3F800000, %p35;
|
|
mul.rn.f32 %f54, %f1269, %f1269;
|
|
mov.f32 %f1270, 0fB94D4153;
|
|
@%p35 bra $L__BB0_30;
|
|
|
|
mov.f32 %f280, 0fBAB607ED;
|
|
mov.f32 %f281, 0f37CBAC00;
|
|
fma.rn.f32 %f1270, %f281, %f54, %f280;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f282, 0f3C0885E4, 0f3D2AAABB, %p35;
|
|
fma.rn.f32 %f283, %f1270, %f54, %f282;
|
|
selp.f32 %f284, 0fBE2AAAA8, 0fBEFFFFFF, %p35;
|
|
fma.rn.f32 %f285, %f283, %f54, %f284;
|
|
mov.f32 %f286, 0f00000000;
|
|
fma.rn.f32 %f287, %f54, %f53, %f286;
|
|
fma.rn.f32 %f1271, %f285, %f287, %f53;
|
|
and.b32 %r135, %r386, 2;
|
|
setp.eq.s32 %p37, %r135, 0;
|
|
@%p37 bra $L__BB0_32;
|
|
|
|
mov.f32 %f289, 0fBF800000;
|
|
fma.rn.f32 %f1271, %f1271, %f289, %f286;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f299, %f52, %f52;
|
|
mov.f32 %f300, 0f3F800000;
|
|
sub.f32 %f301, %f300, %f299;
|
|
mul.f32 %f302, %f35, %f1271;
|
|
mul.f32 %f303, %f302, %f302;
|
|
sub.f32 %f304, %f301, %f303;
|
|
max.f32 %f305, %f286, %f304;
|
|
sqrt.rn.f32 %f306, %f305;
|
|
mul.f32 %f307, %f20, %f302;
|
|
mul.f32 %f308, %f21, %f302;
|
|
mul.f32 %f309, %f22, %f302;
|
|
fma.rn.f32 %f310, %f23, %f52, %f307;
|
|
fma.rn.f32 %f311, %f24, %f52, %f308;
|
|
fma.rn.f32 %f312, %f25, %f52, %f309;
|
|
fma.rn.f32 %f313, %f204, %f306, %f310;
|
|
fma.rn.f32 %f314, %f205, %f306, %f311;
|
|
fma.rn.f32 %f315, %f206, %f306, %f312;
|
|
add.f32 %f316, %f204, %f313;
|
|
add.f32 %f317, %f205, %f314;
|
|
add.f32 %f318, %f206, %f315;
|
|
mul.f32 %f319, %f27, %f316;
|
|
mul.f32 %f320, %f27, %f317;
|
|
mul.f32 %f321, %f27, %f318;
|
|
sub.f32 %f322, %f319, %f204;
|
|
sub.f32 %f323, %f320, %f205;
|
|
sub.f32 %f324, %f321, %f206;
|
|
mul.f32 %f325, %f323, %f323;
|
|
fma.rn.f32 %f326, %f322, %f322, %f325;
|
|
fma.rn.f32 %f327, %f324, %f324, %f326;
|
|
sqrt.rn.f32 %f328, %f327;
|
|
rcp.rn.f32 %f329, %f328;
|
|
mul.f32 %f293, %f329, %f322;
|
|
mul.f32 %f294, %f329, %f323;
|
|
mul.f32 %f295, %f329, %f324;
|
|
mov.f32 %f335, 0f38D1B717;
|
|
max.f32 %f336, %f334, %f335;
|
|
mul.f32 %f296, %f28, %f336;
|
|
mov.f32 %f297, 0f6C4ECB8F;
|
|
mov.u32 %r172, 2;
|
|
mov.u32 %r174, 1;
|
|
mov.u32 %r175, 1065353216;
|
|
mov.u32 %r206, 0;
|
|
// begin inline asm
|
|
call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd4,%f17,%f18,%f19,%f293,%f294,%f295,%f296,%f297,%f286,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f337, %r136;
|
|
add.f32 %f1265, %f1265, %f337;
|
|
add.s32 %r378, %r378, 1;
|
|
setp.lt.s32 %p38, %r378, %r5;
|
|
@%p38 bra $L__BB0_8;
|
|
|
|
add.s32 %r376, %r376, 1;
|
|
setp.lt.s32 %p39, %r376, %r5;
|
|
@%p39 bra $L__BB0_7;
|
|
|
|
$L__BB0_34:
|
|
setp.eq.s32 %p40, %r5, 0;
|
|
mov.f32 %f1273, 0f3F800000;
|
|
@%p40 bra $L__BB0_36;
|
|
|
|
mul.lo.s32 %r207, %r5, %r5;
|
|
cvt.rn.f32.s32 %f339, %r207;
|
|
div.rn.f32 %f1273, %f1265, %f339;
|
|
|
|
$L__BB0_36:
|
|
mul.f32 %f340, %f15, %f24;
|
|
fma.rn.f32 %f341, %f14, %f23, %f340;
|
|
fma.rn.f32 %f342, %f16, %f25, %f341;
|
|
ld.const.v4.f32 {%f343, %f344, %f345, %f346}, [params+560];
|
|
fma.rn.f32 %f351, %f342, %f343, %f345;
|
|
mul.f32 %f352, %f15, %f21;
|
|
fma.rn.f32 %f353, %f14, %f20, %f352;
|
|
fma.rn.f32 %f354, %f16, %f22, %f353;
|
|
fma.rn.f32 %f355, %f354, %f344, %f346;
|
|
ld.const.u64 %rd76, [params+552];
|
|
tex.2d.v4.f32.f32 {%f356, %f357, %f358, %f359}, [%rd76, {%f351, %f355}];
|
|
min.f32 %f360, %f356, %f357;
|
|
min.f32 %f361, %f360, %f358;
|
|
mul.f32 %f64, %f1273, %f361;
|
|
ld.const.f32 %f362, [params+524];
|
|
mul.f32 %f363, %f1273, %f362;
|
|
ld.const.v2.f32 {%f364, %f365}, [params+528];
|
|
mul.f32 %f368, %f1273, %f364;
|
|
mul.f32 %f369, %f1273, %f365;
|
|
mul.f32 %f65, %f356, %f363;
|
|
mul.f32 %f66, %f357, %f368;
|
|
mul.f32 %f67, %f358, %f369;
|
|
cvt.sat.f32.f32 %f370, %f13;
|
|
mul.f32 %f68, %f65, %f370;
|
|
mul.f32 %f69, %f66, %f370;
|
|
mul.f32 %f70, %f370, %f67;
|
|
ld.const.u32 %r48, [params+104];
|
|
and.b32 %r208, %r48, 8;
|
|
setp.eq.s32 %p41, %r208, 0;
|
|
@%p41 bra $L__BB0_50;
|
|
|
|
mov.f32 %f375, 0f3EE8BA2E;
|
|
abs.f32 %f72, %f64;
|
|
setp.lt.f32 %p42, %f72, 0f00800000;
|
|
mul.f32 %f377, %f72, 0f4B800000;
|
|
selp.f32 %f378, %f377, %f72, %p42;
|
|
selp.f32 %f379, 0fC3170000, 0fC2FE0000, %p42;
|
|
mov.b32 %r211, %f378;
|
|
and.b32 %r212, %r211, 8388607;
|
|
or.b32 %r213, %r212, 1065353216;
|
|
mov.b32 %f380, %r213;
|
|
shr.u32 %r214, %r211, 23;
|
|
cvt.rn.f32.u32 %f381, %r214;
|
|
add.f32 %f382, %f379, %f381;
|
|
setp.gt.f32 %p43, %f380, 0f3FB504F3;
|
|
mul.f32 %f383, %f380, 0f3F000000;
|
|
add.f32 %f384, %f382, 0f3F800000;
|
|
selp.f32 %f385, %f384, %f382, %p43;
|
|
selp.f32 %f386, %f383, %f380, %p43;
|
|
add.f32 %f387, %f386, 0fBF800000;
|
|
add.f32 %f388, %f386, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f389, %f388;
|
|
add.f32 %f390, %f387, %f387;
|
|
mul.f32 %f391, %f390, %f389;
|
|
mul.f32 %f392, %f391, %f391;
|
|
mov.f32 %f393, 0f3C4CAF63;
|
|
mov.f32 %f394, 0f3B18F0FE;
|
|
fma.rn.f32 %f395, %f394, %f392, %f393;
|
|
mov.f32 %f396, 0f3DAAAABD;
|
|
fma.rn.f32 %f397, %f395, %f392, %f396;
|
|
mul.rn.f32 %f398, %f397, %f392;
|
|
mul.rn.f32 %f399, %f398, %f391;
|
|
sub.f32 %f400, %f387, %f391;
|
|
add.f32 %f401, %f400, %f400;
|
|
neg.f32 %f402, %f391;
|
|
fma.rn.f32 %f403, %f402, %f387, %f401;
|
|
mul.rn.f32 %f404, %f389, %f403;
|
|
add.f32 %f405, %f399, %f391;
|
|
sub.f32 %f406, %f391, %f405;
|
|
add.f32 %f407, %f399, %f406;
|
|
add.f32 %f408, %f404, %f407;
|
|
add.f32 %f409, %f405, %f408;
|
|
sub.f32 %f410, %f405, %f409;
|
|
add.f32 %f411, %f408, %f410;
|
|
mov.f32 %f412, 0f3F317200;
|
|
mul.rn.f32 %f413, %f385, %f412;
|
|
mov.f32 %f414, 0f35BFBE8E;
|
|
mul.rn.f32 %f415, %f385, %f414;
|
|
add.f32 %f416, %f413, %f409;
|
|
sub.f32 %f417, %f413, %f416;
|
|
add.f32 %f418, %f409, %f417;
|
|
add.f32 %f419, %f411, %f418;
|
|
add.f32 %f420, %f415, %f419;
|
|
add.f32 %f421, %f416, %f420;
|
|
sub.f32 %f422, %f416, %f421;
|
|
add.f32 %f423, %f420, %f422;
|
|
mul.rn.f32 %f424, %f375, %f421;
|
|
neg.f32 %f425, %f424;
|
|
fma.rn.f32 %f426, %f375, %f421, %f425;
|
|
fma.rn.f32 %f427, %f375, %f423, %f426;
|
|
mov.f32 %f428, 0f00000000;
|
|
fma.rn.f32 %f429, %f428, %f421, %f427;
|
|
add.rn.f32 %f430, %f424, %f429;
|
|
neg.f32 %f431, %f430;
|
|
add.rn.f32 %f432, %f424, %f431;
|
|
add.rn.f32 %f433, %f432, %f429;
|
|
mov.b32 %r215, %f430;
|
|
setp.eq.s32 %p44, %r215, 1118925336;
|
|
add.s32 %r216, %r215, -1;
|
|
mov.b32 %f434, %r216;
|
|
add.f32 %f435, %f433, 0f37000000;
|
|
selp.f32 %f73, %f435, %f433, %p44;
|
|
selp.f32 %f436, %f434, %f430, %p44;
|
|
mov.f32 %f437, 0f3FB8AA3B;
|
|
mul.rn.f32 %f438, %f436, %f437;
|
|
cvt.rzi.f32.f32 %f439, %f438;
|
|
abs.f32 %f440, %f439;
|
|
setp.gt.f32 %p45, %f440, 0f42FC0000;
|
|
mov.b32 %r217, %f439;
|
|
and.b32 %r218, %r217, -2147483648;
|
|
or.b32 %r219, %r218, 1123811328;
|
|
mov.b32 %f441, %r219;
|
|
selp.f32 %f442, %f441, %f439, %p45;
|
|
mov.f32 %f443, 0fBF317218;
|
|
fma.rn.f32 %f444, %f442, %f443, %f436;
|
|
mov.f32 %f445, 0f3102E308;
|
|
fma.rn.f32 %f446, %f442, %f445, %f444;
|
|
mul.f32 %f447, %f446, 0f3FB8AA3B;
|
|
add.f32 %f448, %f442, 0f4B40007F;
|
|
mov.b32 %r220, %f448;
|
|
shl.b32 %r221, %r220, 23;
|
|
mov.b32 %f449, %r221;
|
|
ex2.approx.ftz.f32 %f450, %f447;
|
|
mul.f32 %f74, %f450, %f449;
|
|
setp.eq.f32 %p46, %f74, 0f7F800000;
|
|
mov.f32 %f1274, 0f7F800000;
|
|
@%p46 bra $L__BB0_39;
|
|
|
|
fma.rn.f32 %f1274, %f74, %f73, %f74;
|
|
|
|
$L__BB0_39:
|
|
mov.f32 %f1214, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f1213, %f1214;
|
|
add.f32 %f1212, %f1213, %f1213;
|
|
mov.f32 %f1211, 0f3EE8BA2E;
|
|
sub.f32 %f1210, %f1211, %f1212;
|
|
abs.f32 %f1209, %f1210;
|
|
setp.lt.f32 %p47, %f64, 0f00000000;
|
|
setp.eq.f32 %p48, %f1209, 0f3F800000;
|
|
and.pred %p1, %p47, %p48;
|
|
setp.eq.f32 %p49, %f64, 0f00000000;
|
|
@%p49 bra $L__BB0_43;
|
|
bra.uni $L__BB0_40;
|
|
|
|
$L__BB0_43:
|
|
add.f32 %f455, %f64, %f64;
|
|
selp.f32 %f1276, %f455, 0f00000000, %p48;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_162:
|
|
mov.f32 %f1121, 0f00000000;
|
|
mov.u32 %r388, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs189, %f1121;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs188, %f1121;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs187, %f1121;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs190, 0;
|
|
st.global.v4.u16 [%rd30], {%rs187, %rs188, %rs189, %rs190};
|
|
|
|
$L__BB0_163:
|
|
ld.const.u64 %rd124, [params+256];
|
|
cvta.to.global.u64 %rd125, %rd124;
|
|
ld.const.u32 %r352, [params+248];
|
|
mad.lo.s32 %r353, %r352, %r4, %r3;
|
|
mul.wide.u32 %rd126, %r353, 8;
|
|
add.s64 %rd31, %rd125, %rd126;
|
|
setp.eq.s32 %p172, %r388, 0;
|
|
@%p172 bra $L__BB0_165;
|
|
|
|
ld.global.v4.u16 {%rs197, %rs198, %rs199, %rs200}, [%rd31];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1122, %rs197;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1123, %rs198;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1124, %rs199;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1125, %f1122, 0f00000000;
|
|
add.f32 %f1126, %f1123, 0f00000000;
|
|
add.f32 %f1127, %f1124, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs196, %f1127;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs195, %f1126;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs194, %f1125;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs201, 0;
|
|
st.global.v4.u16 [%rd31], {%rs194, %rs195, %rs196, %rs201};
|
|
bra.uni $L__BB0_166;
|
|
|
|
$L__BB0_165:
|
|
mov.f32 %f1130, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs204, %f1130;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs203, %f1130;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs202, %f1130;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs205, 0;
|
|
st.global.v4.u16 [%rd31], {%rs202, %rs203, %rs204, %rs205};
|
|
|
|
$L__BB0_166:
|
|
ld.const.u64 %rd127, [params+272];
|
|
cvta.to.global.u64 %rd128, %rd127;
|
|
ld.const.u32 %r354, [params+264];
|
|
mad.lo.s32 %r355, %r354, %r4, %r3;
|
|
mul.wide.u32 %rd129, %r355, 8;
|
|
add.s64 %rd32, %rd128, %rd129;
|
|
@%p172 bra $L__BB0_168;
|
|
|
|
ld.global.v4.u16 {%rs212, %rs213, %rs214, %rs215}, [%rd32];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1131, %rs212;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1132, %rs213;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1133, %rs214;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1134, %f1131, 0f00000000;
|
|
add.f32 %f1135, %f1132, 0f00000000;
|
|
add.f32 %f1136, %f1133, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs211, %f1136;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs210, %f1135;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs209, %f1134;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs216, 0;
|
|
st.global.v4.u16 [%rd32], {%rs209, %rs210, %rs211, %rs216};
|
|
bra.uni $L__BB0_169;
|
|
|
|
$L__BB0_168:
|
|
mov.f32 %f1139, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs219, %f1139;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs218, %f1139;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs217, %f1139;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs220, 0;
|
|
st.global.v4.u16 [%rd32], {%rs217, %rs218, %rs219, %rs220};
|
|
|
|
$L__BB0_169:
|
|
ld.const.u64 %rd130, [params+288];
|
|
cvta.to.global.u64 %rd131, %rd130;
|
|
ld.const.u32 %r356, [params+280];
|
|
mad.lo.s32 %r357, %r356, %r4, %r3;
|
|
mul.wide.u32 %rd132, %r357, 8;
|
|
add.s64 %rd33, %rd131, %rd132;
|
|
@%p172 bra $L__BB0_171;
|
|
|
|
ld.global.v4.u16 {%rs227, %rs228, %rs229, %rs230}, [%rd33];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1140, %rs227;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1141, %rs228;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1142, %rs229;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1143, %f1140, 0f00000000;
|
|
add.f32 %f1144, %f1141, 0f00000000;
|
|
add.f32 %f1145, %f1142, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs226, %f1145;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs225, %f1144;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs224, %f1143;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs231, 0;
|
|
st.global.v4.u16 [%rd33], {%rs224, %rs225, %rs226, %rs231};
|
|
bra.uni $L__BB0_172;
|
|
|
|
$L__BB0_171:
|
|
mov.f32 %f1148, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs234, %f1148;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs233, %f1148;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs232, %f1148;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs235, 0;
|
|
st.global.v4.u16 [%rd33], {%rs232, %rs233, %rs234, %rs235};
|
|
|
|
$L__BB0_172:
|
|
ld.const.u64 %rd133, [params+304];
|
|
cvta.to.global.u64 %rd134, %rd133;
|
|
ld.const.u32 %r358, [params+296];
|
|
mad.lo.s32 %r359, %r358, %r4, %r3;
|
|
mul.wide.u32 %rd135, %r359, 8;
|
|
add.s64 %rd34, %rd134, %rd135;
|
|
@%p172 bra $L__BB0_174;
|
|
|
|
ld.global.v4.u16 {%rs242, %rs243, %rs244, %rs245}, [%rd34];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1149, %rs242;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1150, %rs243;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1151, %rs244;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1152, %f1149, 0f00000000;
|
|
add.f32 %f1153, %f1150, 0f00000000;
|
|
add.f32 %f1154, %f1151, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs241, %f1154;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs240, %f1153;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs239, %f1152;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs246, 0;
|
|
st.global.v4.u16 [%rd34], {%rs239, %rs240, %rs241, %rs246};
|
|
bra.uni $L__BB0_175;
|
|
|
|
$L__BB0_174:
|
|
mov.f32 %f1157, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs249, %f1157;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs248, %f1157;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs247, %f1157;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs250, 0;
|
|
st.global.v4.u16 [%rd34], {%rs247, %rs248, %rs249, %rs250};
|
|
|
|
$L__BB0_175:
|
|
ld.const.u64 %rd136, [params+320];
|
|
cvta.to.global.u64 %rd137, %rd136;
|
|
ld.const.u32 %r360, [params+312];
|
|
mad.lo.s32 %r361, %r360, %r4, %r3;
|
|
mul.wide.u32 %rd138, %r361, 8;
|
|
add.s64 %rd35, %rd137, %rd138;
|
|
@%p172 bra $L__BB0_177;
|
|
|
|
ld.global.v4.u16 {%rs257, %rs258, %rs259, %rs260}, [%rd35];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1158, %rs257;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1159, %rs258;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1160, %rs259;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1161, %f1158, 0f00000000;
|
|
add.f32 %f1162, %f1159, 0f00000000;
|
|
add.f32 %f1163, %f1160, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs256, %f1163;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs255, %f1162;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs254, %f1161;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs261, 0;
|
|
st.global.v4.u16 [%rd35], {%rs254, %rs255, %rs256, %rs261};
|
|
bra.uni $L__BB0_178;
|
|
|
|
$L__BB0_177:
|
|
mov.f32 %f1166, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs264, %f1166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs263, %f1166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs262, %f1166;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs265, 0;
|
|
st.global.v4.u16 [%rd35], {%rs262, %rs263, %rs264, %rs265};
|
|
|
|
$L__BB0_178:
|
|
ld.const.u64 %rd139, [params+336];
|
|
cvta.to.global.u64 %rd140, %rd139;
|
|
ld.const.u32 %r362, [params+328];
|
|
mad.lo.s32 %r363, %r362, %r4, %r3;
|
|
mul.wide.u32 %rd141, %r363, 8;
|
|
add.s64 %rd36, %rd140, %rd141;
|
|
@%p172 bra $L__BB0_180;
|
|
|
|
ld.global.v4.u16 {%rs272, %rs273, %rs274, %rs275}, [%rd36];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1167, %rs272;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1168, %rs273;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1169, %rs274;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1170, %f1167, 0f00000000;
|
|
add.f32 %f1171, %f1168, 0f00000000;
|
|
add.f32 %f1172, %f1169, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs271, %f1172;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs270, %f1171;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs269, %f1170;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs276, 0;
|
|
st.global.v4.u16 [%rd36], {%rs269, %rs270, %rs271, %rs276};
|
|
bra.uni $L__BB0_181;
|
|
|
|
$L__BB0_180:
|
|
mov.f32 %f1175, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs279, %f1175;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs278, %f1175;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs277, %f1175;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs280, 0;
|
|
st.global.v4.u16 [%rd36], {%rs277, %rs278, %rs279, %rs280};
|
|
|
|
$L__BB0_181:
|
|
ld.const.u64 %rd142, [params+352];
|
|
cvta.to.global.u64 %rd143, %rd142;
|
|
ld.const.u32 %r364, [params+344];
|
|
mad.lo.s32 %r365, %r364, %r4, %r3;
|
|
mul.wide.u32 %rd144, %r365, 8;
|
|
add.s64 %rd37, %rd143, %rd144;
|
|
@%p172 bra $L__BB0_183;
|
|
|
|
ld.global.v4.u16 {%rs287, %rs288, %rs289, %rs290}, [%rd37];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1176, %rs287;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1177, %rs288;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1178, %rs289;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1179, %f1176, 0f00000000;
|
|
add.f32 %f1180, %f1177, 0f00000000;
|
|
add.f32 %f1181, %f1178, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs286, %f1181;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs285, %f1180;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs284, %f1179;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs291, 0;
|
|
st.global.v4.u16 [%rd37], {%rs284, %rs285, %rs286, %rs291};
|
|
bra.uni $L__BB0_184;
|
|
|
|
$L__BB0_183:
|
|
mov.f32 %f1184, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs294, %f1184;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs293, %f1184;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs292, %f1184;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs295, 0;
|
|
st.global.v4.u16 [%rd37], {%rs292, %rs293, %rs294, %rs295};
|
|
|
|
$L__BB0_184:
|
|
ld.const.u64 %rd145, [params+368];
|
|
cvta.to.global.u64 %rd146, %rd145;
|
|
ld.const.u32 %r366, [params+360];
|
|
mad.lo.s32 %r367, %r366, %r4, %r3;
|
|
mul.wide.u32 %rd147, %r367, 8;
|
|
add.s64 %rd38, %rd146, %rd147;
|
|
@%p172 bra $L__BB0_186;
|
|
|
|
ld.global.v4.u16 {%rs302, %rs303, %rs304, %rs305}, [%rd38];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1185, %rs302;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1186, %rs303;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1187, %rs304;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1188, %f1185, 0f00000000;
|
|
add.f32 %f1189, %f1186, 0f00000000;
|
|
add.f32 %f1190, %f1187, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs301, %f1190;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs300, %f1189;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs299, %f1188;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs306, 0;
|
|
st.global.v4.u16 [%rd38], {%rs299, %rs300, %rs301, %rs306};
|
|
bra.uni $L__BB0_187;
|
|
|
|
$L__BB0_186:
|
|
mov.f32 %f1193, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs309, %f1193;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs308, %f1193;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs307, %f1193;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs310, 0;
|
|
st.global.v4.u16 [%rd38], {%rs307, %rs308, %rs309, %rs310};
|
|
|
|
$L__BB0_187:
|
|
ld.const.u64 %rd148, [params+384];
|
|
cvta.to.global.u64 %rd149, %rd148;
|
|
ld.const.u32 %r368, [params+376];
|
|
mad.lo.s32 %r369, %r368, %r4, %r3;
|
|
mul.wide.u32 %rd150, %r369, 8;
|
|
add.s64 %rd39, %rd149, %rd150;
|
|
@%p172 bra $L__BB0_189;
|
|
|
|
ld.global.v4.u16 {%rs317, %rs318, %rs319, %rs320}, [%rd39];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1194, %rs317;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1195, %rs318;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1196, %rs319;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1197, %f1194, 0f00000000;
|
|
add.f32 %f1198, %f1195, 0f00000000;
|
|
add.f32 %f1199, %f1196, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs316, %f1199;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs315, %f1198;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs314, %f1197;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs321, 0;
|
|
st.global.v4.u16 [%rd39], {%rs314, %rs315, %rs316, %rs321};
|
|
bra.uni $L__BB0_190;
|
|
|
|
$L__BB0_189:
|
|
mov.f32 %f1202, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs324, %f1202;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs323, %f1202;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs322, %f1202;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs325, 0;
|
|
st.global.v4.u16 [%rd39], {%rs322, %rs323, %rs324, %rs325};
|
|
bra.uni $L__BB0_190;
|
|
|
|
$L__BB0_40:
|
|
mov.b32 %r222, %f1274;
|
|
xor.b32 %r223, %r222, -2147483648;
|
|
mov.b32 %f451, %r223;
|
|
selp.f32 %f1276, %f451, %f1274, %p1;
|
|
setp.geu.f32 %p50, %f64, 0f00000000;
|
|
@%p50 bra $L__BB0_44;
|
|
|
|
mov.f32 %f452, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f453, %f452;
|
|
setp.eq.f32 %p51, %f453, 0f3EE8BA2E;
|
|
@%p51 bra $L__BB0_44;
|
|
|
|
mov.f32 %f1276, 0f7FFFFFFF;
|
|
|
|
$L__BB0_44:
|
|
abs.f32 %f1215, %f64;
|
|
add.f32 %f456, %f1215, 0f3EE8BA2E;
|
|
mov.b32 %r224, %f456;
|
|
setp.lt.s32 %p53, %r224, 2139095040;
|
|
@%p53 bra $L__BB0_49;
|
|
|
|
abs.f32 %f1216, %f64;
|
|
setp.gtu.f32 %p54, %f1216, 0f7F800000;
|
|
@%p54 bra $L__BB0_48;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f1276, %f64, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_46:
|
|
abs.f32 %f1217, %f64;
|
|
setp.neu.f32 %p55, %f1217, 0f7F800000;
|
|
@%p55 bra $L__BB0_49;
|
|
|
|
selp.f32 %f1276, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_49:
|
|
ld.const.u32 %r375, [params+184];
|
|
mad.lo.s32 %r374, %r375, %r4, %r3;
|
|
cvt.u64.u32 %rd156, %r374;
|
|
ld.const.u64 %rd155, [params+192];
|
|
cvta.to.global.u64 %rd154, %rd155;
|
|
mul.f32 %f457, %f1276, 0f437F0000;
|
|
setp.eq.f32 %p56, %f64, 0f3F800000;
|
|
selp.f32 %f458, 0f437F0000, %f457, %p56;
|
|
cvt.rzi.u32.f32 %r225, %f458;
|
|
shl.b64 %rd78, %rd156, 1;
|
|
add.s64 %rd79, %rd154, %rd78;
|
|
cvt.u16.u32 %rs17, %r225;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v2.u8 [%rd79], {%rs17, %rs18};
|
|
|
|
$L__BB0_50:
|
|
ld.const.u32 %r373, [params+104];
|
|
and.b32 %r226, %r373, 1;
|
|
setp.eq.b32 %p57, %r226, 1;
|
|
mov.pred %p58, 0;
|
|
xor.pred %p59, %p57, %p58;
|
|
not.pred %p60, %p59;
|
|
@%p60 bra $L__BB0_124;
|
|
|
|
mov.f32 %f463, 0f3EE66666;
|
|
abs.f32 %f84, %f68;
|
|
setp.lt.f32 %p61, %f84, 0f00800000;
|
|
mul.f32 %f465, %f84, 0f4B800000;
|
|
selp.f32 %f466, %f465, %f84, %p61;
|
|
selp.f32 %f467, 0fC3170000, 0fC2FE0000, %p61;
|
|
mov.b32 %r227, %f466;
|
|
and.b32 %r228, %r227, 8388607;
|
|
or.b32 %r229, %r228, 1065353216;
|
|
mov.b32 %f468, %r229;
|
|
shr.u32 %r230, %r227, 23;
|
|
cvt.rn.f32.u32 %f469, %r230;
|
|
add.f32 %f470, %f467, %f469;
|
|
setp.gt.f32 %p62, %f468, 0f3FB504F3;
|
|
mul.f32 %f471, %f468, 0f3F000000;
|
|
add.f32 %f472, %f470, 0f3F800000;
|
|
selp.f32 %f473, %f472, %f470, %p62;
|
|
selp.f32 %f474, %f471, %f468, %p62;
|
|
add.f32 %f475, %f474, 0fBF800000;
|
|
add.f32 %f476, %f474, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f477, %f476;
|
|
add.f32 %f478, %f475, %f475;
|
|
mul.f32 %f479, %f478, %f477;
|
|
mul.f32 %f480, %f479, %f479;
|
|
mov.f32 %f481, 0f3C4CAF63;
|
|
mov.f32 %f482, 0f3B18F0FE;
|
|
fma.rn.f32 %f483, %f482, %f480, %f481;
|
|
mov.f32 %f484, 0f3DAAAABD;
|
|
fma.rn.f32 %f485, %f483, %f480, %f484;
|
|
mul.rn.f32 %f486, %f485, %f480;
|
|
mul.rn.f32 %f487, %f486, %f479;
|
|
sub.f32 %f488, %f475, %f479;
|
|
add.f32 %f489, %f488, %f488;
|
|
neg.f32 %f490, %f479;
|
|
fma.rn.f32 %f491, %f490, %f475, %f489;
|
|
mul.rn.f32 %f492, %f477, %f491;
|
|
add.f32 %f493, %f487, %f479;
|
|
sub.f32 %f494, %f479, %f493;
|
|
add.f32 %f495, %f487, %f494;
|
|
add.f32 %f496, %f492, %f495;
|
|
add.f32 %f497, %f493, %f496;
|
|
sub.f32 %f498, %f493, %f497;
|
|
add.f32 %f499, %f496, %f498;
|
|
mov.f32 %f500, 0f3F317200;
|
|
mul.rn.f32 %f501, %f473, %f500;
|
|
mov.f32 %f502, 0f35BFBE8E;
|
|
mul.rn.f32 %f503, %f473, %f502;
|
|
add.f32 %f504, %f501, %f497;
|
|
sub.f32 %f505, %f501, %f504;
|
|
add.f32 %f506, %f497, %f505;
|
|
add.f32 %f507, %f499, %f506;
|
|
add.f32 %f508, %f503, %f507;
|
|
add.f32 %f509, %f504, %f508;
|
|
sub.f32 %f510, %f504, %f509;
|
|
add.f32 %f511, %f508, %f510;
|
|
mul.rn.f32 %f512, %f463, %f509;
|
|
neg.f32 %f513, %f512;
|
|
fma.rn.f32 %f514, %f463, %f509, %f513;
|
|
fma.rn.f32 %f515, %f463, %f511, %f514;
|
|
mov.f32 %f516, 0f00000000;
|
|
fma.rn.f32 %f517, %f516, %f509, %f515;
|
|
add.rn.f32 %f518, %f512, %f517;
|
|
neg.f32 %f519, %f518;
|
|
add.rn.f32 %f520, %f512, %f519;
|
|
add.rn.f32 %f521, %f520, %f517;
|
|
mov.b32 %r231, %f518;
|
|
setp.eq.s32 %p63, %r231, 1118925336;
|
|
add.s32 %r232, %r231, -1;
|
|
mov.b32 %f522, %r232;
|
|
add.f32 %f523, %f521, 0f37000000;
|
|
selp.f32 %f85, %f523, %f521, %p63;
|
|
selp.f32 %f524, %f522, %f518, %p63;
|
|
mov.f32 %f525, 0f3FB8AA3B;
|
|
mul.rn.f32 %f526, %f524, %f525;
|
|
cvt.rzi.f32.f32 %f527, %f526;
|
|
abs.f32 %f528, %f527;
|
|
setp.gt.f32 %p64, %f528, 0f42FC0000;
|
|
mov.b32 %r233, %f527;
|
|
and.b32 %r234, %r233, -2147483648;
|
|
or.b32 %r235, %r234, 1123811328;
|
|
mov.b32 %f529, %r235;
|
|
selp.f32 %f530, %f529, %f527, %p64;
|
|
mov.f32 %f531, 0fBF317218;
|
|
fma.rn.f32 %f532, %f530, %f531, %f524;
|
|
mov.f32 %f533, 0f3102E308;
|
|
fma.rn.f32 %f534, %f530, %f533, %f532;
|
|
mul.f32 %f535, %f534, 0f3FB8AA3B;
|
|
add.f32 %f536, %f530, 0f4B40007F;
|
|
mov.b32 %r236, %f536;
|
|
shl.b32 %r237, %r236, 23;
|
|
mov.b32 %f537, %r237;
|
|
ex2.approx.ftz.f32 %f538, %f535;
|
|
mul.f32 %f86, %f538, %f537;
|
|
setp.eq.f32 %p65, %f86, 0f7F800000;
|
|
mov.f32 %f1277, 0f7F800000;
|
|
@%p65 bra $L__BB0_53;
|
|
|
|
fma.rn.f32 %f1277, %f86, %f85, %f86;
|
|
|
|
$L__BB0_53:
|
|
mov.f32 %f1223, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f1222, %f1223;
|
|
add.f32 %f1221, %f1222, %f1222;
|
|
mov.f32 %f1220, 0f3EE66666;
|
|
sub.f32 %f1219, %f1220, %f1221;
|
|
abs.f32 %f1218, %f1219;
|
|
setp.lt.f32 %p66, %f68, 0f00000000;
|
|
setp.eq.f32 %p67, %f1218, 0f3F800000;
|
|
and.pred %p2, %p66, %p67;
|
|
setp.eq.f32 %p68, %f68, 0f00000000;
|
|
@%p68 bra $L__BB0_57;
|
|
bra.uni $L__BB0_54;
|
|
|
|
$L__BB0_57:
|
|
add.f32 %f543, %f68, %f68;
|
|
selp.f32 %f1279, %f543, 0f00000000, %p67;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_54:
|
|
mov.b32 %r238, %f1277;
|
|
xor.b32 %r239, %r238, -2147483648;
|
|
mov.b32 %f539, %r239;
|
|
selp.f32 %f1279, %f539, %f1277, %p2;
|
|
setp.geu.f32 %p69, %f68, 0f00000000;
|
|
@%p69 bra $L__BB0_58;
|
|
|
|
mov.f32 %f540, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f541, %f540;
|
|
setp.eq.f32 %p70, %f541, 0f3EE66666;
|
|
@%p70 bra $L__BB0_58;
|
|
|
|
mov.f32 %f1279, 0f7FFFFFFF;
|
|
|
|
$L__BB0_58:
|
|
abs.f32 %f1224, %f68;
|
|
add.f32 %f544, %f1224, 0f3EE66666;
|
|
mov.b32 %r240, %f544;
|
|
setp.lt.s32 %p72, %r240, 2139095040;
|
|
@%p72 bra $L__BB0_63;
|
|
|
|
abs.f32 %f1225, %f68;
|
|
setp.gtu.f32 %p73, %f1225, 0f7F800000;
|
|
@%p73 bra $L__BB0_62;
|
|
bra.uni $L__BB0_60;
|
|
|
|
$L__BB0_62:
|
|
add.f32 %f1279, %f68, 0f3EE66666;
|
|
bra.uni $L__BB0_63;
|
|
|
|
$L__BB0_60:
|
|
abs.f32 %f1226, %f68;
|
|
setp.neu.f32 %p74, %f1226, 0f7F800000;
|
|
@%p74 bra $L__BB0_63;
|
|
|
|
selp.f32 %f1279, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_63:
|
|
setp.eq.f32 %p75, %f68, 0f3F800000;
|
|
selp.f32 %f95, 0f3F800000, %f1279, %p75;
|
|
abs.f32 %f96, %f69;
|
|
setp.lt.f32 %p76, %f96, 0f00800000;
|
|
mul.f32 %f546, %f96, 0f4B800000;
|
|
selp.f32 %f547, %f546, %f96, %p76;
|
|
selp.f32 %f548, 0fC3170000, 0fC2FE0000, %p76;
|
|
mov.b32 %r241, %f547;
|
|
and.b32 %r242, %r241, 8388607;
|
|
or.b32 %r243, %r242, 1065353216;
|
|
mov.b32 %f549, %r243;
|
|
shr.u32 %r244, %r241, 23;
|
|
cvt.rn.f32.u32 %f550, %r244;
|
|
add.f32 %f551, %f548, %f550;
|
|
setp.gt.f32 %p77, %f549, 0f3FB504F3;
|
|
mul.f32 %f552, %f549, 0f3F000000;
|
|
add.f32 %f553, %f551, 0f3F800000;
|
|
selp.f32 %f554, %f553, %f551, %p77;
|
|
selp.f32 %f555, %f552, %f549, %p77;
|
|
add.f32 %f556, %f555, 0fBF800000;
|
|
add.f32 %f557, %f555, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f558, %f557;
|
|
add.f32 %f559, %f556, %f556;
|
|
mul.f32 %f560, %f559, %f558;
|
|
mul.f32 %f561, %f560, %f560;
|
|
mov.f32 %f562, 0f3C4CAF63;
|
|
mov.f32 %f563, 0f3B18F0FE;
|
|
fma.rn.f32 %f564, %f563, %f561, %f562;
|
|
mov.f32 %f565, 0f3DAAAABD;
|
|
fma.rn.f32 %f566, %f564, %f561, %f565;
|
|
mul.rn.f32 %f567, %f566, %f561;
|
|
mul.rn.f32 %f568, %f567, %f560;
|
|
sub.f32 %f569, %f556, %f560;
|
|
add.f32 %f570, %f569, %f569;
|
|
neg.f32 %f571, %f560;
|
|
fma.rn.f32 %f572, %f571, %f556, %f570;
|
|
mul.rn.f32 %f573, %f558, %f572;
|
|
add.f32 %f574, %f568, %f560;
|
|
sub.f32 %f575, %f560, %f574;
|
|
add.f32 %f576, %f568, %f575;
|
|
add.f32 %f577, %f573, %f576;
|
|
add.f32 %f578, %f574, %f577;
|
|
sub.f32 %f579, %f574, %f578;
|
|
add.f32 %f580, %f577, %f579;
|
|
mov.f32 %f581, 0f3F317200;
|
|
mul.rn.f32 %f582, %f554, %f581;
|
|
mov.f32 %f583, 0f35BFBE8E;
|
|
mul.rn.f32 %f584, %f554, %f583;
|
|
add.f32 %f585, %f582, %f578;
|
|
sub.f32 %f586, %f582, %f585;
|
|
add.f32 %f587, %f578, %f586;
|
|
add.f32 %f588, %f580, %f587;
|
|
add.f32 %f589, %f584, %f588;
|
|
add.f32 %f590, %f585, %f589;
|
|
sub.f32 %f591, %f585, %f590;
|
|
add.f32 %f592, %f589, %f591;
|
|
mov.f32 %f593, 0f3EE66666;
|
|
mul.rn.f32 %f594, %f593, %f590;
|
|
neg.f32 %f595, %f594;
|
|
fma.rn.f32 %f596, %f593, %f590, %f595;
|
|
fma.rn.f32 %f597, %f593, %f592, %f596;
|
|
mov.f32 %f598, 0f00000000;
|
|
fma.rn.f32 %f599, %f598, %f590, %f597;
|
|
add.rn.f32 %f600, %f594, %f599;
|
|
neg.f32 %f601, %f600;
|
|
add.rn.f32 %f602, %f594, %f601;
|
|
add.rn.f32 %f603, %f602, %f599;
|
|
mov.b32 %r245, %f600;
|
|
setp.eq.s32 %p78, %r245, 1118925336;
|
|
add.s32 %r246, %r245, -1;
|
|
mov.b32 %f604, %r246;
|
|
add.f32 %f605, %f603, 0f37000000;
|
|
selp.f32 %f97, %f605, %f603, %p78;
|
|
selp.f32 %f606, %f604, %f600, %p78;
|
|
mov.f32 %f607, 0f3FB8AA3B;
|
|
mul.rn.f32 %f608, %f606, %f607;
|
|
cvt.rzi.f32.f32 %f609, %f608;
|
|
abs.f32 %f610, %f609;
|
|
setp.gt.f32 %p79, %f610, 0f42FC0000;
|
|
mov.b32 %r247, %f609;
|
|
and.b32 %r248, %r247, -2147483648;
|
|
or.b32 %r249, %r248, 1123811328;
|
|
mov.b32 %f611, %r249;
|
|
selp.f32 %f612, %f611, %f609, %p79;
|
|
mov.f32 %f613, 0fBF317218;
|
|
fma.rn.f32 %f614, %f612, %f613, %f606;
|
|
mov.f32 %f615, 0f3102E308;
|
|
fma.rn.f32 %f616, %f612, %f615, %f614;
|
|
mul.f32 %f617, %f616, 0f3FB8AA3B;
|
|
add.f32 %f618, %f612, 0f4B40007F;
|
|
mov.b32 %r250, %f618;
|
|
shl.b32 %r251, %r250, 23;
|
|
mov.b32 %f619, %r251;
|
|
ex2.approx.ftz.f32 %f620, %f617;
|
|
mul.f32 %f98, %f620, %f619;
|
|
setp.eq.f32 %p80, %f98, 0f7F800000;
|
|
mov.f32 %f1280, 0f7F800000;
|
|
@%p80 bra $L__BB0_65;
|
|
|
|
fma.rn.f32 %f1280, %f98, %f97, %f98;
|
|
|
|
$L__BB0_65:
|
|
setp.lt.f32 %p81, %f69, 0f00000000;
|
|
and.pred %p3, %p81, %p67;
|
|
setp.eq.f32 %p83, %f69, 0f00000000;
|
|
@%p83 bra $L__BB0_69;
|
|
bra.uni $L__BB0_66;
|
|
|
|
$L__BB0_69:
|
|
add.f32 %f625, %f69, %f69;
|
|
selp.f32 %f1282, %f625, 0f00000000, %p67;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_66:
|
|
mov.b32 %r252, %f1280;
|
|
xor.b32 %r253, %r252, -2147483648;
|
|
mov.b32 %f621, %r253;
|
|
selp.f32 %f1282, %f621, %f1280, %p3;
|
|
setp.geu.f32 %p84, %f69, 0f00000000;
|
|
@%p84 bra $L__BB0_70;
|
|
|
|
mov.f32 %f622, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f623, %f622;
|
|
setp.eq.f32 %p85, %f623, 0f3EE66666;
|
|
@%p85 bra $L__BB0_70;
|
|
|
|
mov.f32 %f1282, 0f7FFFFFFF;
|
|
|
|
$L__BB0_70:
|
|
abs.f32 %f1227, %f69;
|
|
add.f32 %f626, %f1227, 0f3EE66666;
|
|
mov.b32 %r254, %f626;
|
|
setp.lt.s32 %p87, %r254, 2139095040;
|
|
@%p87 bra $L__BB0_75;
|
|
|
|
abs.f32 %f1228, %f69;
|
|
setp.gtu.f32 %p88, %f1228, 0f7F800000;
|
|
@%p88 bra $L__BB0_74;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_74:
|
|
add.f32 %f1282, %f69, 0f3EE66666;
|
|
bra.uni $L__BB0_75;
|
|
|
|
$L__BB0_72:
|
|
abs.f32 %f1229, %f69;
|
|
setp.neu.f32 %p89, %f1229, 0f7F800000;
|
|
@%p89 bra $L__BB0_75;
|
|
|
|
selp.f32 %f1282, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_75:
|
|
setp.eq.f32 %p90, %f69, 0f3F800000;
|
|
selp.f32 %f107, 0f3F800000, %f1282, %p90;
|
|
abs.f32 %f108, %f70;
|
|
setp.lt.f32 %p91, %f108, 0f00800000;
|
|
mul.f32 %f628, %f108, 0f4B800000;
|
|
selp.f32 %f629, %f628, %f108, %p91;
|
|
selp.f32 %f630, 0fC3170000, 0fC2FE0000, %p91;
|
|
mov.b32 %r255, %f629;
|
|
and.b32 %r256, %r255, 8388607;
|
|
or.b32 %r257, %r256, 1065353216;
|
|
mov.b32 %f631, %r257;
|
|
shr.u32 %r258, %r255, 23;
|
|
cvt.rn.f32.u32 %f632, %r258;
|
|
add.f32 %f633, %f630, %f632;
|
|
setp.gt.f32 %p92, %f631, 0f3FB504F3;
|
|
mul.f32 %f634, %f631, 0f3F000000;
|
|
add.f32 %f635, %f633, 0f3F800000;
|
|
selp.f32 %f636, %f635, %f633, %p92;
|
|
selp.f32 %f637, %f634, %f631, %p92;
|
|
add.f32 %f638, %f637, 0fBF800000;
|
|
add.f32 %f639, %f637, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f640, %f639;
|
|
add.f32 %f641, %f638, %f638;
|
|
mul.f32 %f642, %f641, %f640;
|
|
mul.f32 %f643, %f642, %f642;
|
|
mov.f32 %f644, 0f3C4CAF63;
|
|
mov.f32 %f645, 0f3B18F0FE;
|
|
fma.rn.f32 %f646, %f645, %f643, %f644;
|
|
mov.f32 %f647, 0f3DAAAABD;
|
|
fma.rn.f32 %f648, %f646, %f643, %f647;
|
|
mul.rn.f32 %f649, %f648, %f643;
|
|
mul.rn.f32 %f650, %f649, %f642;
|
|
sub.f32 %f651, %f638, %f642;
|
|
add.f32 %f652, %f651, %f651;
|
|
neg.f32 %f653, %f642;
|
|
fma.rn.f32 %f654, %f653, %f638, %f652;
|
|
mul.rn.f32 %f655, %f640, %f654;
|
|
add.f32 %f656, %f650, %f642;
|
|
sub.f32 %f657, %f642, %f656;
|
|
add.f32 %f658, %f650, %f657;
|
|
add.f32 %f659, %f655, %f658;
|
|
add.f32 %f660, %f656, %f659;
|
|
sub.f32 %f661, %f656, %f660;
|
|
add.f32 %f662, %f659, %f661;
|
|
mov.f32 %f663, 0f3F317200;
|
|
mul.rn.f32 %f664, %f636, %f663;
|
|
mov.f32 %f665, 0f35BFBE8E;
|
|
mul.rn.f32 %f666, %f636, %f665;
|
|
add.f32 %f667, %f664, %f660;
|
|
sub.f32 %f668, %f664, %f667;
|
|
add.f32 %f669, %f660, %f668;
|
|
add.f32 %f670, %f662, %f669;
|
|
add.f32 %f671, %f666, %f670;
|
|
add.f32 %f672, %f667, %f671;
|
|
sub.f32 %f673, %f667, %f672;
|
|
add.f32 %f674, %f671, %f673;
|
|
mov.f32 %f675, 0f3EE66666;
|
|
mul.rn.f32 %f676, %f675, %f672;
|
|
neg.f32 %f677, %f676;
|
|
fma.rn.f32 %f678, %f675, %f672, %f677;
|
|
fma.rn.f32 %f679, %f675, %f674, %f678;
|
|
mov.f32 %f680, 0f00000000;
|
|
fma.rn.f32 %f681, %f680, %f672, %f679;
|
|
add.rn.f32 %f682, %f676, %f681;
|
|
neg.f32 %f683, %f682;
|
|
add.rn.f32 %f684, %f676, %f683;
|
|
add.rn.f32 %f685, %f684, %f681;
|
|
mov.b32 %r259, %f682;
|
|
setp.eq.s32 %p93, %r259, 1118925336;
|
|
add.s32 %r260, %r259, -1;
|
|
mov.b32 %f686, %r260;
|
|
add.f32 %f687, %f685, 0f37000000;
|
|
selp.f32 %f109, %f687, %f685, %p93;
|
|
selp.f32 %f688, %f686, %f682, %p93;
|
|
mov.f32 %f689, 0f3FB8AA3B;
|
|
mul.rn.f32 %f690, %f688, %f689;
|
|
cvt.rzi.f32.f32 %f691, %f690;
|
|
abs.f32 %f692, %f691;
|
|
setp.gt.f32 %p94, %f692, 0f42FC0000;
|
|
mov.b32 %r261, %f691;
|
|
and.b32 %r262, %r261, -2147483648;
|
|
or.b32 %r263, %r262, 1123811328;
|
|
mov.b32 %f693, %r263;
|
|
selp.f32 %f694, %f693, %f691, %p94;
|
|
mov.f32 %f695, 0fBF317218;
|
|
fma.rn.f32 %f696, %f694, %f695, %f688;
|
|
mov.f32 %f697, 0f3102E308;
|
|
fma.rn.f32 %f698, %f694, %f697, %f696;
|
|
mul.f32 %f699, %f698, 0f3FB8AA3B;
|
|
add.f32 %f700, %f694, 0f4B40007F;
|
|
mov.b32 %r264, %f700;
|
|
shl.b32 %r265, %r264, 23;
|
|
mov.b32 %f701, %r265;
|
|
ex2.approx.ftz.f32 %f702, %f699;
|
|
mul.f32 %f110, %f702, %f701;
|
|
setp.eq.f32 %p95, %f110, 0f7F800000;
|
|
mov.f32 %f1283, 0f7F800000;
|
|
@%p95 bra $L__BB0_77;
|
|
|
|
fma.rn.f32 %f1283, %f110, %f109, %f110;
|
|
|
|
$L__BB0_77:
|
|
setp.lt.f32 %p96, %f70, 0f00000000;
|
|
and.pred %p4, %p96, %p67;
|
|
setp.eq.f32 %p98, %f70, 0f00000000;
|
|
@%p98 bra $L__BB0_81;
|
|
bra.uni $L__BB0_78;
|
|
|
|
$L__BB0_81:
|
|
add.f32 %f707, %f70, %f70;
|
|
selp.f32 %f1285, %f707, 0f00000000, %p67;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_78:
|
|
mov.b32 %r266, %f1283;
|
|
xor.b32 %r267, %r266, -2147483648;
|
|
mov.b32 %f703, %r267;
|
|
selp.f32 %f1285, %f703, %f1283, %p4;
|
|
setp.geu.f32 %p99, %f70, 0f00000000;
|
|
@%p99 bra $L__BB0_82;
|
|
|
|
mov.f32 %f704, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f705, %f704;
|
|
setp.eq.f32 %p100, %f705, 0f3EE66666;
|
|
@%p100 bra $L__BB0_82;
|
|
|
|
mov.f32 %f1285, 0f7FFFFFFF;
|
|
|
|
$L__BB0_82:
|
|
abs.f32 %f1230, %f70;
|
|
add.f32 %f708, %f1230, 0f3EE66666;
|
|
mov.b32 %r268, %f708;
|
|
setp.lt.s32 %p102, %r268, 2139095040;
|
|
@%p102 bra $L__BB0_87;
|
|
|
|
abs.f32 %f1231, %f70;
|
|
setp.gtu.f32 %p103, %f1231, 0f7F800000;
|
|
@%p103 bra $L__BB0_86;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_86:
|
|
add.f32 %f1285, %f70, 0f3EE66666;
|
|
bra.uni $L__BB0_87;
|
|
|
|
$L__BB0_84:
|
|
abs.f32 %f1232, %f70;
|
|
setp.neu.f32 %p104, %f1232, 0f7F800000;
|
|
@%p104 bra $L__BB0_87;
|
|
|
|
selp.f32 %f1285, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_87:
|
|
setp.eq.f32 %p105, %f70, 0f3F800000;
|
|
mov.f32 %f710, 0f3F800000;
|
|
selp.f32 %f711, 0f3F800000, %f1285, %p105;
|
|
min.f32 %f712, %f95, %f710;
|
|
mov.f32 %f713, 0f00000000;
|
|
max.f32 %f119, %f713, %f712;
|
|
min.f32 %f714, %f107, %f710;
|
|
max.f32 %f120, %f713, %f714;
|
|
min.f32 %f715, %f711, %f710;
|
|
max.f32 %f121, %f713, %f715;
|
|
mov.f32 %f719, 0f3ED55555;
|
|
abs.f32 %f123, %f119;
|
|
setp.lt.f32 %p106, %f123, 0f00800000;
|
|
mul.f32 %f721, %f123, 0f4B800000;
|
|
selp.f32 %f722, %f721, %f123, %p106;
|
|
selp.f32 %f723, 0fC3170000, 0fC2FE0000, %p106;
|
|
mov.b32 %r271, %f722;
|
|
and.b32 %r272, %r271, 8388607;
|
|
or.b32 %r273, %r272, 1065353216;
|
|
mov.b32 %f724, %r273;
|
|
shr.u32 %r274, %r271, 23;
|
|
cvt.rn.f32.u32 %f725, %r274;
|
|
add.f32 %f726, %f723, %f725;
|
|
setp.gt.f32 %p107, %f724, 0f3FB504F3;
|
|
mul.f32 %f727, %f724, 0f3F000000;
|
|
add.f32 %f728, %f726, 0f3F800000;
|
|
selp.f32 %f729, %f728, %f726, %p107;
|
|
selp.f32 %f730, %f727, %f724, %p107;
|
|
add.f32 %f731, %f730, 0fBF800000;
|
|
add.f32 %f732, %f730, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f733, %f732;
|
|
add.f32 %f734, %f731, %f731;
|
|
mul.f32 %f735, %f734, %f733;
|
|
mul.f32 %f736, %f735, %f735;
|
|
mov.f32 %f737, 0f3C4CAF63;
|
|
mov.f32 %f738, 0f3B18F0FE;
|
|
fma.rn.f32 %f739, %f738, %f736, %f737;
|
|
mov.f32 %f740, 0f3DAAAABD;
|
|
fma.rn.f32 %f741, %f739, %f736, %f740;
|
|
mul.rn.f32 %f742, %f741, %f736;
|
|
mul.rn.f32 %f743, %f742, %f735;
|
|
sub.f32 %f744, %f731, %f735;
|
|
add.f32 %f745, %f744, %f744;
|
|
neg.f32 %f746, %f735;
|
|
fma.rn.f32 %f747, %f746, %f731, %f745;
|
|
mul.rn.f32 %f748, %f733, %f747;
|
|
add.f32 %f749, %f743, %f735;
|
|
sub.f32 %f750, %f735, %f749;
|
|
add.f32 %f751, %f743, %f750;
|
|
add.f32 %f752, %f748, %f751;
|
|
add.f32 %f753, %f749, %f752;
|
|
sub.f32 %f754, %f749, %f753;
|
|
add.f32 %f755, %f752, %f754;
|
|
mov.f32 %f756, 0f3F317200;
|
|
mul.rn.f32 %f757, %f729, %f756;
|
|
mov.f32 %f758, 0f35BFBE8E;
|
|
mul.rn.f32 %f759, %f729, %f758;
|
|
add.f32 %f760, %f757, %f753;
|
|
sub.f32 %f761, %f757, %f760;
|
|
add.f32 %f762, %f753, %f761;
|
|
add.f32 %f763, %f755, %f762;
|
|
add.f32 %f764, %f759, %f763;
|
|
add.f32 %f765, %f760, %f764;
|
|
sub.f32 %f766, %f760, %f765;
|
|
add.f32 %f767, %f764, %f766;
|
|
mul.rn.f32 %f768, %f719, %f765;
|
|
neg.f32 %f769, %f768;
|
|
fma.rn.f32 %f770, %f719, %f765, %f769;
|
|
fma.rn.f32 %f771, %f719, %f767, %f770;
|
|
fma.rn.f32 %f772, %f713, %f765, %f771;
|
|
add.rn.f32 %f773, %f768, %f772;
|
|
neg.f32 %f774, %f773;
|
|
add.rn.f32 %f775, %f768, %f774;
|
|
add.rn.f32 %f776, %f775, %f772;
|
|
mov.b32 %r275, %f773;
|
|
setp.eq.s32 %p108, %r275, 1118925336;
|
|
add.s32 %r276, %r275, -1;
|
|
mov.b32 %f777, %r276;
|
|
add.f32 %f778, %f776, 0f37000000;
|
|
selp.f32 %f124, %f778, %f776, %p108;
|
|
selp.f32 %f779, %f777, %f773, %p108;
|
|
mov.f32 %f780, 0f3FB8AA3B;
|
|
mul.rn.f32 %f781, %f779, %f780;
|
|
cvt.rzi.f32.f32 %f782, %f781;
|
|
abs.f32 %f783, %f782;
|
|
setp.gt.f32 %p109, %f783, 0f42FC0000;
|
|
mov.b32 %r277, %f782;
|
|
and.b32 %r278, %r277, -2147483648;
|
|
or.b32 %r279, %r278, 1123811328;
|
|
mov.b32 %f784, %r279;
|
|
selp.f32 %f785, %f784, %f782, %p109;
|
|
mov.f32 %f786, 0fBF317218;
|
|
fma.rn.f32 %f787, %f785, %f786, %f779;
|
|
mov.f32 %f788, 0f3102E308;
|
|
fma.rn.f32 %f789, %f785, %f788, %f787;
|
|
mul.f32 %f790, %f789, 0f3FB8AA3B;
|
|
add.f32 %f791, %f785, 0f4B40007F;
|
|
mov.b32 %r280, %f791;
|
|
shl.b32 %r281, %r280, 23;
|
|
mov.b32 %f792, %r281;
|
|
ex2.approx.ftz.f32 %f793, %f790;
|
|
mul.f32 %f125, %f793, %f792;
|
|
setp.eq.f32 %p110, %f125, 0f7F800000;
|
|
mov.f32 %f1286, 0f7F800000;
|
|
@%p110 bra $L__BB0_89;
|
|
|
|
fma.rn.f32 %f1286, %f125, %f124, %f125;
|
|
|
|
$L__BB0_89:
|
|
mov.f32 %f1243, 0f00000000;
|
|
max.f32 %f1242, %f1243, %f712;
|
|
mov.f32 %f1208, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1207, %f1208;
|
|
add.f32 %f1206, %f1207, %f1207;
|
|
mov.f32 %f1205, 0f3ED55555;
|
|
sub.f32 %f1204, %f1205, %f1206;
|
|
abs.f32 %f1203, %f1204;
|
|
setp.lt.f32 %p111, %f1242, 0f00000000;
|
|
setp.eq.f32 %p112, %f1203, 0f3F800000;
|
|
and.pred %p5, %p111, %p112;
|
|
setp.eq.f32 %p113, %f1242, 0f00000000;
|
|
@%p113 bra $L__BB0_93;
|
|
bra.uni $L__BB0_90;
|
|
|
|
$L__BB0_93:
|
|
mov.f32 %f1260, 0f00000000;
|
|
max.f32 %f1259, %f1260, %f712;
|
|
add.f32 %f798, %f1259, %f1259;
|
|
selp.f32 %f1288, %f798, 0f00000000, %p112;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_90:
|
|
mov.f32 %f1245, 0f00000000;
|
|
max.f32 %f1244, %f1245, %f712;
|
|
mov.b32 %r282, %f1286;
|
|
xor.b32 %r283, %r282, -2147483648;
|
|
mov.b32 %f794, %r283;
|
|
selp.f32 %f1288, %f794, %f1286, %p5;
|
|
setp.geu.f32 %p114, %f1244, 0f00000000;
|
|
@%p114 bra $L__BB0_94;
|
|
|
|
mov.f32 %f795, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f796, %f795;
|
|
setp.eq.f32 %p115, %f796, 0f3ED55555;
|
|
@%p115 bra $L__BB0_94;
|
|
|
|
mov.f32 %f1288, 0f7FFFFFFF;
|
|
|
|
$L__BB0_94:
|
|
mov.f32 %f1248, 0f00000000;
|
|
max.f32 %f1247, %f1248, %f712;
|
|
abs.f32 %f1246, %f1247;
|
|
add.f32 %f799, %f1246, 0f3ED55555;
|
|
mov.b32 %r284, %f799;
|
|
setp.lt.s32 %p117, %r284, 2139095040;
|
|
@%p117 bra $L__BB0_99;
|
|
|
|
mov.f32 %f1253, 0f00000000;
|
|
max.f32 %f1252, %f1253, %f712;
|
|
abs.f32 %f1251, %f1252;
|
|
setp.gtu.f32 %p118, %f1251, 0f7F800000;
|
|
@%p118 bra $L__BB0_98;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_98:
|
|
mov.f32 %f1258, 0f00000000;
|
|
max.f32 %f1257, %f1258, %f712;
|
|
add.f32 %f1288, %f1257, 0f3ED55555;
|
|
bra.uni $L__BB0_99;
|
|
|
|
$L__BB0_96:
|
|
mov.f32 %f1256, 0f00000000;
|
|
max.f32 %f1255, %f1256, %f712;
|
|
abs.f32 %f1254, %f1255;
|
|
setp.neu.f32 %p119, %f1254, 0f7F800000;
|
|
@%p119 bra $L__BB0_99;
|
|
|
|
selp.f32 %f1288, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_99:
|
|
abs.f32 %f134, %f120;
|
|
setp.lt.f32 %p120, %f134, 0f00800000;
|
|
mul.f32 %f801, %f134, 0f4B800000;
|
|
selp.f32 %f802, %f801, %f134, %p120;
|
|
selp.f32 %f803, 0fC3170000, 0fC2FE0000, %p120;
|
|
mov.b32 %r285, %f802;
|
|
and.b32 %r286, %r285, 8388607;
|
|
or.b32 %r287, %r286, 1065353216;
|
|
mov.b32 %f804, %r287;
|
|
shr.u32 %r288, %r285, 23;
|
|
cvt.rn.f32.u32 %f805, %r288;
|
|
add.f32 %f806, %f803, %f805;
|
|
setp.gt.f32 %p121, %f804, 0f3FB504F3;
|
|
mul.f32 %f807, %f804, 0f3F000000;
|
|
add.f32 %f808, %f806, 0f3F800000;
|
|
selp.f32 %f809, %f808, %f806, %p121;
|
|
selp.f32 %f810, %f807, %f804, %p121;
|
|
add.f32 %f811, %f810, 0fBF800000;
|
|
add.f32 %f812, %f810, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f813, %f812;
|
|
add.f32 %f814, %f811, %f811;
|
|
mul.f32 %f815, %f814, %f813;
|
|
mul.f32 %f816, %f815, %f815;
|
|
mov.f32 %f817, 0f3C4CAF63;
|
|
mov.f32 %f818, 0f3B18F0FE;
|
|
fma.rn.f32 %f819, %f818, %f816, %f817;
|
|
mov.f32 %f820, 0f3DAAAABD;
|
|
fma.rn.f32 %f821, %f819, %f816, %f820;
|
|
mul.rn.f32 %f822, %f821, %f816;
|
|
mul.rn.f32 %f823, %f822, %f815;
|
|
sub.f32 %f824, %f811, %f815;
|
|
add.f32 %f825, %f824, %f824;
|
|
neg.f32 %f826, %f815;
|
|
fma.rn.f32 %f827, %f826, %f811, %f825;
|
|
mul.rn.f32 %f828, %f813, %f827;
|
|
add.f32 %f829, %f823, %f815;
|
|
sub.f32 %f830, %f815, %f829;
|
|
add.f32 %f831, %f823, %f830;
|
|
add.f32 %f832, %f828, %f831;
|
|
add.f32 %f833, %f829, %f832;
|
|
sub.f32 %f834, %f829, %f833;
|
|
add.f32 %f835, %f832, %f834;
|
|
mov.f32 %f836, 0f3F317200;
|
|
mul.rn.f32 %f837, %f809, %f836;
|
|
mov.f32 %f838, 0f35BFBE8E;
|
|
mul.rn.f32 %f839, %f809, %f838;
|
|
add.f32 %f840, %f837, %f833;
|
|
sub.f32 %f841, %f837, %f840;
|
|
add.f32 %f842, %f833, %f841;
|
|
add.f32 %f843, %f835, %f842;
|
|
add.f32 %f844, %f839, %f843;
|
|
add.f32 %f845, %f840, %f844;
|
|
sub.f32 %f846, %f840, %f845;
|
|
add.f32 %f847, %f844, %f846;
|
|
mov.f32 %f848, 0f3ED55555;
|
|
mul.rn.f32 %f849, %f848, %f845;
|
|
neg.f32 %f850, %f849;
|
|
fma.rn.f32 %f851, %f848, %f845, %f850;
|
|
fma.rn.f32 %f852, %f848, %f847, %f851;
|
|
mov.f32 %f853, 0f00000000;
|
|
fma.rn.f32 %f854, %f853, %f845, %f852;
|
|
add.rn.f32 %f855, %f849, %f854;
|
|
neg.f32 %f856, %f855;
|
|
add.rn.f32 %f857, %f849, %f856;
|
|
add.rn.f32 %f858, %f857, %f854;
|
|
mov.b32 %r289, %f855;
|
|
setp.eq.s32 %p122, %r289, 1118925336;
|
|
add.s32 %r290, %r289, -1;
|
|
mov.b32 %f859, %r290;
|
|
add.f32 %f860, %f858, 0f37000000;
|
|
selp.f32 %f135, %f860, %f858, %p122;
|
|
selp.f32 %f861, %f859, %f855, %p122;
|
|
mov.f32 %f862, 0f3FB8AA3B;
|
|
mul.rn.f32 %f863, %f861, %f862;
|
|
cvt.rzi.f32.f32 %f864, %f863;
|
|
abs.f32 %f865, %f864;
|
|
setp.gt.f32 %p123, %f865, 0f42FC0000;
|
|
mov.b32 %r291, %f864;
|
|
and.b32 %r292, %r291, -2147483648;
|
|
or.b32 %r293, %r292, 1123811328;
|
|
mov.b32 %f866, %r293;
|
|
selp.f32 %f867, %f866, %f864, %p123;
|
|
mov.f32 %f868, 0fBF317218;
|
|
fma.rn.f32 %f869, %f867, %f868, %f861;
|
|
mov.f32 %f870, 0f3102E308;
|
|
fma.rn.f32 %f871, %f867, %f870, %f869;
|
|
mul.f32 %f872, %f871, 0f3FB8AA3B;
|
|
add.f32 %f873, %f867, 0f4B40007F;
|
|
mov.b32 %r294, %f873;
|
|
shl.b32 %r295, %r294, 23;
|
|
mov.b32 %f874, %r295;
|
|
ex2.approx.ftz.f32 %f875, %f872;
|
|
mul.f32 %f136, %f875, %f874;
|
|
setp.eq.f32 %p124, %f136, 0f7F800000;
|
|
mov.f32 %f1289, 0f7F800000;
|
|
@%p124 bra $L__BB0_101;
|
|
|
|
fma.rn.f32 %f1289, %f136, %f135, %f136;
|
|
|
|
$L__BB0_101:
|
|
setp.lt.f32 %p125, %f120, 0f00000000;
|
|
and.pred %p6, %p125, %p112;
|
|
setp.eq.f32 %p127, %f120, 0f00000000;
|
|
@%p127 bra $L__BB0_105;
|
|
bra.uni $L__BB0_102;
|
|
|
|
$L__BB0_105:
|
|
add.f32 %f880, %f120, %f120;
|
|
selp.f32 %f1291, %f880, 0f00000000, %p112;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_102:
|
|
mov.b32 %r296, %f1289;
|
|
xor.b32 %r297, %r296, -2147483648;
|
|
mov.b32 %f876, %r297;
|
|
selp.f32 %f1291, %f876, %f1289, %p6;
|
|
setp.geu.f32 %p128, %f120, 0f00000000;
|
|
@%p128 bra $L__BB0_106;
|
|
|
|
mov.f32 %f877, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f878, %f877;
|
|
setp.eq.f32 %p129, %f878, 0f3ED55555;
|
|
@%p129 bra $L__BB0_106;
|
|
|
|
mov.f32 %f1291, 0f7FFFFFFF;
|
|
|
|
$L__BB0_106:
|
|
mov.f32 %f1235, 0f00000000;
|
|
max.f32 %f1234, %f1235, %f714;
|
|
abs.f32 %f1233, %f1234;
|
|
add.f32 %f881, %f1233, 0f3ED55555;
|
|
mov.b32 %r298, %f881;
|
|
setp.lt.s32 %p131, %r298, 2139095040;
|
|
@%p131 bra $L__BB0_111;
|
|
|
|
mov.f32 %f1238, 0f00000000;
|
|
max.f32 %f1237, %f1238, %f714;
|
|
abs.f32 %f1236, %f1237;
|
|
setp.gtu.f32 %p132, %f1236, 0f7F800000;
|
|
@%p132 bra $L__BB0_110;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_110:
|
|
add.f32 %f1291, %f120, 0f3ED55555;
|
|
bra.uni $L__BB0_111;
|
|
|
|
$L__BB0_108:
|
|
mov.f32 %f1241, 0f00000000;
|
|
max.f32 %f1240, %f1241, %f714;
|
|
abs.f32 %f1239, %f1240;
|
|
setp.neu.f32 %p133, %f1239, 0f7F800000;
|
|
@%p133 bra $L__BB0_111;
|
|
|
|
selp.f32 %f1291, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_111:
|
|
abs.f32 %f145, %f121;
|
|
setp.lt.f32 %p134, %f145, 0f00800000;
|
|
mul.f32 %f883, %f145, 0f4B800000;
|
|
selp.f32 %f884, %f883, %f145, %p134;
|
|
selp.f32 %f885, 0fC3170000, 0fC2FE0000, %p134;
|
|
mov.b32 %r299, %f884;
|
|
and.b32 %r300, %r299, 8388607;
|
|
or.b32 %r301, %r300, 1065353216;
|
|
mov.b32 %f886, %r301;
|
|
shr.u32 %r302, %r299, 23;
|
|
cvt.rn.f32.u32 %f887, %r302;
|
|
add.f32 %f888, %f885, %f887;
|
|
setp.gt.f32 %p135, %f886, 0f3FB504F3;
|
|
mul.f32 %f889, %f886, 0f3F000000;
|
|
add.f32 %f890, %f888, 0f3F800000;
|
|
selp.f32 %f891, %f890, %f888, %p135;
|
|
selp.f32 %f892, %f889, %f886, %p135;
|
|
add.f32 %f893, %f892, 0fBF800000;
|
|
add.f32 %f894, %f892, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f895, %f894;
|
|
add.f32 %f896, %f893, %f893;
|
|
mul.f32 %f897, %f896, %f895;
|
|
mul.f32 %f898, %f897, %f897;
|
|
mov.f32 %f899, 0f3C4CAF63;
|
|
mov.f32 %f900, 0f3B18F0FE;
|
|
fma.rn.f32 %f901, %f900, %f898, %f899;
|
|
mov.f32 %f902, 0f3DAAAABD;
|
|
fma.rn.f32 %f903, %f901, %f898, %f902;
|
|
mul.rn.f32 %f904, %f903, %f898;
|
|
mul.rn.f32 %f905, %f904, %f897;
|
|
sub.f32 %f906, %f893, %f897;
|
|
add.f32 %f907, %f906, %f906;
|
|
neg.f32 %f908, %f897;
|
|
fma.rn.f32 %f909, %f908, %f893, %f907;
|
|
mul.rn.f32 %f910, %f895, %f909;
|
|
add.f32 %f911, %f905, %f897;
|
|
sub.f32 %f912, %f897, %f911;
|
|
add.f32 %f913, %f905, %f912;
|
|
add.f32 %f914, %f910, %f913;
|
|
add.f32 %f915, %f911, %f914;
|
|
sub.f32 %f916, %f911, %f915;
|
|
add.f32 %f917, %f914, %f916;
|
|
mov.f32 %f918, 0f3F317200;
|
|
mul.rn.f32 %f919, %f891, %f918;
|
|
mov.f32 %f920, 0f35BFBE8E;
|
|
mul.rn.f32 %f921, %f891, %f920;
|
|
add.f32 %f922, %f919, %f915;
|
|
sub.f32 %f923, %f919, %f922;
|
|
add.f32 %f924, %f915, %f923;
|
|
add.f32 %f925, %f917, %f924;
|
|
add.f32 %f926, %f921, %f925;
|
|
add.f32 %f927, %f922, %f926;
|
|
sub.f32 %f928, %f922, %f927;
|
|
add.f32 %f929, %f926, %f928;
|
|
mov.f32 %f930, 0f3ED55555;
|
|
mul.rn.f32 %f931, %f930, %f927;
|
|
neg.f32 %f932, %f931;
|
|
fma.rn.f32 %f933, %f930, %f927, %f932;
|
|
fma.rn.f32 %f934, %f930, %f929, %f933;
|
|
mov.f32 %f935, 0f00000000;
|
|
fma.rn.f32 %f936, %f935, %f927, %f934;
|
|
add.rn.f32 %f937, %f931, %f936;
|
|
neg.f32 %f938, %f937;
|
|
add.rn.f32 %f939, %f931, %f938;
|
|
add.rn.f32 %f940, %f939, %f936;
|
|
mov.b32 %r303, %f937;
|
|
setp.eq.s32 %p136, %r303, 1118925336;
|
|
add.s32 %r304, %r303, -1;
|
|
mov.b32 %f941, %r304;
|
|
add.f32 %f942, %f940, 0f37000000;
|
|
selp.f32 %f146, %f942, %f940, %p136;
|
|
selp.f32 %f943, %f941, %f937, %p136;
|
|
mov.f32 %f944, 0f3FB8AA3B;
|
|
mul.rn.f32 %f945, %f943, %f944;
|
|
cvt.rzi.f32.f32 %f946, %f945;
|
|
abs.f32 %f947, %f946;
|
|
setp.gt.f32 %p137, %f947, 0f42FC0000;
|
|
mov.b32 %r305, %f946;
|
|
and.b32 %r306, %r305, -2147483648;
|
|
or.b32 %r307, %r306, 1123811328;
|
|
mov.b32 %f948, %r307;
|
|
selp.f32 %f949, %f948, %f946, %p137;
|
|
mov.f32 %f950, 0fBF317218;
|
|
fma.rn.f32 %f951, %f949, %f950, %f943;
|
|
mov.f32 %f952, 0f3102E308;
|
|
fma.rn.f32 %f953, %f949, %f952, %f951;
|
|
mul.f32 %f954, %f953, 0f3FB8AA3B;
|
|
add.f32 %f955, %f949, 0f4B40007F;
|
|
mov.b32 %r308, %f955;
|
|
shl.b32 %r309, %r308, 23;
|
|
mov.b32 %f956, %r309;
|
|
ex2.approx.ftz.f32 %f957, %f954;
|
|
mul.f32 %f147, %f957, %f956;
|
|
setp.eq.f32 %p138, %f147, 0f7F800000;
|
|
mov.f32 %f1292, 0f7F800000;
|
|
@%p138 bra $L__BB0_113;
|
|
|
|
fma.rn.f32 %f1292, %f147, %f146, %f147;
|
|
|
|
$L__BB0_113:
|
|
setp.lt.f32 %p139, %f121, 0f00000000;
|
|
and.pred %p7, %p139, %p112;
|
|
setp.eq.f32 %p141, %f121, 0f00000000;
|
|
@%p141 bra $L__BB0_117;
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_117:
|
|
add.f32 %f962, %f121, %f121;
|
|
selp.f32 %f1294, %f962, 0f00000000, %p112;
|
|
bra.uni $L__BB0_118;
|
|
|
|
$L__BB0_114:
|
|
mov.b32 %r310, %f1292;
|
|
xor.b32 %r311, %r310, -2147483648;
|
|
mov.b32 %f958, %r311;
|
|
selp.f32 %f1294, %f958, %f1292, %p7;
|
|
setp.geu.f32 %p142, %f121, 0f00000000;
|
|
@%p142 bra $L__BB0_118;
|
|
|
|
mov.f32 %f959, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f960, %f959;
|
|
setp.eq.f32 %p143, %f960, 0f3ED55555;
|
|
@%p143 bra $L__BB0_118;
|
|
|
|
mov.f32 %f1294, 0f7FFFFFFF;
|
|
|
|
$L__BB0_118:
|
|
add.f32 %f963, %f145, 0f3ED55555;
|
|
mov.b32 %r312, %f963;
|
|
setp.lt.s32 %p145, %r312, 2139095040;
|
|
@%p145 bra $L__BB0_123;
|
|
|
|
setp.gtu.f32 %p146, %f145, 0f7F800000;
|
|
@%p146 bra $L__BB0_122;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_122:
|
|
add.f32 %f1294, %f121, 0f3ED55555;
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_120:
|
|
setp.neu.f32 %p147, %f145, 0f7F800000;
|
|
@%p147 bra $L__BB0_123;
|
|
|
|
selp.f32 %f1294, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_123:
|
|
mov.f32 %f1250, 0f00000000;
|
|
max.f32 %f1249, %f1250, %f712;
|
|
ld.const.u64 %rd153, [params+144];
|
|
cvta.to.global.u64 %rd152, %rd153;
|
|
ld.const.u32 %r371, [params+136];
|
|
mad.lo.s32 %r370, %r371, %r4, %r3;
|
|
cvt.u64.u32 %rd151, %r370;
|
|
fma.rn.f32 %f964, %f1288, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p148, %f1249, 0f3F800000;
|
|
mov.f32 %f965, 0f3F800000;
|
|
selp.f32 %f966, 0f3F7FFFFF, %f964, %p148;
|
|
mul.f32 %f967, %f1249, 0f414EB852;
|
|
setp.lt.f32 %p149, %f1249, 0f3B4D2E1C;
|
|
selp.f32 %f968, %f967, %f966, %p149;
|
|
fma.rn.f32 %f969, %f1291, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p150, %f120, 0f3F800000;
|
|
selp.f32 %f970, 0f3F7FFFFF, %f969, %p150;
|
|
mul.f32 %f971, %f120, 0f414EB852;
|
|
setp.lt.f32 %p151, %f120, 0f3B4D2E1C;
|
|
selp.f32 %f972, %f971, %f970, %p151;
|
|
fma.rn.f32 %f973, %f1294, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p152, %f121, 0f3F800000;
|
|
selp.f32 %f974, 0f3F7FFFFF, %f973, %p152;
|
|
mul.f32 %f975, %f121, 0f414EB852;
|
|
setp.lt.f32 %p153, %f121, 0f3B4D2E1C;
|
|
selp.f32 %f976, %f975, %f974, %p153;
|
|
min.f32 %f977, %f968, %f965;
|
|
mov.f32 %f978, 0f00000000;
|
|
max.f32 %f979, %f978, %f977;
|
|
mul.f32 %f980, %f979, 0f43800000;
|
|
cvt.rzi.u32.f32 %r313, %f980;
|
|
min.u32 %r314, %r313, 255;
|
|
min.f32 %f981, %f972, %f965;
|
|
max.f32 %f982, %f978, %f981;
|
|
mul.f32 %f983, %f982, 0f43800000;
|
|
cvt.rzi.u32.f32 %r315, %f983;
|
|
min.u32 %r316, %r315, 255;
|
|
min.f32 %f984, %f976, %f965;
|
|
max.f32 %f985, %f978, %f984;
|
|
mul.f32 %f986, %f985, 0f43800000;
|
|
cvt.rzi.u32.f32 %r317, %f986;
|
|
min.u32 %r318, %r317, 255;
|
|
shl.b64 %rd81, %rd151, 2;
|
|
add.s64 %rd82, %rd152, %rd81;
|
|
cvt.u16.u32 %rs19, %r318;
|
|
cvt.u16.u32 %rs20, %r316;
|
|
cvt.u16.u32 %rs21, %r314;
|
|
mov.u16 %rs22, 255;
|
|
st.global.v4.u8 [%rd82], {%rs21, %rs20, %rs19, %rs22};
|
|
|
|
$L__BB0_124:
|
|
ld.const.u32 %r372, [params+104];
|
|
and.b32 %r319, %r372, 4;
|
|
setp.eq.s32 %p154, %r319, 0;
|
|
ld.const.u32 %r387, [params+108];
|
|
@%p154 bra $L__BB0_128;
|
|
|
|
setp.eq.s32 %p155, %r387, 0;
|
|
ld.const.u64 %rd83, [params+224];
|
|
cvta.to.global.u64 %rd84, %rd83;
|
|
ld.const.u32 %r320, [params+216];
|
|
mad.lo.s32 %r321, %r320, %r4, %r3;
|
|
mul.wide.u32 %rd85, %r321, 8;
|
|
add.s64 %rd20, %rd84, %rd85;
|
|
@%p155 bra $L__BB0_127;
|
|
|
|
ld.global.v4.u16 {%rs30, %rs31, %rs32, %rs33}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f987, %rs30;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f988, %rs31;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f989, %rs32;}
|
|
|
|
// end inline asm
|
|
add.f32 %f990, %f68, %f987;
|
|
add.f32 %f991, %f69, %f988;
|
|
add.f32 %f992, %f70, %f989;
|
|
mov.f32 %f993, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f992;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f991;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs26, %f990;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f993;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs26, %rs27, %rs28, %rs29};
|
|
bra.uni $L__BB0_128;
|
|
|
|
$L__BB0_127:
|
|
mov.f32 %f997, 0f3F800000;
|
|
mov.u32 %r387, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f997;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f70;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f69;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs34, %f68;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs34, %rs35, %rs36, %rs37};
|
|
|
|
$L__BB0_128:
|
|
mul.f32 %f156, %f65, 0f403D3C19;
|
|
mul.f32 %f157, %f156, 0f3E906EBB;
|
|
mul.f32 %f158, %f66, 0f403D3C19;
|
|
mul.f32 %f159, %f158, 0f3E906EBB;
|
|
mul.f32 %f160, %f67, 0f403D3C19;
|
|
mul.f32 %f161, %f160, 0f3E906EBB;
|
|
ld.const.u64 %rd86, [params+256];
|
|
cvta.to.global.u64 %rd87, %rd86;
|
|
ld.const.u32 %r323, [params+248];
|
|
mad.lo.s32 %r324, %r323, %r4, %r3;
|
|
mul.wide.u32 %rd88, %r324, 8;
|
|
add.s64 %rd21, %rd87, %rd88;
|
|
setp.eq.s32 %p156, %r387, 0;
|
|
@%p156 bra $L__BB0_130;
|
|
|
|
ld.global.v4.u16 {%rs45, %rs46, %rs47, %rs48}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f998, %rs45;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f999, %rs46;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1000, %rs47;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1001, %f157, %f998;
|
|
add.f32 %f1002, %f159, %f999;
|
|
add.f32 %f1003, %f161, %f1000;
|
|
mov.f32 %f1004, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f1003;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f1002;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs41, %f1001;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs44, %f1004;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs41, %rs42, %rs43, %rs44};
|
|
bra.uni $L__BB0_131;
|
|
|
|
$L__BB0_130:
|
|
mov.f32 %f1008, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f1008;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f161;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f159;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs49, %f157;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs49, %rs50, %rs51, %rs52};
|
|
|
|
$L__BB0_131:
|
|
mul.f32 %f1009, %f205, 0fBEFA2A1C;
|
|
mul.f32 %f162, %f156, %f1009;
|
|
mul.f32 %f163, %f158, %f1009;
|
|
mul.f32 %f164, %f160, %f1009;
|
|
ld.const.u64 %rd89, [params+272];
|
|
cvta.to.global.u64 %rd90, %rd89;
|
|
ld.const.u32 %r325, [params+264];
|
|
mad.lo.s32 %r326, %r325, %r4, %r3;
|
|
mul.wide.u32 %rd91, %r326, 8;
|
|
add.s64 %rd22, %rd90, %rd91;
|
|
@%p156 bra $L__BB0_133;
|
|
|
|
ld.global.v4.u16 {%rs60, %rs61, %rs62, %rs63}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1010, %rs60;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1011, %rs61;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1012, %rs62;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1013, %f162, %f1010;
|
|
add.f32 %f1014, %f163, %f1011;
|
|
add.f32 %f1015, %f164, %f1012;
|
|
mov.f32 %f1016, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f1015;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1014;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs56, %f1013;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f1016;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs56, %rs57, %rs58, %rs59};
|
|
bra.uni $L__BB0_134;
|
|
|
|
$L__BB0_133:
|
|
mov.f32 %f1020, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f1020;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f164;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f163;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs64, %f162;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs64, %rs65, %rs66, %rs67};
|
|
|
|
$L__BB0_134:
|
|
mul.f32 %f1021, %f206, 0fBEFA2A1C;
|
|
mul.f32 %f165, %f156, %f1021;
|
|
mul.f32 %f166, %f158, %f1021;
|
|
mul.f32 %f167, %f160, %f1021;
|
|
ld.const.u64 %rd92, [params+288];
|
|
cvta.to.global.u64 %rd93, %rd92;
|
|
ld.const.u32 %r327, [params+280];
|
|
mad.lo.s32 %r328, %r327, %r4, %r3;
|
|
mul.wide.u32 %rd94, %r328, 8;
|
|
add.s64 %rd23, %rd93, %rd94;
|
|
@%p156 bra $L__BB0_136;
|
|
|
|
ld.global.v4.u16 {%rs75, %rs76, %rs77, %rs78}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1022, %rs75;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1023, %rs76;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1024, %rs77;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1025, %f165, %f1022;
|
|
add.f32 %f1026, %f166, %f1023;
|
|
add.f32 %f1027, %f167, %f1024;
|
|
mov.f32 %f1028, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1027;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1026;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs71, %f1025;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs74, %f1028;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs71, %rs72, %rs73, %rs74};
|
|
bra.uni $L__BB0_137;
|
|
|
|
$L__BB0_136:
|
|
mov.f32 %f1032, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f1032;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f167;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs79, %f165;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs79, %rs80, %rs81, %rs82};
|
|
|
|
$L__BB0_137:
|
|
mul.f32 %f1033, %f204, 0fBEFA2A1C;
|
|
mul.f32 %f168, %f156, %f1033;
|
|
mul.f32 %f169, %f158, %f1033;
|
|
mul.f32 %f170, %f160, %f1033;
|
|
ld.const.u64 %rd95, [params+304];
|
|
cvta.to.global.u64 %rd96, %rd95;
|
|
ld.const.u32 %r329, [params+296];
|
|
mad.lo.s32 %r330, %r329, %r4, %r3;
|
|
mul.wide.u32 %rd97, %r330, 8;
|
|
add.s64 %rd24, %rd96, %rd97;
|
|
@%p156 bra $L__BB0_139;
|
|
|
|
ld.global.v4.u16 {%rs90, %rs91, %rs92, %rs93}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1034, %rs90;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1035, %rs91;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1036, %rs92;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1037, %f168, %f1034;
|
|
add.f32 %f1038, %f169, %f1035;
|
|
add.f32 %f1039, %f170, %f1036;
|
|
mov.f32 %f1040, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1039;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1038;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs86, %f1037;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs89, %f1040;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs86, %rs87, %rs88, %rs89};
|
|
bra.uni $L__BB0_140;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f1044, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f1044;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f170;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f169;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs94, %f168;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd24], {%rs94, %rs95, %rs96, %rs97};
|
|
|
|
$L__BB0_140:
|
|
mul.f32 %f1045, %f204, %f205;
|
|
mul.f32 %f1046, %f1045, 0f3F8BD8A1;
|
|
mul.f32 %f171, %f156, %f1046;
|
|
mul.f32 %f172, %f158, %f1046;
|
|
mul.f32 %f173, %f160, %f1046;
|
|
ld.const.u64 %rd98, [params+320];
|
|
cvta.to.global.u64 %rd99, %rd98;
|
|
ld.const.u32 %r331, [params+312];
|
|
mad.lo.s32 %r332, %r331, %r4, %r3;
|
|
mul.wide.u32 %rd100, %r332, 8;
|
|
add.s64 %rd25, %rd99, %rd100;
|
|
@%p156 bra $L__BB0_142;
|
|
|
|
ld.global.v4.u16 {%rs105, %rs106, %rs107, %rs108}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1047, %rs105;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1048, %rs106;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1049, %rs107;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1050, %f171, %f1047;
|
|
add.f32 %f1051, %f172, %f1048;
|
|
add.f32 %f1052, %f173, %f1049;
|
|
mov.f32 %f1053, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs103, %f1052;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs102, %f1051;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs101, %f1050;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs104, %f1053;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs101, %rs102, %rs103, %rs104};
|
|
bra.uni $L__BB0_143;
|
|
|
|
$L__BB0_142:
|
|
mov.f32 %f1057, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs112, %f1057;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs111, %f173;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs110, %f172;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs109, %f171;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd25], {%rs109, %rs110, %rs111, %rs112};
|
|
|
|
$L__BB0_143:
|
|
mul.f32 %f1058, %f205, %f206;
|
|
mul.f32 %f1059, %f1058, 0f3F8BD8A1;
|
|
mul.f32 %f174, %f156, %f1059;
|
|
mul.f32 %f175, %f158, %f1059;
|
|
mul.f32 %f176, %f160, %f1059;
|
|
ld.const.u64 %rd101, [params+336];
|
|
cvta.to.global.u64 %rd102, %rd101;
|
|
ld.const.u32 %r333, [params+328];
|
|
mad.lo.s32 %r334, %r333, %r4, %r3;
|
|
mul.wide.u32 %rd103, %r334, 8;
|
|
add.s64 %rd26, %rd102, %rd103;
|
|
@%p156 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs120, %rs121, %rs122, %rs123}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1060, %rs120;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1061, %rs121;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1062, %rs122;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1063, %f174, %f1060;
|
|
add.f32 %f1064, %f175, %f1061;
|
|
add.f32 %f1065, %f176, %f1062;
|
|
mov.f32 %f1066, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs118, %f1065;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs117, %f1064;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs116, %f1063;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs119, %f1066;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs116, %rs117, %rs118, %rs119};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1070, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f1070;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs126, %f176;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs125, %f175;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs124, %f174;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd26], {%rs124, %rs125, %rs126, %rs127};
|
|
|
|
$L__BB0_146:
|
|
fma.rn.f32 %f1071, %f206, %f206, 0fBEAAAAAB;
|
|
mul.f32 %f1072, %f1071, 0f3F723881;
|
|
mul.f32 %f177, %f156, %f1072;
|
|
mul.f32 %f178, %f158, %f1072;
|
|
mul.f32 %f179, %f160, %f1072;
|
|
ld.const.u64 %rd104, [params+352];
|
|
cvta.to.global.u64 %rd105, %rd104;
|
|
ld.const.u32 %r335, [params+344];
|
|
mad.lo.s32 %r336, %r335, %r4, %r3;
|
|
mul.wide.u32 %rd106, %r336, 8;
|
|
add.s64 %rd27, %rd105, %rd106;
|
|
@%p156 bra $L__BB0_148;
|
|
|
|
ld.global.v4.u16 {%rs135, %rs136, %rs137, %rs138}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1073, %rs135;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1074, %rs136;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1075, %rs137;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1076, %f177, %f1073;
|
|
add.f32 %f1077, %f178, %f1074;
|
|
add.f32 %f1078, %f179, %f1075;
|
|
mov.f32 %f1079, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs133, %f1078;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs132, %f1077;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs131, %f1076;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs134, %f1079;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs131, %rs132, %rs133, %rs134};
|
|
bra.uni $L__BB0_149;
|
|
|
|
$L__BB0_148:
|
|
mov.f32 %f1083, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f1083;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs141, %f179;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs140, %f178;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs139, %f177;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd27], {%rs139, %rs140, %rs141, %rs142};
|
|
|
|
$L__BB0_149:
|
|
mul.f32 %f1084, %f204, %f206;
|
|
mul.f32 %f1085, %f1084, 0f3F8BD8A1;
|
|
mul.f32 %f180, %f156, %f1085;
|
|
mul.f32 %f181, %f158, %f1085;
|
|
mul.f32 %f182, %f160, %f1085;
|
|
ld.const.u64 %rd107, [params+368];
|
|
cvta.to.global.u64 %rd108, %rd107;
|
|
ld.const.u32 %r337, [params+360];
|
|
mad.lo.s32 %r338, %r337, %r4, %r3;
|
|
mul.wide.u32 %rd109, %r338, 8;
|
|
add.s64 %rd28, %rd108, %rd109;
|
|
@%p156 bra $L__BB0_151;
|
|
|
|
ld.global.v4.u16 {%rs150, %rs151, %rs152, %rs153}, [%rd28];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1086, %rs150;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1087, %rs151;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1088, %rs152;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1089, %f180, %f1086;
|
|
add.f32 %f1090, %f181, %f1087;
|
|
add.f32 %f1091, %f182, %f1088;
|
|
mov.f32 %f1092, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs148, %f1091;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs147, %f1090;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs146, %f1089;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs149, %f1092;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd28], {%rs146, %rs147, %rs148, %rs149};
|
|
bra.uni $L__BB0_152;
|
|
|
|
$L__BB0_151:
|
|
mov.f32 %f1096, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f1096;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs156, %f182;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs155, %f181;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs154, %f180;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd28], {%rs154, %rs155, %rs156, %rs157};
|
|
|
|
$L__BB0_152:
|
|
mul.f32 %f1097, %f205, %f205;
|
|
mul.f32 %f1098, %f204, %f204;
|
|
sub.f32 %f1099, %f1098, %f1097;
|
|
mul.f32 %f1100, %f1099, 0f3F0BD8A1;
|
|
mul.f32 %f183, %f156, %f1100;
|
|
mul.f32 %f184, %f158, %f1100;
|
|
mul.f32 %f185, %f160, %f1100;
|
|
ld.const.u64 %rd110, [params+384];
|
|
cvta.to.global.u64 %rd111, %rd110;
|
|
ld.const.u32 %r339, [params+376];
|
|
mad.lo.s32 %r340, %r339, %r4, %r3;
|
|
mul.wide.u32 %rd112, %r340, 8;
|
|
add.s64 %rd29, %rd111, %rd112;
|
|
@%p156 bra $L__BB0_154;
|
|
|
|
ld.global.v4.u16 {%rs165, %rs166, %rs167, %rs168}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1101, %rs165;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1102, %rs166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1103, %rs167;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1104, %f183, %f1101;
|
|
add.f32 %f1105, %f184, %f1102;
|
|
add.f32 %f1106, %f185, %f1103;
|
|
mov.f32 %f1107, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs163, %f1106;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs162, %f1105;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs161, %f1104;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs164, %f1107;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd29], {%rs161, %rs162, %rs163, %rs164};
|
|
bra.uni $L__BB0_190;
|
|
|
|
$L__BB0_154:
|
|
mov.f32 %f1111, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs172, %f1111;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs171, %f185;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs170, %f184;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs169, %f183;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd29], {%rs169, %rs170, %rs171, %rs172};
|
|
|
|
$L__BB0_190:
|
|
ret;
|
|
|
|
}
|
|
|