3307 lines
90 KiB
Plaintext
3307 lines
90 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.visible .entry __raygen__oxMain()
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{
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.reg .pred %p<193>;
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.reg .b16 %rs<330>;
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.reg .f32 %f<1880>;
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.reg .b32 %r<450>;
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.reg .b64 %rd<118>;
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// begin inline asm
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call (%r26), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r27), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u64 %rd31, [params+400];
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cvta.to.global.u64 %rd32, %rd31;
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ld.const.u32 %r32, [params+392];
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mad.lo.s32 %r33, %r32, %r27, %r26;
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mul.wide.u32 %rd33, %r33, 4;
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add.s64 %rd1, %rd32, %rd33;
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ld.global.v2.u8 {%rs9, %rs328}, [%rd1];
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or.b16 %rs11, %rs9, %rs328;
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and.b16 %rs12, %rs11, 255;
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setp.eq.s16 %p10, %rs12, 0;
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@%p10 bra $L__BB0_2;
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ld.global.u8 %rs327, [%rd1+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs327, [%rd1+2];
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setp.eq.s16 %p11, %rs327, 0;
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mov.f32 %f1716, 0f00000000;
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mov.u16 %rs328, 0;
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mov.f32 %f1717, %f1716;
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mov.f32 %f1718, %f1716;
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@%p11 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f389, %rs9;
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div.rn.f32 %f390, %f389, 0f437F0000;
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fma.rn.f32 %f391, %f390, 0f40000000, 0fBF800000;
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and.b16 %rs15, %rs328, 255;
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cvt.rn.f32.u16 %f392, %rs15;
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div.rn.f32 %f393, %f392, 0f437F0000;
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fma.rn.f32 %f394, %f393, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f395, %rs327;
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div.rn.f32 %f396, %f395, 0f437F0000;
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fma.rn.f32 %f397, %f396, 0f40000000, 0fBF800000;
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mul.f32 %f398, %f394, %f394;
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fma.rn.f32 %f399, %f391, %f391, %f398;
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fma.rn.f32 %f400, %f397, %f397, %f399;
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sqrt.rn.f32 %f401, %f400;
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rcp.rn.f32 %f402, %f401;
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mul.f32 %f1718, %f402, %f397;
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mul.f32 %f1717, %f402, %f394;
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mul.f32 %f1716, %f391, %f402;
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$L__BB0_4:
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ld.const.v2.u32 {%r34, %r35}, [params];
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add.s32 %r3, %r34, %r26;
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add.s32 %r4, %r35, %r27;
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setp.eq.f32 %p12, %f1716, 0f00000000;
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setp.eq.f32 %p13, %f1717, 0f00000000;
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and.pred %p14, %p12, %p13;
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setp.eq.f32 %p15, %f1718, 0f00000000;
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and.pred %p16, %p15, %p14;
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@%p16 bra $L__BB0_164;
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bra.uni $L__BB0_5;
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$L__BB0_164:
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ld.const.u32 %r23, [params+104];
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and.b32 %r414, %r23, 1;
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setp.eq.b32 %p176, %r414, 1;
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mov.pred %p177, 0;
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xor.pred %p178, %p176, %p177;
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not.pred %p179, %p178;
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@%p179 bra $L__BB0_166;
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ld.const.u64 %rd79, [params+144];
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cvta.to.global.u64 %rd80, %rd79;
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ld.const.u32 %r415, [params+136];
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mad.lo.s32 %r416, %r415, %r4, %r3;
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mul.wide.u32 %rd81, %r416, 4;
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add.s64 %rd82, %rd80, %rd81;
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mov.u16 %rs174, 0;
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st.global.v4.u8 [%rd82], {%rs174, %rs174, %rs174, %rs174};
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$L__BB0_166:
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and.b32 %r417, %r23, 8;
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setp.eq.s32 %p180, %r417, 0;
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@%p180 bra $L__BB0_168;
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ld.const.u64 %rd83, [params+192];
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cvta.to.global.u64 %rd84, %rd83;
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ld.const.u32 %r418, [params+184];
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mad.lo.s32 %r419, %r418, %r4, %r3;
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mov.f32 %f1622, 0f00000000;
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cvt.rzi.u32.f32 %r420, %f1622;
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mul.wide.u32 %rd85, %r419, 2;
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add.s64 %rd86, %rd84, %rd85;
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mov.u16 %rs175, 0;
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cvt.u16.u32 %rs176, %r420;
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st.global.v2.u8 [%rd86], {%rs176, %rs175};
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$L__BB0_168:
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and.b32 %r421, %r23, 4;
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setp.eq.s32 %p181, %r421, 0;
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ld.const.u32 %r449, [params+108];
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@%p181 bra $L__BB0_172;
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setp.eq.s32 %p182, %r449, 0;
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ld.const.u64 %rd87, [params+224];
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cvta.to.global.u64 %rd88, %rd87;
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ld.const.u32 %r422, [params+216];
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mad.lo.s32 %r423, %r422, %r4, %r3;
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mul.wide.u32 %rd89, %r423, 8;
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add.s64 %rd21, %rd88, %rd89;
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@%p182 bra $L__BB0_171;
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ld.global.v4.u16 {%rs183, %rs184, %rs185, %rs186}, [%rd21];
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// begin inline asm
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{ cvt.f32.f16 %f1623, %rs183;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1624, %rs184;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1625, %rs185;}
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// end inline asm
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add.f32 %f1626, %f1623, 0f00000000;
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add.f32 %f1627, %f1624, 0f00000000;
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add.f32 %f1628, %f1625, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs182, %f1628;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs181, %f1627;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs180, %f1626;}
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// end inline asm
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mov.u16 %rs187, 0;
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st.global.v4.u16 [%rd21], {%rs180, %rs181, %rs182, %rs187};
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bra.uni $L__BB0_172;
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$L__BB0_5:
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ld.const.u64 %rd34, [params+432];
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cvta.to.global.u64 %rd35, %rd34;
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ld.const.u32 %r38, [params+424];
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mad.lo.s32 %r39, %r38, %r27, %r26;
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mul.wide.u32 %rd36, %r39, 12;
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add.s64 %rd37, %rd35, %rd36;
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ld.global.f32 %f10, [%rd37];
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mul.f32 %f403, %f10, 0f3456BF95;
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ld.global.f32 %f11, [%rd37+4];
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mul.f32 %f404, %f11, 0f3456BF95;
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ld.global.f32 %f12, [%rd37+8];
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mul.f32 %f405, %f12, 0f3456BF95;
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abs.f32 %f406, %f1716;
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div.rn.f32 %f407, %f403, %f406;
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abs.f32 %f408, %f1717;
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div.rn.f32 %f409, %f404, %f408;
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abs.f32 %f410, %f1718;
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div.rn.f32 %f411, %f405, %f410;
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abs.f32 %f412, %f407;
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abs.f32 %f413, %f409;
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abs.f32 %f414, %f411;
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mov.f32 %f415, 0f38D1B717;
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max.f32 %f416, %f412, %f415;
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max.f32 %f417, %f413, %f415;
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max.f32 %f418, %f414, %f415;
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fma.rn.f32 %f13, %f1716, %f416, %f10;
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fma.rn.f32 %f14, %f1717, %f417, %f11;
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fma.rn.f32 %f15, %f1718, %f418, %f12;
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cvt.rn.f32.u32 %f16, %r26;
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cvt.rn.f32.u32 %f17, %r27;
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ld.const.u32 %r5, [params+600];
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setp.eq.s32 %p17, %r5, 0;
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@%p17 bra $L__BB0_44;
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ld.const.u64 %rd38, [params+608];
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cvta.to.global.u64 %rd2, %rd38;
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mov.f32 %f450, 0f40000000;
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cvt.rzi.f32.f32 %f451, %f450;
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add.f32 %f452, %f451, %f451;
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mov.f32 %f453, 0f40800000;
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sub.f32 %f454, %f453, %f452;
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abs.f32 %f18, %f454;
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ld.const.u32 %r6, [params+544];
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ld.const.u32 %r447, [params+104];
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mul.f32 %f19, %f13, 0f3456BF95;
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mul.f32 %f20, %f14, 0f3456BF95;
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mul.f32 %f21, %f15, 0f3456BF95;
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mov.f32 %f449, 0f00000000;
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mov.u32 %r443, 0;
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ld.const.u64 %rd3, [params+96];
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abs.f32 %f674, %f19;
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abs.f32 %f675, %f20;
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max.f32 %f676, %f674, %f675;
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abs.f32 %f677, %f21;
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max.f32 %f678, %f676, %f677;
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mov.f32 %f1827, %f449;
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mov.f32 %f1826, %f449;
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mov.f32 %f1825, %f449;
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mov.f32 %f1824, %f449;
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mov.f32 %f1823, %f449;
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mov.f32 %f1822, %f449;
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mov.f32 %f1821, %f449;
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mov.f32 %f1820, %f449;
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mov.f32 %f1819, %f449;
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mov.f32 %f1818, %f449;
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mov.f32 %f1817, %f449;
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mov.f32 %f1816, %f449;
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mov.f32 %f1815, %f449;
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mov.f32 %f1814, %f449;
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mov.f32 %f1813, %f449;
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mov.f32 %f1812, %f449;
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mov.f32 %f1811, %f449;
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mov.f32 %f1810, %f449;
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mov.f32 %f1809, %f449;
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mov.f32 %f1808, %f449;
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mov.f32 %f1807, %f449;
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mov.f32 %f1806, %f449;
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mov.f32 %f1805, %f449;
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mov.f32 %f1804, %f449;
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mov.f32 %f1803, %f449;
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mov.f32 %f1802, %f449;
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mov.f32 %f1801, %f449;
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mov.f32 %f1800, %f449;
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mov.f32 %f1799, %f449;
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mov.f32 %f1798, %f449;
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mov.f32 %f1797, %f449;
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$L__BB0_7:
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mul.wide.u32 %rd39, %r443, 112;
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add.s64 %rd5, %rd2, %rd39;
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ld.global.v4.f32 {%f456, %f457, %f458, %f459}, [%rd5];
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ld.global.v4.f32 {%f463, %f464, %f465, %f466}, [%rd5+16];
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ld.global.v4.f32 {%f469, %f1758, %f1759, %f472}, [%rd5+32];
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ld.global.v4.f32 {%f473, %f474, %f475, %f1756}, [%rd5+48];
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ld.global.v4.f32 {%f477, %f478, %f479, %f480}, [%rd5+64];
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ld.global.v4.u32 {%r41, %r42, %r43, %r44}, [%rd5+80];
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mov.b32 %f66, %r41;
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mov.b32 %f67, %r42;
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mov.b32 %f68, %r43;
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ld.global.u64 %rd6, [%rd5+96];
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sub.f32 %f69, %f457, %f10;
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sub.f32 %f70, %f458, %f11;
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sub.f32 %f71, %f459, %f12;
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mul.f32 %f481, %f70, %f70;
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fma.rn.f32 %f482, %f69, %f69, %f481;
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fma.rn.f32 %f483, %f71, %f71, %f482;
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sqrt.rn.f32 %f484, %f483;
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rcp.rn.f32 %f485, %f484;
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mul.f32 %f72, %f69, %f485;
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mul.f32 %f73, %f70, %f485;
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mul.f32 %f74, %f71, %f485;
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mul.f32 %f75, %f484, %f464;
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mul.f32 %f76, %f484, %f466;
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abs.f32 %f77, %f76;
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setp.lt.f32 %p18, %f77, 0f00800000;
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mul.f32 %f486, %f77, 0f4B800000;
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selp.f32 %f487, %f486, %f77, %p18;
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selp.f32 %f488, 0fC3170000, 0fC2FE0000, %p18;
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mov.b32 %r48, %f487;
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and.b32 %r49, %r48, 8388607;
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or.b32 %r50, %r49, 1065353216;
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mov.b32 %f489, %r50;
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shr.u32 %r51, %r48, 23;
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cvt.rn.f32.u32 %f490, %r51;
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add.f32 %f491, %f488, %f490;
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setp.gt.f32 %p19, %f489, 0f3FB504F3;
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mul.f32 %f492, %f489, 0f3F000000;
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add.f32 %f493, %f491, 0f3F800000;
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selp.f32 %f494, %f493, %f491, %p19;
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selp.f32 %f495, %f492, %f489, %p19;
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add.f32 %f496, %f495, 0fBF800000;
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add.f32 %f497, %f495, 0f3F800000;
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rcp.approx.ftz.f32 %f498, %f497;
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add.f32 %f499, %f496, %f496;
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mul.f32 %f500, %f499, %f498;
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mul.f32 %f501, %f500, %f500;
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mov.f32 %f502, 0f3C4CAF63;
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mov.f32 %f503, 0f3B18F0FE;
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fma.rn.f32 %f504, %f503, %f501, %f502;
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mov.f32 %f505, 0f3DAAAABD;
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fma.rn.f32 %f506, %f504, %f501, %f505;
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mul.rn.f32 %f507, %f506, %f501;
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mul.rn.f32 %f508, %f507, %f500;
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sub.f32 %f509, %f496, %f500;
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add.f32 %f510, %f509, %f509;
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|
neg.f32 %f511, %f500;
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fma.rn.f32 %f512, %f511, %f496, %f510;
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|
mul.rn.f32 %f513, %f498, %f512;
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add.f32 %f514, %f508, %f500;
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sub.f32 %f515, %f500, %f514;
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add.f32 %f516, %f508, %f515;
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add.f32 %f517, %f513, %f516;
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add.f32 %f518, %f514, %f517;
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sub.f32 %f519, %f514, %f518;
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add.f32 %f520, %f517, %f519;
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mov.f32 %f521, 0f3F317200;
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mul.rn.f32 %f522, %f494, %f521;
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mov.f32 %f523, 0f35BFBE8E;
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mul.rn.f32 %f524, %f494, %f523;
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|
add.f32 %f525, %f522, %f518;
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|
sub.f32 %f526, %f522, %f525;
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|
add.f32 %f527, %f518, %f526;
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|
add.f32 %f528, %f520, %f527;
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add.f32 %f529, %f524, %f528;
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add.f32 %f530, %f525, %f529;
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|
sub.f32 %f531, %f525, %f530;
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|
add.f32 %f532, %f529, %f531;
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|
mul.rn.f32 %f534, %f453, %f530;
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|
neg.f32 %f535, %f534;
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fma.rn.f32 %f536, %f453, %f530, %f535;
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fma.rn.f32 %f537, %f453, %f532, %f536;
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|
fma.rn.f32 %f539, %f449, %f530, %f537;
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add.rn.f32 %f540, %f534, %f539;
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neg.f32 %f541, %f540;
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add.rn.f32 %f542, %f534, %f541;
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add.rn.f32 %f543, %f542, %f539;
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|
mov.b32 %r52, %f540;
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setp.eq.s32 %p20, %r52, 1118925336;
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add.s32 %r53, %r52, -1;
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|
mov.b32 %f544, %r53;
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|
add.f32 %f545, %f543, 0f37000000;
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selp.f32 %f78, %f545, %f543, %p20;
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|
selp.f32 %f546, %f544, %f540, %p20;
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|
mov.f32 %f547, 0f3FB8AA3B;
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|
mul.rn.f32 %f548, %f546, %f547;
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|
cvt.rzi.f32.f32 %f549, %f548;
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|
abs.f32 %f550, %f549;
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|
setp.gt.f32 %p21, %f550, 0f42FC0000;
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|
mov.b32 %r54, %f549;
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|
and.b32 %r55, %r54, -2147483648;
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|
or.b32 %r56, %r55, 1123811328;
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|
mov.b32 %f551, %r56;
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|
selp.f32 %f552, %f551, %f549, %p21;
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|
mov.f32 %f553, 0fBF317218;
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|
fma.rn.f32 %f554, %f552, %f553, %f546;
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|
mov.f32 %f555, 0f3102E308;
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|
fma.rn.f32 %f556, %f552, %f555, %f554;
|
|
mul.f32 %f557, %f556, 0f3FB8AA3B;
|
|
add.f32 %f558, %f552, 0f4B40007F;
|
|
mov.b32 %r57, %f558;
|
|
shl.b32 %r58, %r57, 23;
|
|
mov.b32 %f559, %r58;
|
|
ex2.approx.ftz.f32 %f560, %f557;
|
|
mul.f32 %f79, %f560, %f559;
|
|
setp.eq.f32 %p22, %f79, 0f7F800000;
|
|
mov.f32 %f1750, 0f7F800000;
|
|
@%p22 bra $L__BB0_9;
|
|
|
|
fma.rn.f32 %f1750, %f79, %f78, %f79;
|
|
|
|
$L__BB0_9:
|
|
setp.lt.f32 %p23, %f76, 0f00000000;
|
|
setp.eq.f32 %p24, %f18, 0f3F800000;
|
|
and.pred %p1, %p23, %p24;
|
|
setp.eq.f32 %p25, %f76, 0f00000000;
|
|
@%p25 bra $L__BB0_13;
|
|
bra.uni $L__BB0_10;
|
|
|
|
$L__BB0_13:
|
|
add.f32 %f565, %f76, %f76;
|
|
selp.f32 %f1752, %f565, 0f00000000, %p24;
|
|
bra.uni $L__BB0_14;
|
|
|
|
$L__BB0_10:
|
|
mov.b32 %r59, %f1750;
|
|
xor.b32 %r60, %r59, -2147483648;
|
|
mov.b32 %f561, %r60;
|
|
selp.f32 %f1752, %f561, %f1750, %p1;
|
|
setp.geu.f32 %p26, %f76, 0f00000000;
|
|
@%p26 bra $L__BB0_14;
|
|
|
|
mov.f32 %f562, 0f40800000;
|
|
cvt.rzi.f32.f32 %f563, %f562;
|
|
setp.eq.f32 %p27, %f563, 0f40800000;
|
|
@%p27 bra $L__BB0_14;
|
|
|
|
mov.f32 %f1752, 0f7FFFFFFF;
|
|
|
|
$L__BB0_14:
|
|
abs.f32 %f1713, %f76;
|
|
add.f32 %f566, %f1713, 0f40800000;
|
|
mov.b32 %r61, %f566;
|
|
setp.lt.s32 %p29, %r61, 2139095040;
|
|
@%p29 bra $L__BB0_19;
|
|
|
|
abs.f32 %f1714, %f76;
|
|
setp.gtu.f32 %p30, %f1714, 0f7F800000;
|
|
@%p30 bra $L__BB0_18;
|
|
bra.uni $L__BB0_16;
|
|
|
|
$L__BB0_18:
|
|
add.f32 %f1752, %f76, 0f40800000;
|
|
bra.uni $L__BB0_19;
|
|
|
|
$L__BB0_16:
|
|
abs.f32 %f1715, %f76;
|
|
setp.neu.f32 %p31, %f1715, 0f7F800000;
|
|
@%p31 bra $L__BB0_19;
|
|
|
|
selp.f32 %f1752, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_19:
|
|
mov.f32 %f567, 0f3F800000;
|
|
sub.f32 %f568, %f567, %f1752;
|
|
setp.eq.f32 %p32, %f76, 0f3F800000;
|
|
selp.f32 %f569, 0f00000000, %f568, %p32;
|
|
cvt.sat.f32.f32 %f570, %f569;
|
|
fma.rn.f32 %f571, %f75, %f75, %f465;
|
|
div.rn.f32 %f88, %f570, %f571;
|
|
mul.f32 %f572, %f1717, %f73;
|
|
fma.rn.f32 %f573, %f1716, %f72, %f572;
|
|
fma.rn.f32 %f89, %f1718, %f74, %f573;
|
|
setp.eq.f32 %p33, %f456, 0f3F800000;
|
|
@%p33 bra $L__BB0_25;
|
|
bra.uni $L__BB0_20;
|
|
|
|
$L__BB0_25:
|
|
setp.eq.s64 %p37, %rd6, 0;
|
|
mov.f32 %f1757, %f469;
|
|
mov.f32 %f1760, %f88;
|
|
@%p37 bra $L__BB0_29;
|
|
|
|
setp.geu.f32 %p38, %f1756, 0f00000000;
|
|
mov.f32 %f1753, %f72;
|
|
mov.f32 %f1754, %f73;
|
|
mov.f32 %f1755, %f74;
|
|
@%p38 bra $L__BB0_28;
|
|
|
|
mul.f32 %f596, %f67, %f70;
|
|
fma.rn.f32 %f597, %f66, %f69, %f596;
|
|
fma.rn.f32 %f598, %f68, %f71, %f597;
|
|
rcp.rn.f32 %f599, %f598;
|
|
mul.f32 %f1753, %f69, %f599;
|
|
mul.f32 %f1754, %f70, %f599;
|
|
mul.f32 %f1755, %f71, %f599;
|
|
neg.f32 %f1756, %f1756;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f600, %f68, %f74;
|
|
mul.f32 %f601, %f67, %f73;
|
|
neg.f32 %f602, %f601;
|
|
mul.f32 %f603, %f66, %f72;
|
|
sub.f32 %f604, %f602, %f603;
|
|
sub.f32 %f605, %f604, %f600;
|
|
setp.gt.f32 %p39, %f605, 0f00000000;
|
|
selp.f32 %f606, 0f3F800000, 0f00000000, %p39;
|
|
mov.f32 %f607, 0f3F800000;
|
|
mul.f32 %f608, %f474, %f1754;
|
|
fma.rn.f32 %f609, %f473, %f1753, %f608;
|
|
mul.f32 %f610, %f478, %f1754;
|
|
fma.rn.f32 %f611, %f477, %f1753, %f610;
|
|
fma.rn.f32 %f612, %f475, %f1755, %f609;
|
|
fma.rn.f32 %f613, %f479, %f1755, %f611;
|
|
fma.rn.f32 %f614, %f1756, %f612, 0f3F000000;
|
|
sub.f32 %f615, %f607, %f614;
|
|
fma.rn.f32 %f616, %f1756, %f613, 0f3F000000;
|
|
tex.2d.v4.f32.f32 {%f617, %f618, %f619, %f620}, [%rd6, {%f615, %f616}];
|
|
mul.f32 %f621, %f606, %f617;
|
|
mul.f32 %f622, %f606, %f618;
|
|
mul.f32 %f623, %f606, %f619;
|
|
mul.f32 %f1757, %f469, %f621;
|
|
mul.f32 %f1758, %f1758, %f622;
|
|
mul.f32 %f1759, %f1759, %f623;
|
|
mov.f32 %f1760, %f88;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_20:
|
|
setp.eq.f32 %p34, %f456, 0f40000000;
|
|
@%p34 bra $L__BB0_23;
|
|
bra.uni $L__BB0_21;
|
|
|
|
$L__BB0_23:
|
|
setp.eq.s64 %p36, %rd6, 0;
|
|
mov.f32 %f1757, %f469;
|
|
mov.f32 %f1760, %f88;
|
|
@%p36 bra $L__BB0_29;
|
|
|
|
mul.f32 %f583, %f474, %f73;
|
|
fma.rn.f32 %f584, %f473, %f72, %f583;
|
|
mul.f32 %f585, %f478, %f73;
|
|
fma.rn.f32 %f586, %f477, %f72, %f585;
|
|
mul.f32 %f587, %f67, %f73;
|
|
fma.rn.f32 %f588, %f66, %f72, %f587;
|
|
fma.rn.f32 %f589, %f475, %f74, %f584;
|
|
fma.rn.f32 %f590, %f479, %f74, %f586;
|
|
fma.rn.f32 %f591, %f68, %f74, %f588;
|
|
tex.cube.v4.f32.f32 {%f592, %f593, %f594, %f595}, [%rd6, {%f589, %f590, %f591, %f591}];
|
|
mul.f32 %f1757, %f469, %f592;
|
|
mul.f32 %f1758, %f1758, %f593;
|
|
mul.f32 %f1759, %f1759, %f594;
|
|
mov.f32 %f1760, %f88;
|
|
bra.uni $L__BB0_29;
|
|
|
|
$L__BB0_21:
|
|
setp.neu.f32 %p35, %f456, 0f40800000;
|
|
mov.f32 %f1757, %f469;
|
|
mov.f32 %f1760, %f88;
|
|
@%p35 bra $L__BB0_29;
|
|
|
|
mul.f32 %f574, %f66, %f72;
|
|
mul.f32 %f575, %f67, %f73;
|
|
neg.f32 %f576, %f575;
|
|
sub.f32 %f577, %f576, %f574;
|
|
mul.f32 %f578, %f68, %f74;
|
|
sub.f32 %f579, %f577, %f578;
|
|
fma.rn.f32 %f580, %f472, %f579, %f1756;
|
|
cvt.sat.f32.f32 %f581, %f580;
|
|
mul.f32 %f582, %f581, %f581;
|
|
mul.f32 %f1760, %f88, %f582;
|
|
mov.f32 %f1757, %f469;
|
|
|
|
$L__BB0_29:
|
|
max.f32 %f654, %f1757, %f1758;
|
|
max.f32 %f655, %f654, %f1759;
|
|
mul.f32 %f656, %f1760, %f655;
|
|
setp.lt.f32 %p41, %f656, 0f3727C5AC;
|
|
mov.pred %p192, -1;
|
|
mov.f32 %f1761, 0f00000000;
|
|
mov.f32 %f1762, %f1761;
|
|
mov.f32 %f1763, %f1761;
|
|
mov.f32 %f1764, %f1761;
|
|
mov.f32 %f1765, %f1761;
|
|
mov.f32 %f1766, %f1761;
|
|
mov.f32 %f1767, %f1761;
|
|
mov.f32 %f1768, %f1761;
|
|
mov.f32 %f1769, %f1761;
|
|
mov.f32 %f1770, %f1761;
|
|
mov.f32 %f1771, %f1761;
|
|
mov.f32 %f1772, %f1761;
|
|
mov.f32 %f1773, %f1761;
|
|
mov.f32 %f1774, %f1761;
|
|
mov.f32 %f1775, %f1761;
|
|
mov.f32 %f1776, %f1761;
|
|
mov.f32 %f1777, %f1761;
|
|
mov.f32 %f1778, %f1761;
|
|
mov.f32 %f1779, %f1761;
|
|
mov.f32 %f1780, %f1761;
|
|
mov.f32 %f1781, %f1761;
|
|
mov.f32 %f1782, %f1761;
|
|
mov.f32 %f1783, %f1761;
|
|
mov.f32 %f1784, %f1761;
|
|
mov.f32 %f1785, %f1761;
|
|
mov.f32 %f1786, %f1761;
|
|
mov.f32 %f1787, %f1761;
|
|
mov.f32 %f1788, %f1761;
|
|
mov.f32 %f1789, %f1761;
|
|
mov.f32 %f1790, %f1761;
|
|
@%p41 bra $L__BB0_31;
|
|
|
|
setp.eq.s32 %p43, %r6, 0;
|
|
selp.f32 %f657, %f89, 0f3F800000, %p43;
|
|
cvt.sat.f32.f32 %f658, %f657;
|
|
mul.f32 %f659, %f1760, %f658;
|
|
mul.f32 %f1790, %f1757, %f659;
|
|
mul.f32 %f1789, %f1758, %f659;
|
|
mul.f32 %f1788, %f1759, %f659;
|
|
mul.f32 %f660, %f1757, %f1760;
|
|
add.f32 %f1787, %f660, 0f00000000;
|
|
mul.f32 %f661, %f1758, %f1760;
|
|
add.f32 %f1786, %f661, 0f00000000;
|
|
mul.f32 %f662, %f1759, %f1760;
|
|
add.f32 %f1785, %f662, 0f00000000;
|
|
fma.rn.f32 %f1784, %f73, %f660, 0f00000000;
|
|
fma.rn.f32 %f1783, %f73, %f661, 0f00000000;
|
|
fma.rn.f32 %f1782, %f73, %f662, 0f00000000;
|
|
fma.rn.f32 %f1781, %f74, %f660, 0f00000000;
|
|
fma.rn.f32 %f1780, %f74, %f661, 0f00000000;
|
|
fma.rn.f32 %f1779, %f74, %f662, 0f00000000;
|
|
fma.rn.f32 %f1778, %f72, %f660, 0f00000000;
|
|
fma.rn.f32 %f1777, %f72, %f661, 0f00000000;
|
|
fma.rn.f32 %f1776, %f72, %f662, 0f00000000;
|
|
mul.f32 %f663, %f72, %f73;
|
|
fma.rn.f32 %f1775, %f663, %f660, 0f00000000;
|
|
fma.rn.f32 %f1774, %f663, %f661, 0f00000000;
|
|
fma.rn.f32 %f1773, %f663, %f662, 0f00000000;
|
|
mul.f32 %f664, %f73, %f74;
|
|
fma.rn.f32 %f1772, %f664, %f660, 0f00000000;
|
|
fma.rn.f32 %f1771, %f664, %f661, 0f00000000;
|
|
fma.rn.f32 %f1770, %f664, %f662, 0f00000000;
|
|
fma.rn.f32 %f665, %f74, %f74, 0fBEAAAAAB;
|
|
fma.rn.f32 %f1769, %f665, %f660, 0f00000000;
|
|
fma.rn.f32 %f1768, %f665, %f661, 0f00000000;
|
|
fma.rn.f32 %f1767, %f665, %f662, 0f00000000;
|
|
mul.f32 %f666, %f72, %f74;
|
|
fma.rn.f32 %f1766, %f666, %f660, 0f00000000;
|
|
fma.rn.f32 %f1765, %f666, %f661, 0f00000000;
|
|
fma.rn.f32 %f1764, %f666, %f662, 0f00000000;
|
|
mul.f32 %f667, %f73, %f73;
|
|
mul.f32 %f668, %f72, %f72;
|
|
sub.f32 %f669, %f668, %f667;
|
|
fma.rn.f32 %f1763, %f669, %f660, 0f00000000;
|
|
fma.rn.f32 %f1762, %f669, %f661, 0f00000000;
|
|
fma.rn.f32 %f1761, %f669, %f662, 0f00000000;
|
|
mov.pred %p192, 0;
|
|
|
|
$L__BB0_31:
|
|
@%p192 bra $L__BB0_43;
|
|
|
|
setp.eq.s32 %p44, %r44, 0;
|
|
mov.u16 %rs329, 0;
|
|
mov.f32 %f1796, 0f3F800000;
|
|
@%p44 bra $L__BB0_40;
|
|
|
|
abs.s32 %r10, %r44;
|
|
setp.lt.s32 %p45, %r10, 1;
|
|
mov.f32 %f1792, 0f00000000;
|
|
@%p45 bra $L__BB0_39;
|
|
|
|
mov.f32 %f679, 0f38D1B717;
|
|
max.f32 %f680, %f678, %f679;
|
|
and.b32 %r63, %r447, 32;
|
|
setp.eq.s32 %p46, %r63, 0;
|
|
mov.u32 %r446, 0;
|
|
selp.f32 %f681, 0f3F800000, 0f41200000, %p46;
|
|
mul.f32 %f169, %f681, %f680;
|
|
and.b32 %r11, %r10, 1;
|
|
setp.eq.s32 %p47, %r10, 1;
|
|
mov.f32 %f1792, 0f00000000;
|
|
@%p47 bra $L__BB0_37;
|
|
|
|
sub.s32 %r445, %r10, %r11;
|
|
|
|
$L__BB0_36:
|
|
cvt.rn.f32.s32 %f701, %r446;
|
|
add.f32 %f702, %f16, %f701;
|
|
sub.f32 %f703, %f17, %f701;
|
|
mul.f32 %f704, %f702, 0f3DD32618;
|
|
cvt.rmi.f32.f32 %f705, %f704;
|
|
sub.f32 %f706, %f704, %f705;
|
|
mul.f32 %f707, %f703, 0f3DD2F1AA;
|
|
cvt.rmi.f32.f32 %f708, %f707;
|
|
sub.f32 %f709, %f707, %f708;
|
|
mul.f32 %f710, %f701, 0f3DC74539;
|
|
cvt.rmi.f32.f32 %f711, %f710;
|
|
sub.f32 %f712, %f710, %f711;
|
|
add.f32 %f713, %f709, 0f420551EC;
|
|
add.f32 %f714, %f706, 0f420551EC;
|
|
add.f32 %f715, %f712, 0f420551EC;
|
|
mul.f32 %f716, %f706, %f713;
|
|
fma.rn.f32 %f717, %f709, %f714, %f716;
|
|
fma.rn.f32 %f718, %f712, %f715, %f717;
|
|
add.f32 %f719, %f706, %f718;
|
|
add.f32 %f720, %f709, %f718;
|
|
add.f32 %f721, %f712, %f718;
|
|
add.f32 %f722, %f719, %f720;
|
|
mul.f32 %f723, %f721, %f722;
|
|
cvt.rmi.f32.f32 %f724, %f723;
|
|
sub.f32 %f725, %f723, %f724;
|
|
add.f32 %f726, %f719, %f719;
|
|
mul.f32 %f727, %f720, %f726;
|
|
cvt.rmi.f32.f32 %f728, %f727;
|
|
sub.f32 %f729, %f727, %f728;
|
|
mul.f32 %f730, %f719, %f722;
|
|
cvt.rmi.f32.f32 %f731, %f730;
|
|
sub.f32 %f732, %f730, %f731;
|
|
fma.rn.f32 %f733, %f725, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f734, %f729, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f735, %f732, 0f40000000, 0fBF800000;
|
|
ld.global.f32 %f736, [%rd5+16];
|
|
ld.global.f32 %f737, [%rd5+4];
|
|
fma.rn.f32 %f738, %f736, %f733, %f737;
|
|
ld.global.f32 %f739, [%rd5+8];
|
|
fma.rn.f32 %f740, %f736, %f734, %f739;
|
|
ld.global.f32 %f741, [%rd5+12];
|
|
fma.rn.f32 %f742, %f736, %f735, %f741;
|
|
sub.f32 %f743, %f738, %f10;
|
|
sub.f32 %f744, %f740, %f11;
|
|
sub.f32 %f745, %f742, %f12;
|
|
mul.f32 %f746, %f744, %f744;
|
|
fma.rn.f32 %f747, %f743, %f743, %f746;
|
|
fma.rn.f32 %f748, %f745, %f745, %f747;
|
|
sqrt.rn.f32 %f690, %f748;
|
|
rcp.rn.f32 %f749, %f690;
|
|
mul.f32 %f686, %f749, %f743;
|
|
mul.f32 %f687, %f749, %f744;
|
|
mul.f32 %f688, %f749, %f745;
|
|
mov.f32 %f700, 0f00000000;
|
|
mov.u32 %r172, 2;
|
|
mov.u32 %r174, 1;
|
|
mov.u32 %r175, 1065353216;
|
|
mov.u32 %r206, 0;
|
|
// begin inline asm
|
|
call(%r65,%r66,%r67,%r68,%r69,%r70,%r71,%r72,%r73,%r74,%r75,%r76,%r77,%r78,%r79,%r80,%r81,%r82,%r83,%r84,%r85,%r86,%r87,%r88,%r89,%r90,%r91,%r92,%r93,%r94,%r95,%r96),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f686,%f687,%f688,%f169,%f690,%f700,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f750, %r65;
|
|
add.f32 %f751, %f1792, %f750;
|
|
add.s32 %r207, %r446, 1;
|
|
cvt.rn.f32.s32 %f752, %r207;
|
|
add.f32 %f753, %f16, %f752;
|
|
sub.f32 %f754, %f17, %f752;
|
|
mul.f32 %f755, %f753, 0f3DD32618;
|
|
cvt.rmi.f32.f32 %f756, %f755;
|
|
sub.f32 %f757, %f755, %f756;
|
|
mul.f32 %f758, %f754, 0f3DD2F1AA;
|
|
cvt.rmi.f32.f32 %f759, %f758;
|
|
sub.f32 %f760, %f758, %f759;
|
|
mul.f32 %f761, %f752, 0f3DC74539;
|
|
cvt.rmi.f32.f32 %f762, %f761;
|
|
sub.f32 %f763, %f761, %f762;
|
|
add.f32 %f764, %f760, 0f420551EC;
|
|
add.f32 %f765, %f757, 0f420551EC;
|
|
add.f32 %f766, %f763, 0f420551EC;
|
|
mul.f32 %f767, %f757, %f764;
|
|
fma.rn.f32 %f768, %f760, %f765, %f767;
|
|
fma.rn.f32 %f769, %f763, %f766, %f768;
|
|
add.f32 %f770, %f757, %f769;
|
|
add.f32 %f771, %f760, %f769;
|
|
add.f32 %f772, %f763, %f769;
|
|
add.f32 %f773, %f770, %f771;
|
|
mul.f32 %f774, %f772, %f773;
|
|
cvt.rmi.f32.f32 %f775, %f774;
|
|
sub.f32 %f776, %f774, %f775;
|
|
add.f32 %f777, %f770, %f770;
|
|
mul.f32 %f778, %f771, %f777;
|
|
cvt.rmi.f32.f32 %f779, %f778;
|
|
sub.f32 %f780, %f778, %f779;
|
|
mul.f32 %f781, %f770, %f773;
|
|
cvt.rmi.f32.f32 %f782, %f781;
|
|
sub.f32 %f783, %f781, %f782;
|
|
fma.rn.f32 %f784, %f776, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f785, %f780, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f786, %f783, 0f40000000, 0fBF800000;
|
|
ld.global.f32 %f787, [%rd5+16];
|
|
ld.global.f32 %f788, [%rd5+4];
|
|
fma.rn.f32 %f789, %f787, %f784, %f788;
|
|
ld.global.f32 %f790, [%rd5+8];
|
|
fma.rn.f32 %f791, %f787, %f785, %f790;
|
|
ld.global.f32 %f792, [%rd5+12];
|
|
fma.rn.f32 %f793, %f787, %f786, %f792;
|
|
sub.f32 %f794, %f789, %f10;
|
|
sub.f32 %f795, %f791, %f11;
|
|
sub.f32 %f796, %f793, %f12;
|
|
mul.f32 %f797, %f795, %f795;
|
|
fma.rn.f32 %f798, %f794, %f794, %f797;
|
|
fma.rn.f32 %f799, %f796, %f796, %f798;
|
|
sqrt.rn.f32 %f699, %f799;
|
|
rcp.rn.f32 %f800, %f699;
|
|
mul.f32 %f695, %f800, %f794;
|
|
mul.f32 %f696, %f800, %f795;
|
|
mul.f32 %f697, %f800, %f796;
|
|
// begin inline asm
|
|
call(%r136,%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167),_optix_trace_typed_32,(%r206,%rd3,%f13,%f14,%f15,%f695,%f696,%f697,%f169,%f699,%f700,%r174,%r206,%r174,%r172,%r174,%r174,%r175,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206,%r206);
|
|
// end inline asm
|
|
mov.b32 %f801, %r136;
|
|
add.f32 %f1792, %f751, %f801;
|
|
add.s32 %r446, %r446, 2;
|
|
add.s32 %r445, %r445, -2;
|
|
setp.ne.s32 %p48, %r445, 0;
|
|
@%p48 bra $L__BB0_36;
|
|
|
|
$L__BB0_37:
|
|
setp.eq.s32 %p49, %r11, 0;
|
|
@%p49 bra $L__BB0_39;
|
|
|
|
cvt.rn.f32.s32 %f811, %r446;
|
|
add.f32 %f812, %f16, %f811;
|
|
sub.f32 %f813, %f17, %f811;
|
|
mul.f32 %f814, %f812, 0f3DD32618;
|
|
cvt.rmi.f32.f32 %f815, %f814;
|
|
sub.f32 %f816, %f814, %f815;
|
|
mul.f32 %f817, %f813, 0f3DD2F1AA;
|
|
cvt.rmi.f32.f32 %f818, %f817;
|
|
sub.f32 %f819, %f817, %f818;
|
|
mul.f32 %f820, %f811, 0f3DC74539;
|
|
cvt.rmi.f32.f32 %f821, %f820;
|
|
sub.f32 %f822, %f820, %f821;
|
|
add.f32 %f823, %f819, 0f420551EC;
|
|
add.f32 %f824, %f816, 0f420551EC;
|
|
add.f32 %f825, %f822, 0f420551EC;
|
|
mul.f32 %f826, %f816, %f823;
|
|
fma.rn.f32 %f827, %f819, %f824, %f826;
|
|
fma.rn.f32 %f828, %f822, %f825, %f827;
|
|
add.f32 %f829, %f816, %f828;
|
|
add.f32 %f830, %f819, %f828;
|
|
add.f32 %f831, %f822, %f828;
|
|
add.f32 %f832, %f829, %f830;
|
|
mul.f32 %f833, %f831, %f832;
|
|
cvt.rmi.f32.f32 %f834, %f833;
|
|
sub.f32 %f835, %f833, %f834;
|
|
add.f32 %f836, %f829, %f829;
|
|
mul.f32 %f837, %f830, %f836;
|
|
cvt.rmi.f32.f32 %f838, %f837;
|
|
sub.f32 %f839, %f837, %f838;
|
|
mul.f32 %f840, %f829, %f832;
|
|
cvt.rmi.f32.f32 %f841, %f840;
|
|
sub.f32 %f842, %f840, %f841;
|
|
fma.rn.f32 %f843, %f835, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f844, %f839, 0f40000000, 0fBF800000;
|
|
fma.rn.f32 %f845, %f842, 0f40000000, 0fBF800000;
|
|
ld.global.f32 %f846, [%rd5+16];
|
|
ld.global.f32 %f847, [%rd5+4];
|
|
fma.rn.f32 %f848, %f846, %f843, %f847;
|
|
ld.global.f32 %f849, [%rd5+8];
|
|
fma.rn.f32 %f850, %f846, %f844, %f849;
|
|
ld.global.f32 %f851, [%rd5+12];
|
|
fma.rn.f32 %f852, %f846, %f845, %f851;
|
|
sub.f32 %f853, %f848, %f10;
|
|
sub.f32 %f854, %f850, %f11;
|
|
sub.f32 %f855, %f852, %f12;
|
|
mul.f32 %f856, %f854, %f854;
|
|
fma.rn.f32 %f857, %f853, %f853, %f856;
|
|
fma.rn.f32 %f858, %f855, %f855, %f857;
|
|
sqrt.rn.f32 %f809, %f858;
|
|
rcp.rn.f32 %f859, %f809;
|
|
mul.f32 %f805, %f859, %f853;
|
|
mul.f32 %f806, %f859, %f854;
|
|
mul.f32 %f807, %f859, %f855;
|
|
mov.f32 %f810, 0f00000000;
|
|
mov.u32 %r244, 2;
|
|
mov.u32 %r246, 1;
|
|
mov.u32 %r247, 1065353216;
|
|
mov.u32 %r278, 0;
|
|
// begin inline asm
|
|
call(%r208,%r209,%r210,%r211,%r212,%r213,%r214,%r215,%r216,%r217,%r218,%r219,%r220,%r221,%r222,%r223,%r224,%r225,%r226,%r227,%r228,%r229,%r230,%r231,%r232,%r233,%r234,%r235,%r236,%r237,%r238,%r239),_optix_trace_typed_32,(%r278,%rd3,%f13,%f14,%f15,%f805,%f806,%f807,%f169,%f809,%f810,%r246,%r278,%r246,%r244,%r246,%r246,%r247,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278,%r278);
|
|
// end inline asm
|
|
mov.b32 %f860, %r208;
|
|
add.f32 %f1792, %f1792, %f860;
|
|
|
|
$L__BB0_39:
|
|
cvt.rn.f32.s32 %f861, %r10;
|
|
div.rn.f32 %f1796, %f1792, %f861;
|
|
shr.u32 %r279, %r44, 31;
|
|
cvt.u16.u32 %rs329, %r279;
|
|
|
|
$L__BB0_40:
|
|
fma.rn.f32 %f1797, %f1790, %f1796, %f1797;
|
|
fma.rn.f32 %f1798, %f1789, %f1796, %f1798;
|
|
fma.rn.f32 %f1799, %f1788, %f1796, %f1799;
|
|
fma.rn.f32 %f1800, %f1787, %f1796, %f1800;
|
|
fma.rn.f32 %f1801, %f1786, %f1796, %f1801;
|
|
fma.rn.f32 %f1802, %f1785, %f1796, %f1802;
|
|
fma.rn.f32 %f1803, %f1784, %f1796, %f1803;
|
|
fma.rn.f32 %f1804, %f1783, %f1796, %f1804;
|
|
fma.rn.f32 %f1805, %f1782, %f1796, %f1805;
|
|
fma.rn.f32 %f1806, %f1781, %f1796, %f1806;
|
|
fma.rn.f32 %f1807, %f1780, %f1796, %f1807;
|
|
fma.rn.f32 %f1808, %f1779, %f1796, %f1808;
|
|
fma.rn.f32 %f1809, %f1778, %f1796, %f1809;
|
|
fma.rn.f32 %f1810, %f1777, %f1796, %f1810;
|
|
fma.rn.f32 %f1811, %f1776, %f1796, %f1811;
|
|
fma.rn.f32 %f1812, %f1775, %f1796, %f1812;
|
|
fma.rn.f32 %f1813, %f1774, %f1796, %f1813;
|
|
fma.rn.f32 %f1814, %f1773, %f1796, %f1814;
|
|
fma.rn.f32 %f1815, %f1772, %f1796, %f1815;
|
|
fma.rn.f32 %f1816, %f1771, %f1796, %f1816;
|
|
fma.rn.f32 %f1817, %f1770, %f1796, %f1817;
|
|
fma.rn.f32 %f1818, %f1769, %f1796, %f1818;
|
|
fma.rn.f32 %f1819, %f1768, %f1796, %f1819;
|
|
fma.rn.f32 %f1820, %f1767, %f1796, %f1820;
|
|
fma.rn.f32 %f1821, %f1766, %f1796, %f1821;
|
|
fma.rn.f32 %f1822, %f1765, %f1796, %f1822;
|
|
fma.rn.f32 %f1823, %f1764, %f1796, %f1823;
|
|
fma.rn.f32 %f1824, %f1763, %f1796, %f1824;
|
|
fma.rn.f32 %f1825, %f1762, %f1796, %f1825;
|
|
fma.rn.f32 %f1826, %f1761, %f1796, %f1826;
|
|
setp.eq.s16 %p50, %rs329, 0;
|
|
@%p50 bra $L__BB0_42;
|
|
|
|
div.rn.f32 %f862, %f1790, %f469;
|
|
div.rn.f32 %f863, %f862, %f88;
|
|
cvt.sat.f32.f32 %f864, %f863;
|
|
mul.f32 %f1796, %f1796, %f864;
|
|
|
|
$L__BB0_42:
|
|
add.f32 %f1827, %f1827, %f1796;
|
|
|
|
$L__BB0_43:
|
|
cvt.u64.u32 %rd117, %r443;
|
|
cvt.u32.u64 %r280, %rd117;
|
|
add.s32 %r443, %r280, 1;
|
|
setp.lt.u32 %p51, %r443, %r5;
|
|
@%p51 bra $L__BB0_7;
|
|
bra.uni $L__BB0_45;
|
|
|
|
$L__BB0_44:
|
|
mov.f32 %f1797, 0f00000000;
|
|
ld.const.u32 %r447, [params+104];
|
|
mov.f32 %f1798, %f1797;
|
|
mov.f32 %f1799, %f1797;
|
|
mov.f32 %f1800, %f1797;
|
|
mov.f32 %f1801, %f1797;
|
|
mov.f32 %f1802, %f1797;
|
|
mov.f32 %f1803, %f1797;
|
|
mov.f32 %f1804, %f1797;
|
|
mov.f32 %f1805, %f1797;
|
|
mov.f32 %f1806, %f1797;
|
|
mov.f32 %f1807, %f1797;
|
|
mov.f32 %f1808, %f1797;
|
|
mov.f32 %f1809, %f1797;
|
|
mov.f32 %f1810, %f1797;
|
|
mov.f32 %f1811, %f1797;
|
|
mov.f32 %f1812, %f1797;
|
|
mov.f32 %f1813, %f1797;
|
|
mov.f32 %f1814, %f1797;
|
|
mov.f32 %f1815, %f1797;
|
|
mov.f32 %f1816, %f1797;
|
|
mov.f32 %f1817, %f1797;
|
|
mov.f32 %f1818, %f1797;
|
|
mov.f32 %f1819, %f1797;
|
|
mov.f32 %f1820, %f1797;
|
|
mov.f32 %f1821, %f1797;
|
|
mov.f32 %f1822, %f1797;
|
|
mov.f32 %f1823, %f1797;
|
|
mov.f32 %f1824, %f1797;
|
|
mov.f32 %f1825, %f1797;
|
|
mov.f32 %f1826, %f1797;
|
|
mov.f32 %f1827, %f1797;
|
|
|
|
$L__BB0_45:
|
|
and.b32 %r281, %r447, 8;
|
|
setp.eq.s32 %p52, %r281, 0;
|
|
@%p52 bra $L__BB0_59;
|
|
|
|
cvt.sat.f32.f32 %f273, %f1827;
|
|
ld.const.u64 %rd43, [params+192];
|
|
cvta.to.global.u64 %rd7, %rd43;
|
|
ld.const.u32 %r282, [params+184];
|
|
mad.lo.s32 %r283, %r282, %r4, %r3;
|
|
cvt.u64.u32 %rd8, %r283;
|
|
mov.f32 %f897, 0f3E68BA2E;
|
|
cvt.rzi.f32.f32 %f898, %f897;
|
|
add.f32 %f899, %f898, %f898;
|
|
mov.f32 %f900, 0f3EE8BA2E;
|
|
sub.f32 %f901, %f900, %f899;
|
|
abs.f32 %f274, %f901;
|
|
abs.f32 %f275, %f273;
|
|
setp.lt.f32 %p53, %f275, 0f00800000;
|
|
mul.f32 %f902, %f275, 0f4B800000;
|
|
selp.f32 %f903, %f902, %f275, %p53;
|
|
selp.f32 %f904, 0fC3170000, 0fC2FE0000, %p53;
|
|
mov.b32 %r284, %f903;
|
|
and.b32 %r285, %r284, 8388607;
|
|
or.b32 %r286, %r285, 1065353216;
|
|
mov.b32 %f905, %r286;
|
|
shr.u32 %r287, %r284, 23;
|
|
cvt.rn.f32.u32 %f906, %r287;
|
|
add.f32 %f907, %f904, %f906;
|
|
setp.gt.f32 %p54, %f905, 0f3FB504F3;
|
|
mul.f32 %f908, %f905, 0f3F000000;
|
|
add.f32 %f909, %f907, 0f3F800000;
|
|
selp.f32 %f910, %f909, %f907, %p54;
|
|
selp.f32 %f911, %f908, %f905, %p54;
|
|
add.f32 %f912, %f911, 0fBF800000;
|
|
add.f32 %f913, %f911, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f914, %f913;
|
|
add.f32 %f915, %f912, %f912;
|
|
mul.f32 %f916, %f915, %f914;
|
|
mul.f32 %f917, %f916, %f916;
|
|
mov.f32 %f918, 0f3C4CAF63;
|
|
mov.f32 %f919, 0f3B18F0FE;
|
|
fma.rn.f32 %f920, %f919, %f917, %f918;
|
|
mov.f32 %f921, 0f3DAAAABD;
|
|
fma.rn.f32 %f922, %f920, %f917, %f921;
|
|
mul.rn.f32 %f923, %f922, %f917;
|
|
mul.rn.f32 %f924, %f923, %f916;
|
|
sub.f32 %f925, %f912, %f916;
|
|
add.f32 %f926, %f925, %f925;
|
|
neg.f32 %f927, %f916;
|
|
fma.rn.f32 %f928, %f927, %f912, %f926;
|
|
mul.rn.f32 %f929, %f914, %f928;
|
|
add.f32 %f930, %f924, %f916;
|
|
sub.f32 %f931, %f916, %f930;
|
|
add.f32 %f932, %f924, %f931;
|
|
add.f32 %f933, %f929, %f932;
|
|
add.f32 %f934, %f930, %f933;
|
|
sub.f32 %f935, %f930, %f934;
|
|
add.f32 %f936, %f933, %f935;
|
|
mov.f32 %f937, 0f3F317200;
|
|
mul.rn.f32 %f938, %f910, %f937;
|
|
mov.f32 %f939, 0f35BFBE8E;
|
|
mul.rn.f32 %f940, %f910, %f939;
|
|
add.f32 %f941, %f938, %f934;
|
|
sub.f32 %f942, %f938, %f941;
|
|
add.f32 %f943, %f934, %f942;
|
|
add.f32 %f944, %f936, %f943;
|
|
add.f32 %f945, %f940, %f944;
|
|
add.f32 %f946, %f941, %f945;
|
|
sub.f32 %f947, %f941, %f946;
|
|
add.f32 %f948, %f945, %f947;
|
|
mul.rn.f32 %f949, %f900, %f946;
|
|
neg.f32 %f950, %f949;
|
|
fma.rn.f32 %f951, %f900, %f946, %f950;
|
|
fma.rn.f32 %f952, %f900, %f948, %f951;
|
|
mov.f32 %f953, 0f00000000;
|
|
fma.rn.f32 %f954, %f953, %f946, %f952;
|
|
add.rn.f32 %f955, %f949, %f954;
|
|
neg.f32 %f956, %f955;
|
|
add.rn.f32 %f957, %f949, %f956;
|
|
add.rn.f32 %f958, %f957, %f954;
|
|
mov.b32 %r288, %f955;
|
|
setp.eq.s32 %p55, %r288, 1118925336;
|
|
add.s32 %r289, %r288, -1;
|
|
mov.b32 %f959, %r289;
|
|
add.f32 %f960, %f958, 0f37000000;
|
|
selp.f32 %f276, %f960, %f958, %p55;
|
|
selp.f32 %f961, %f959, %f955, %p55;
|
|
mov.f32 %f962, 0f3FB8AA3B;
|
|
mul.rn.f32 %f963, %f961, %f962;
|
|
cvt.rzi.f32.f32 %f964, %f963;
|
|
abs.f32 %f965, %f964;
|
|
setp.gt.f32 %p56, %f965, 0f42FC0000;
|
|
mov.b32 %r290, %f964;
|
|
and.b32 %r291, %r290, -2147483648;
|
|
or.b32 %r292, %r291, 1123811328;
|
|
mov.b32 %f966, %r292;
|
|
selp.f32 %f967, %f966, %f964, %p56;
|
|
mov.f32 %f968, 0fBF317218;
|
|
fma.rn.f32 %f969, %f967, %f968, %f961;
|
|
mov.f32 %f970, 0f3102E308;
|
|
fma.rn.f32 %f971, %f967, %f970, %f969;
|
|
mul.f32 %f972, %f971, 0f3FB8AA3B;
|
|
add.f32 %f973, %f967, 0f4B40007F;
|
|
mov.b32 %r293, %f973;
|
|
shl.b32 %r294, %r293, 23;
|
|
mov.b32 %f974, %r294;
|
|
ex2.approx.ftz.f32 %f975, %f972;
|
|
mul.f32 %f277, %f975, %f974;
|
|
setp.eq.f32 %p57, %f277, 0f7F800000;
|
|
mov.f32 %f1859, 0f7F800000;
|
|
@%p57 bra $L__BB0_48;
|
|
|
|
fma.rn.f32 %f1859, %f277, %f276, %f277;
|
|
|
|
$L__BB0_48:
|
|
setp.lt.f32 %p58, %f273, 0f00000000;
|
|
setp.eq.f32 %p59, %f274, 0f3F800000;
|
|
and.pred %p3, %p58, %p59;
|
|
setp.eq.f32 %p60, %f273, 0f00000000;
|
|
@%p60 bra $L__BB0_52;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_52:
|
|
add.f32 %f980, %f273, %f273;
|
|
selp.f32 %f1861, %f980, 0f00000000, %p59;
|
|
bra.uni $L__BB0_53;
|
|
|
|
$L__BB0_171:
|
|
mov.f32 %f1631, 0f00000000;
|
|
mov.u32 %r449, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs190, %f1631;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs189, %f1631;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs188, %f1631;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs191, 0;
|
|
st.global.v4.u16 [%rd21], {%rs188, %rs189, %rs190, %rs191};
|
|
|
|
$L__BB0_172:
|
|
ld.const.u64 %rd90, [params+256];
|
|
cvta.to.global.u64 %rd91, %rd90;
|
|
ld.const.u32 %r425, [params+248];
|
|
mad.lo.s32 %r426, %r425, %r4, %r3;
|
|
mul.wide.u32 %rd92, %r426, 8;
|
|
add.s64 %rd22, %rd91, %rd92;
|
|
setp.eq.s32 %p183, %r449, 0;
|
|
@%p183 bra $L__BB0_174;
|
|
|
|
ld.global.v4.u16 {%rs198, %rs199, %rs200, %rs201}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1632, %rs198;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1633, %rs199;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1634, %rs200;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1635, %f1632, 0f00000000;
|
|
add.f32 %f1636, %f1633, 0f00000000;
|
|
add.f32 %f1637, %f1634, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs197, %f1637;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs196, %f1636;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs195, %f1635;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs202, 0;
|
|
st.global.v4.u16 [%rd22], {%rs195, %rs196, %rs197, %rs202};
|
|
bra.uni $L__BB0_175;
|
|
|
|
$L__BB0_174:
|
|
mov.f32 %f1640, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs205, %f1640;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs204, %f1640;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs203, %f1640;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs206, 0;
|
|
st.global.v4.u16 [%rd22], {%rs203, %rs204, %rs205, %rs206};
|
|
|
|
$L__BB0_175:
|
|
ld.const.u64 %rd93, [params+272];
|
|
cvta.to.global.u64 %rd94, %rd93;
|
|
ld.const.u32 %r427, [params+264];
|
|
mad.lo.s32 %r428, %r427, %r4, %r3;
|
|
mul.wide.u32 %rd95, %r428, 8;
|
|
add.s64 %rd23, %rd94, %rd95;
|
|
@%p183 bra $L__BB0_177;
|
|
|
|
ld.global.v4.u16 {%rs213, %rs214, %rs215, %rs216}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1641, %rs213;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1642, %rs214;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1643, %rs215;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1644, %f1641, 0f00000000;
|
|
add.f32 %f1645, %f1642, 0f00000000;
|
|
add.f32 %f1646, %f1643, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs212, %f1646;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs211, %f1645;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs210, %f1644;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs217, 0;
|
|
st.global.v4.u16 [%rd23], {%rs210, %rs211, %rs212, %rs217};
|
|
bra.uni $L__BB0_178;
|
|
|
|
$L__BB0_177:
|
|
mov.f32 %f1649, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs220, %f1649;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs219, %f1649;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs218, %f1649;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs221, 0;
|
|
st.global.v4.u16 [%rd23], {%rs218, %rs219, %rs220, %rs221};
|
|
|
|
$L__BB0_178:
|
|
ld.const.u64 %rd96, [params+288];
|
|
cvta.to.global.u64 %rd97, %rd96;
|
|
ld.const.u32 %r429, [params+280];
|
|
mad.lo.s32 %r430, %r429, %r4, %r3;
|
|
mul.wide.u32 %rd98, %r430, 8;
|
|
add.s64 %rd24, %rd97, %rd98;
|
|
@%p183 bra $L__BB0_180;
|
|
|
|
ld.global.v4.u16 {%rs228, %rs229, %rs230, %rs231}, [%rd24];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1650, %rs228;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1651, %rs229;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1652, %rs230;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1653, %f1650, 0f00000000;
|
|
add.f32 %f1654, %f1651, 0f00000000;
|
|
add.f32 %f1655, %f1652, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs227, %f1655;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs226, %f1654;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs225, %f1653;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs232, 0;
|
|
st.global.v4.u16 [%rd24], {%rs225, %rs226, %rs227, %rs232};
|
|
bra.uni $L__BB0_181;
|
|
|
|
$L__BB0_180:
|
|
mov.f32 %f1658, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs235, %f1658;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs234, %f1658;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs233, %f1658;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs236, 0;
|
|
st.global.v4.u16 [%rd24], {%rs233, %rs234, %rs235, %rs236};
|
|
|
|
$L__BB0_181:
|
|
ld.const.u64 %rd99, [params+304];
|
|
cvta.to.global.u64 %rd100, %rd99;
|
|
ld.const.u32 %r431, [params+296];
|
|
mad.lo.s32 %r432, %r431, %r4, %r3;
|
|
mul.wide.u32 %rd101, %r432, 8;
|
|
add.s64 %rd25, %rd100, %rd101;
|
|
@%p183 bra $L__BB0_183;
|
|
|
|
ld.global.v4.u16 {%rs243, %rs244, %rs245, %rs246}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1659, %rs243;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1660, %rs244;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1661, %rs245;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1662, %f1659, 0f00000000;
|
|
add.f32 %f1663, %f1660, 0f00000000;
|
|
add.f32 %f1664, %f1661, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs242, %f1664;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs241, %f1663;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs240, %f1662;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs247, 0;
|
|
st.global.v4.u16 [%rd25], {%rs240, %rs241, %rs242, %rs247};
|
|
bra.uni $L__BB0_184;
|
|
|
|
$L__BB0_183:
|
|
mov.f32 %f1667, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs250, %f1667;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs249, %f1667;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs248, %f1667;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs251, 0;
|
|
st.global.v4.u16 [%rd25], {%rs248, %rs249, %rs250, %rs251};
|
|
|
|
$L__BB0_184:
|
|
ld.const.u64 %rd102, [params+320];
|
|
cvta.to.global.u64 %rd103, %rd102;
|
|
ld.const.u32 %r433, [params+312];
|
|
mad.lo.s32 %r434, %r433, %r4, %r3;
|
|
mul.wide.u32 %rd104, %r434, 8;
|
|
add.s64 %rd26, %rd103, %rd104;
|
|
@%p183 bra $L__BB0_186;
|
|
|
|
ld.global.v4.u16 {%rs258, %rs259, %rs260, %rs261}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1668, %rs258;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1669, %rs259;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1670, %rs260;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1671, %f1668, 0f00000000;
|
|
add.f32 %f1672, %f1669, 0f00000000;
|
|
add.f32 %f1673, %f1670, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs257, %f1673;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs256, %f1672;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs255, %f1671;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs262, 0;
|
|
st.global.v4.u16 [%rd26], {%rs255, %rs256, %rs257, %rs262};
|
|
bra.uni $L__BB0_187;
|
|
|
|
$L__BB0_186:
|
|
mov.f32 %f1676, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs265, %f1676;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs264, %f1676;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs263, %f1676;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs266, 0;
|
|
st.global.v4.u16 [%rd26], {%rs263, %rs264, %rs265, %rs266};
|
|
|
|
$L__BB0_187:
|
|
ld.const.u64 %rd105, [params+336];
|
|
cvta.to.global.u64 %rd106, %rd105;
|
|
ld.const.u32 %r435, [params+328];
|
|
mad.lo.s32 %r436, %r435, %r4, %r3;
|
|
mul.wide.u32 %rd107, %r436, 8;
|
|
add.s64 %rd27, %rd106, %rd107;
|
|
@%p183 bra $L__BB0_189;
|
|
|
|
ld.global.v4.u16 {%rs273, %rs274, %rs275, %rs276}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1677, %rs273;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1678, %rs274;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1679, %rs275;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1680, %f1677, 0f00000000;
|
|
add.f32 %f1681, %f1678, 0f00000000;
|
|
add.f32 %f1682, %f1679, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs272, %f1682;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs271, %f1681;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs270, %f1680;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs277, 0;
|
|
st.global.v4.u16 [%rd27], {%rs270, %rs271, %rs272, %rs277};
|
|
bra.uni $L__BB0_190;
|
|
|
|
$L__BB0_189:
|
|
mov.f32 %f1685, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs280, %f1685;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs279, %f1685;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs278, %f1685;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs281, 0;
|
|
st.global.v4.u16 [%rd27], {%rs278, %rs279, %rs280, %rs281};
|
|
|
|
$L__BB0_190:
|
|
ld.const.u64 %rd108, [params+352];
|
|
cvta.to.global.u64 %rd109, %rd108;
|
|
ld.const.u32 %r437, [params+344];
|
|
mad.lo.s32 %r438, %r437, %r4, %r3;
|
|
mul.wide.u32 %rd110, %r438, 8;
|
|
add.s64 %rd28, %rd109, %rd110;
|
|
@%p183 bra $L__BB0_192;
|
|
|
|
ld.global.v4.u16 {%rs288, %rs289, %rs290, %rs291}, [%rd28];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1686, %rs288;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1687, %rs289;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1688, %rs290;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1689, %f1686, 0f00000000;
|
|
add.f32 %f1690, %f1687, 0f00000000;
|
|
add.f32 %f1691, %f1688, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs287, %f1691;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs286, %f1690;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs285, %f1689;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs292, 0;
|
|
st.global.v4.u16 [%rd28], {%rs285, %rs286, %rs287, %rs292};
|
|
bra.uni $L__BB0_193;
|
|
|
|
$L__BB0_192:
|
|
mov.f32 %f1694, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs295, %f1694;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs294, %f1694;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs293, %f1694;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs296, 0;
|
|
st.global.v4.u16 [%rd28], {%rs293, %rs294, %rs295, %rs296};
|
|
|
|
$L__BB0_193:
|
|
ld.const.u64 %rd111, [params+368];
|
|
cvta.to.global.u64 %rd112, %rd111;
|
|
ld.const.u32 %r439, [params+360];
|
|
mad.lo.s32 %r440, %r439, %r4, %r3;
|
|
mul.wide.u32 %rd113, %r440, 8;
|
|
add.s64 %rd29, %rd112, %rd113;
|
|
@%p183 bra $L__BB0_195;
|
|
|
|
ld.global.v4.u16 {%rs303, %rs304, %rs305, %rs306}, [%rd29];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1695, %rs303;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1696, %rs304;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1697, %rs305;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1698, %f1695, 0f00000000;
|
|
add.f32 %f1699, %f1696, 0f00000000;
|
|
add.f32 %f1700, %f1697, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs302, %f1700;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs301, %f1699;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs300, %f1698;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs307, 0;
|
|
st.global.v4.u16 [%rd29], {%rs300, %rs301, %rs302, %rs307};
|
|
bra.uni $L__BB0_196;
|
|
|
|
$L__BB0_195:
|
|
mov.f32 %f1703, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs310, %f1703;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs309, %f1703;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs308, %f1703;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs311, 0;
|
|
st.global.v4.u16 [%rd29], {%rs308, %rs309, %rs310, %rs311};
|
|
|
|
$L__BB0_196:
|
|
ld.const.u64 %rd114, [params+384];
|
|
cvta.to.global.u64 %rd115, %rd114;
|
|
ld.const.u32 %r441, [params+376];
|
|
mad.lo.s32 %r442, %r441, %r4, %r3;
|
|
mul.wide.u32 %rd116, %r442, 8;
|
|
add.s64 %rd30, %rd115, %rd116;
|
|
@%p183 bra $L__BB0_198;
|
|
|
|
ld.global.v4.u16 {%rs318, %rs319, %rs320, %rs321}, [%rd30];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1704, %rs318;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1705, %rs319;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1706, %rs320;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1707, %f1704, 0f00000000;
|
|
add.f32 %f1708, %f1705, 0f00000000;
|
|
add.f32 %f1709, %f1706, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs317, %f1709;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs316, %f1708;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs315, %f1707;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs322, 0;
|
|
st.global.v4.u16 [%rd30], {%rs315, %rs316, %rs317, %rs322};
|
|
bra.uni $L__BB0_199;
|
|
|
|
$L__BB0_198:
|
|
mov.f32 %f1712, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs325, %f1712;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs324, %f1712;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs323, %f1712;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs326, 0;
|
|
st.global.v4.u16 [%rd30], {%rs323, %rs324, %rs325, %rs326};
|
|
bra.uni $L__BB0_199;
|
|
|
|
$L__BB0_49:
|
|
mov.b32 %r295, %f1859;
|
|
xor.b32 %r296, %r295, -2147483648;
|
|
mov.b32 %f976, %r296;
|
|
selp.f32 %f1861, %f976, %f1859, %p3;
|
|
setp.geu.f32 %p61, %f273, 0f00000000;
|
|
@%p61 bra $L__BB0_53;
|
|
|
|
mov.f32 %f977, 0f3EE8BA2E;
|
|
cvt.rzi.f32.f32 %f978, %f977;
|
|
setp.eq.f32 %p62, %f978, 0f3EE8BA2E;
|
|
@%p62 bra $L__BB0_53;
|
|
|
|
mov.f32 %f1861, 0f7FFFFFFF;
|
|
|
|
$L__BB0_53:
|
|
add.f32 %f981, %f275, 0f3EE8BA2E;
|
|
mov.b32 %r297, %f981;
|
|
setp.lt.s32 %p64, %r297, 2139095040;
|
|
@%p64 bra $L__BB0_58;
|
|
|
|
setp.gtu.f32 %p65, %f275, 0f7F800000;
|
|
@%p65 bra $L__BB0_57;
|
|
bra.uni $L__BB0_55;
|
|
|
|
$L__BB0_57:
|
|
add.f32 %f1861, %f273, 0f3EE8BA2E;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_55:
|
|
setp.neu.f32 %p66, %f275, 0f7F800000;
|
|
@%p66 bra $L__BB0_58;
|
|
|
|
selp.f32 %f1861, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_58:
|
|
mul.f32 %f982, %f1861, 0f437F0000;
|
|
setp.eq.f32 %p67, %f273, 0f3F800000;
|
|
selp.f32 %f983, 0f437F0000, %f982, %p67;
|
|
cvt.rzi.u32.f32 %r298, %f983;
|
|
shl.b64 %rd44, %rd8, 1;
|
|
add.s64 %rd45, %rd7, %rd44;
|
|
cvt.u16.u32 %rs18, %r298;
|
|
mov.u16 %rs19, 255;
|
|
st.global.v2.u8 [%rd45], {%rs18, %rs19};
|
|
|
|
$L__BB0_59:
|
|
and.b32 %r299, %r447, 1;
|
|
setp.eq.b32 %p68, %r299, 1;
|
|
mov.pred %p69, 0;
|
|
xor.pred %p70, %p68, %p69;
|
|
not.pred %p71, %p70;
|
|
@%p71 bra $L__BB0_133;
|
|
|
|
mov.f32 %f985, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f986, %f985;
|
|
add.f32 %f987, %f986, %f986;
|
|
mov.f32 %f988, 0f3EE66666;
|
|
sub.f32 %f989, %f988, %f987;
|
|
abs.f32 %f286, %f989;
|
|
abs.f32 %f287, %f1797;
|
|
setp.lt.f32 %p72, %f287, 0f00800000;
|
|
mul.f32 %f990, %f287, 0f4B800000;
|
|
selp.f32 %f991, %f990, %f287, %p72;
|
|
selp.f32 %f992, 0fC3170000, 0fC2FE0000, %p72;
|
|
mov.b32 %r300, %f991;
|
|
and.b32 %r301, %r300, 8388607;
|
|
or.b32 %r302, %r301, 1065353216;
|
|
mov.b32 %f993, %r302;
|
|
shr.u32 %r303, %r300, 23;
|
|
cvt.rn.f32.u32 %f994, %r303;
|
|
add.f32 %f995, %f992, %f994;
|
|
setp.gt.f32 %p73, %f993, 0f3FB504F3;
|
|
mul.f32 %f996, %f993, 0f3F000000;
|
|
add.f32 %f997, %f995, 0f3F800000;
|
|
selp.f32 %f998, %f997, %f995, %p73;
|
|
selp.f32 %f999, %f996, %f993, %p73;
|
|
add.f32 %f1000, %f999, 0fBF800000;
|
|
add.f32 %f1001, %f999, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1002, %f1001;
|
|
add.f32 %f1003, %f1000, %f1000;
|
|
mul.f32 %f1004, %f1003, %f1002;
|
|
mul.f32 %f1005, %f1004, %f1004;
|
|
mov.f32 %f1006, 0f3C4CAF63;
|
|
mov.f32 %f1007, 0f3B18F0FE;
|
|
fma.rn.f32 %f1008, %f1007, %f1005, %f1006;
|
|
mov.f32 %f1009, 0f3DAAAABD;
|
|
fma.rn.f32 %f1010, %f1008, %f1005, %f1009;
|
|
mul.rn.f32 %f1011, %f1010, %f1005;
|
|
mul.rn.f32 %f1012, %f1011, %f1004;
|
|
sub.f32 %f1013, %f1000, %f1004;
|
|
add.f32 %f1014, %f1013, %f1013;
|
|
neg.f32 %f1015, %f1004;
|
|
fma.rn.f32 %f1016, %f1015, %f1000, %f1014;
|
|
mul.rn.f32 %f1017, %f1002, %f1016;
|
|
add.f32 %f1018, %f1012, %f1004;
|
|
sub.f32 %f1019, %f1004, %f1018;
|
|
add.f32 %f1020, %f1012, %f1019;
|
|
add.f32 %f1021, %f1017, %f1020;
|
|
add.f32 %f1022, %f1018, %f1021;
|
|
sub.f32 %f1023, %f1018, %f1022;
|
|
add.f32 %f1024, %f1021, %f1023;
|
|
mov.f32 %f1025, 0f3F317200;
|
|
mul.rn.f32 %f1026, %f998, %f1025;
|
|
mov.f32 %f1027, 0f35BFBE8E;
|
|
mul.rn.f32 %f1028, %f998, %f1027;
|
|
add.f32 %f1029, %f1026, %f1022;
|
|
sub.f32 %f1030, %f1026, %f1029;
|
|
add.f32 %f1031, %f1022, %f1030;
|
|
add.f32 %f1032, %f1024, %f1031;
|
|
add.f32 %f1033, %f1028, %f1032;
|
|
add.f32 %f1034, %f1029, %f1033;
|
|
sub.f32 %f1035, %f1029, %f1034;
|
|
add.f32 %f1036, %f1033, %f1035;
|
|
mul.rn.f32 %f1037, %f988, %f1034;
|
|
neg.f32 %f1038, %f1037;
|
|
fma.rn.f32 %f1039, %f988, %f1034, %f1038;
|
|
fma.rn.f32 %f1040, %f988, %f1036, %f1039;
|
|
mov.f32 %f1041, 0f00000000;
|
|
fma.rn.f32 %f1042, %f1041, %f1034, %f1040;
|
|
add.rn.f32 %f1043, %f1037, %f1042;
|
|
neg.f32 %f1044, %f1043;
|
|
add.rn.f32 %f1045, %f1037, %f1044;
|
|
add.rn.f32 %f1046, %f1045, %f1042;
|
|
mov.b32 %r304, %f1043;
|
|
setp.eq.s32 %p74, %r304, 1118925336;
|
|
add.s32 %r305, %r304, -1;
|
|
mov.b32 %f1047, %r305;
|
|
add.f32 %f1048, %f1046, 0f37000000;
|
|
selp.f32 %f288, %f1048, %f1046, %p74;
|
|
selp.f32 %f1049, %f1047, %f1043, %p74;
|
|
mov.f32 %f1050, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1051, %f1049, %f1050;
|
|
cvt.rzi.f32.f32 %f1052, %f1051;
|
|
abs.f32 %f1053, %f1052;
|
|
setp.gt.f32 %p75, %f1053, 0f42FC0000;
|
|
mov.b32 %r306, %f1052;
|
|
and.b32 %r307, %r306, -2147483648;
|
|
or.b32 %r308, %r307, 1123811328;
|
|
mov.b32 %f1054, %r308;
|
|
selp.f32 %f1055, %f1054, %f1052, %p75;
|
|
mov.f32 %f1056, 0fBF317218;
|
|
fma.rn.f32 %f1057, %f1055, %f1056, %f1049;
|
|
mov.f32 %f1058, 0f3102E308;
|
|
fma.rn.f32 %f1059, %f1055, %f1058, %f1057;
|
|
mul.f32 %f1060, %f1059, 0f3FB8AA3B;
|
|
add.f32 %f1061, %f1055, 0f4B40007F;
|
|
mov.b32 %r309, %f1061;
|
|
shl.b32 %r310, %r309, 23;
|
|
mov.b32 %f1062, %r310;
|
|
ex2.approx.ftz.f32 %f1063, %f1060;
|
|
mul.f32 %f289, %f1063, %f1062;
|
|
setp.eq.f32 %p76, %f289, 0f7F800000;
|
|
mov.f32 %f1862, 0f7F800000;
|
|
@%p76 bra $L__BB0_62;
|
|
|
|
fma.rn.f32 %f1862, %f289, %f288, %f289;
|
|
|
|
$L__BB0_62:
|
|
setp.lt.f32 %p77, %f1797, 0f00000000;
|
|
setp.eq.f32 %p78, %f286, 0f3F800000;
|
|
and.pred %p4, %p77, %p78;
|
|
setp.eq.f32 %p79, %f1797, 0f00000000;
|
|
@%p79 bra $L__BB0_66;
|
|
bra.uni $L__BB0_63;
|
|
|
|
$L__BB0_66:
|
|
add.f32 %f1068, %f1797, %f1797;
|
|
selp.f32 %f1864, %f1068, 0f00000000, %p78;
|
|
bra.uni $L__BB0_67;
|
|
|
|
$L__BB0_63:
|
|
mov.b32 %r311, %f1862;
|
|
xor.b32 %r312, %r311, -2147483648;
|
|
mov.b32 %f1064, %r312;
|
|
selp.f32 %f1864, %f1064, %f1862, %p4;
|
|
setp.geu.f32 %p80, %f1797, 0f00000000;
|
|
@%p80 bra $L__BB0_67;
|
|
|
|
mov.f32 %f1065, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1066, %f1065;
|
|
setp.eq.f32 %p81, %f1066, 0f3EE66666;
|
|
@%p81 bra $L__BB0_67;
|
|
|
|
mov.f32 %f1864, 0f7FFFFFFF;
|
|
|
|
$L__BB0_67:
|
|
add.f32 %f1069, %f287, 0f3EE66666;
|
|
mov.b32 %r313, %f1069;
|
|
setp.lt.s32 %p83, %r313, 2139095040;
|
|
@%p83 bra $L__BB0_72;
|
|
|
|
setp.gtu.f32 %p84, %f287, 0f7F800000;
|
|
@%p84 bra $L__BB0_71;
|
|
bra.uni $L__BB0_69;
|
|
|
|
$L__BB0_71:
|
|
add.f32 %f1864, %f1797, 0f3EE66666;
|
|
bra.uni $L__BB0_72;
|
|
|
|
$L__BB0_69:
|
|
setp.neu.f32 %p85, %f287, 0f7F800000;
|
|
@%p85 bra $L__BB0_72;
|
|
|
|
selp.f32 %f1864, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_72:
|
|
setp.eq.f32 %p86, %f1797, 0f3F800000;
|
|
selp.f32 %f298, 0f3F800000, %f1864, %p86;
|
|
abs.f32 %f299, %f1798;
|
|
setp.lt.f32 %p87, %f299, 0f00800000;
|
|
mul.f32 %f1071, %f299, 0f4B800000;
|
|
selp.f32 %f1072, %f1071, %f299, %p87;
|
|
selp.f32 %f1073, 0fC3170000, 0fC2FE0000, %p87;
|
|
mov.b32 %r314, %f1072;
|
|
and.b32 %r315, %r314, 8388607;
|
|
or.b32 %r316, %r315, 1065353216;
|
|
mov.b32 %f1074, %r316;
|
|
shr.u32 %r317, %r314, 23;
|
|
cvt.rn.f32.u32 %f1075, %r317;
|
|
add.f32 %f1076, %f1073, %f1075;
|
|
setp.gt.f32 %p88, %f1074, 0f3FB504F3;
|
|
mul.f32 %f1077, %f1074, 0f3F000000;
|
|
add.f32 %f1078, %f1076, 0f3F800000;
|
|
selp.f32 %f1079, %f1078, %f1076, %p88;
|
|
selp.f32 %f1080, %f1077, %f1074, %p88;
|
|
add.f32 %f1081, %f1080, 0fBF800000;
|
|
add.f32 %f1082, %f1080, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1083, %f1082;
|
|
add.f32 %f1084, %f1081, %f1081;
|
|
mul.f32 %f1085, %f1084, %f1083;
|
|
mul.f32 %f1086, %f1085, %f1085;
|
|
mov.f32 %f1087, 0f3C4CAF63;
|
|
mov.f32 %f1088, 0f3B18F0FE;
|
|
fma.rn.f32 %f1089, %f1088, %f1086, %f1087;
|
|
mov.f32 %f1090, 0f3DAAAABD;
|
|
fma.rn.f32 %f1091, %f1089, %f1086, %f1090;
|
|
mul.rn.f32 %f1092, %f1091, %f1086;
|
|
mul.rn.f32 %f1093, %f1092, %f1085;
|
|
sub.f32 %f1094, %f1081, %f1085;
|
|
add.f32 %f1095, %f1094, %f1094;
|
|
neg.f32 %f1096, %f1085;
|
|
fma.rn.f32 %f1097, %f1096, %f1081, %f1095;
|
|
mul.rn.f32 %f1098, %f1083, %f1097;
|
|
add.f32 %f1099, %f1093, %f1085;
|
|
sub.f32 %f1100, %f1085, %f1099;
|
|
add.f32 %f1101, %f1093, %f1100;
|
|
add.f32 %f1102, %f1098, %f1101;
|
|
add.f32 %f1103, %f1099, %f1102;
|
|
sub.f32 %f1104, %f1099, %f1103;
|
|
add.f32 %f1105, %f1102, %f1104;
|
|
mov.f32 %f1106, 0f3F317200;
|
|
mul.rn.f32 %f1107, %f1079, %f1106;
|
|
mov.f32 %f1108, 0f35BFBE8E;
|
|
mul.rn.f32 %f1109, %f1079, %f1108;
|
|
add.f32 %f1110, %f1107, %f1103;
|
|
sub.f32 %f1111, %f1107, %f1110;
|
|
add.f32 %f1112, %f1103, %f1111;
|
|
add.f32 %f1113, %f1105, %f1112;
|
|
add.f32 %f1114, %f1109, %f1113;
|
|
add.f32 %f1115, %f1110, %f1114;
|
|
sub.f32 %f1116, %f1110, %f1115;
|
|
add.f32 %f1117, %f1114, %f1116;
|
|
mov.f32 %f1118, 0f3EE66666;
|
|
mul.rn.f32 %f1119, %f1118, %f1115;
|
|
neg.f32 %f1120, %f1119;
|
|
fma.rn.f32 %f1121, %f1118, %f1115, %f1120;
|
|
fma.rn.f32 %f1122, %f1118, %f1117, %f1121;
|
|
mov.f32 %f1123, 0f00000000;
|
|
fma.rn.f32 %f1124, %f1123, %f1115, %f1122;
|
|
add.rn.f32 %f1125, %f1119, %f1124;
|
|
neg.f32 %f1126, %f1125;
|
|
add.rn.f32 %f1127, %f1119, %f1126;
|
|
add.rn.f32 %f1128, %f1127, %f1124;
|
|
mov.b32 %r318, %f1125;
|
|
setp.eq.s32 %p89, %r318, 1118925336;
|
|
add.s32 %r319, %r318, -1;
|
|
mov.b32 %f1129, %r319;
|
|
add.f32 %f1130, %f1128, 0f37000000;
|
|
selp.f32 %f300, %f1130, %f1128, %p89;
|
|
selp.f32 %f1131, %f1129, %f1125, %p89;
|
|
mov.f32 %f1132, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1133, %f1131, %f1132;
|
|
cvt.rzi.f32.f32 %f1134, %f1133;
|
|
abs.f32 %f1135, %f1134;
|
|
setp.gt.f32 %p90, %f1135, 0f42FC0000;
|
|
mov.b32 %r320, %f1134;
|
|
and.b32 %r321, %r320, -2147483648;
|
|
or.b32 %r322, %r321, 1123811328;
|
|
mov.b32 %f1136, %r322;
|
|
selp.f32 %f1137, %f1136, %f1134, %p90;
|
|
mov.f32 %f1138, 0fBF317218;
|
|
fma.rn.f32 %f1139, %f1137, %f1138, %f1131;
|
|
mov.f32 %f1140, 0f3102E308;
|
|
fma.rn.f32 %f1141, %f1137, %f1140, %f1139;
|
|
mul.f32 %f1142, %f1141, 0f3FB8AA3B;
|
|
add.f32 %f1143, %f1137, 0f4B40007F;
|
|
mov.b32 %r323, %f1143;
|
|
shl.b32 %r324, %r323, 23;
|
|
mov.b32 %f1144, %r324;
|
|
ex2.approx.ftz.f32 %f1145, %f1142;
|
|
mul.f32 %f301, %f1145, %f1144;
|
|
setp.eq.f32 %p91, %f301, 0f7F800000;
|
|
mov.f32 %f1865, 0f7F800000;
|
|
@%p91 bra $L__BB0_74;
|
|
|
|
fma.rn.f32 %f1865, %f301, %f300, %f301;
|
|
|
|
$L__BB0_74:
|
|
setp.lt.f32 %p92, %f1798, 0f00000000;
|
|
and.pred %p5, %p92, %p78;
|
|
setp.eq.f32 %p94, %f1798, 0f00000000;
|
|
@%p94 bra $L__BB0_78;
|
|
bra.uni $L__BB0_75;
|
|
|
|
$L__BB0_78:
|
|
add.f32 %f1150, %f1798, %f1798;
|
|
selp.f32 %f1867, %f1150, 0f00000000, %p78;
|
|
bra.uni $L__BB0_79;
|
|
|
|
$L__BB0_75:
|
|
mov.b32 %r325, %f1865;
|
|
xor.b32 %r326, %r325, -2147483648;
|
|
mov.b32 %f1146, %r326;
|
|
selp.f32 %f1867, %f1146, %f1865, %p5;
|
|
setp.geu.f32 %p95, %f1798, 0f00000000;
|
|
@%p95 bra $L__BB0_79;
|
|
|
|
mov.f32 %f1147, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1148, %f1147;
|
|
setp.eq.f32 %p96, %f1148, 0f3EE66666;
|
|
@%p96 bra $L__BB0_79;
|
|
|
|
mov.f32 %f1867, 0f7FFFFFFF;
|
|
|
|
$L__BB0_79:
|
|
add.f32 %f1151, %f299, 0f3EE66666;
|
|
mov.b32 %r327, %f1151;
|
|
setp.lt.s32 %p98, %r327, 2139095040;
|
|
@%p98 bra $L__BB0_84;
|
|
|
|
setp.gtu.f32 %p99, %f299, 0f7F800000;
|
|
@%p99 bra $L__BB0_83;
|
|
bra.uni $L__BB0_81;
|
|
|
|
$L__BB0_83:
|
|
add.f32 %f1867, %f1798, 0f3EE66666;
|
|
bra.uni $L__BB0_84;
|
|
|
|
$L__BB0_81:
|
|
setp.neu.f32 %p100, %f299, 0f7F800000;
|
|
@%p100 bra $L__BB0_84;
|
|
|
|
selp.f32 %f1867, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_84:
|
|
setp.eq.f32 %p101, %f1798, 0f3F800000;
|
|
selp.f32 %f310, 0f3F800000, %f1867, %p101;
|
|
abs.f32 %f311, %f1799;
|
|
setp.lt.f32 %p102, %f311, 0f00800000;
|
|
mul.f32 %f1153, %f311, 0f4B800000;
|
|
selp.f32 %f1154, %f1153, %f311, %p102;
|
|
selp.f32 %f1155, 0fC3170000, 0fC2FE0000, %p102;
|
|
mov.b32 %r328, %f1154;
|
|
and.b32 %r329, %r328, 8388607;
|
|
or.b32 %r330, %r329, 1065353216;
|
|
mov.b32 %f1156, %r330;
|
|
shr.u32 %r331, %r328, 23;
|
|
cvt.rn.f32.u32 %f1157, %r331;
|
|
add.f32 %f1158, %f1155, %f1157;
|
|
setp.gt.f32 %p103, %f1156, 0f3FB504F3;
|
|
mul.f32 %f1159, %f1156, 0f3F000000;
|
|
add.f32 %f1160, %f1158, 0f3F800000;
|
|
selp.f32 %f1161, %f1160, %f1158, %p103;
|
|
selp.f32 %f1162, %f1159, %f1156, %p103;
|
|
add.f32 %f1163, %f1162, 0fBF800000;
|
|
add.f32 %f1164, %f1162, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1165, %f1164;
|
|
add.f32 %f1166, %f1163, %f1163;
|
|
mul.f32 %f1167, %f1166, %f1165;
|
|
mul.f32 %f1168, %f1167, %f1167;
|
|
mov.f32 %f1169, 0f3C4CAF63;
|
|
mov.f32 %f1170, 0f3B18F0FE;
|
|
fma.rn.f32 %f1171, %f1170, %f1168, %f1169;
|
|
mov.f32 %f1172, 0f3DAAAABD;
|
|
fma.rn.f32 %f1173, %f1171, %f1168, %f1172;
|
|
mul.rn.f32 %f1174, %f1173, %f1168;
|
|
mul.rn.f32 %f1175, %f1174, %f1167;
|
|
sub.f32 %f1176, %f1163, %f1167;
|
|
add.f32 %f1177, %f1176, %f1176;
|
|
neg.f32 %f1178, %f1167;
|
|
fma.rn.f32 %f1179, %f1178, %f1163, %f1177;
|
|
mul.rn.f32 %f1180, %f1165, %f1179;
|
|
add.f32 %f1181, %f1175, %f1167;
|
|
sub.f32 %f1182, %f1167, %f1181;
|
|
add.f32 %f1183, %f1175, %f1182;
|
|
add.f32 %f1184, %f1180, %f1183;
|
|
add.f32 %f1185, %f1181, %f1184;
|
|
sub.f32 %f1186, %f1181, %f1185;
|
|
add.f32 %f1187, %f1184, %f1186;
|
|
mov.f32 %f1188, 0f3F317200;
|
|
mul.rn.f32 %f1189, %f1161, %f1188;
|
|
mov.f32 %f1190, 0f35BFBE8E;
|
|
mul.rn.f32 %f1191, %f1161, %f1190;
|
|
add.f32 %f1192, %f1189, %f1185;
|
|
sub.f32 %f1193, %f1189, %f1192;
|
|
add.f32 %f1194, %f1185, %f1193;
|
|
add.f32 %f1195, %f1187, %f1194;
|
|
add.f32 %f1196, %f1191, %f1195;
|
|
add.f32 %f1197, %f1192, %f1196;
|
|
sub.f32 %f1198, %f1192, %f1197;
|
|
add.f32 %f1199, %f1196, %f1198;
|
|
mov.f32 %f1200, 0f3EE66666;
|
|
mul.rn.f32 %f1201, %f1200, %f1197;
|
|
neg.f32 %f1202, %f1201;
|
|
fma.rn.f32 %f1203, %f1200, %f1197, %f1202;
|
|
fma.rn.f32 %f1204, %f1200, %f1199, %f1203;
|
|
mov.f32 %f1205, 0f00000000;
|
|
fma.rn.f32 %f1206, %f1205, %f1197, %f1204;
|
|
add.rn.f32 %f1207, %f1201, %f1206;
|
|
neg.f32 %f1208, %f1207;
|
|
add.rn.f32 %f1209, %f1201, %f1208;
|
|
add.rn.f32 %f1210, %f1209, %f1206;
|
|
mov.b32 %r332, %f1207;
|
|
setp.eq.s32 %p104, %r332, 1118925336;
|
|
add.s32 %r333, %r332, -1;
|
|
mov.b32 %f1211, %r333;
|
|
add.f32 %f1212, %f1210, 0f37000000;
|
|
selp.f32 %f312, %f1212, %f1210, %p104;
|
|
selp.f32 %f1213, %f1211, %f1207, %p104;
|
|
mov.f32 %f1214, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1215, %f1213, %f1214;
|
|
cvt.rzi.f32.f32 %f1216, %f1215;
|
|
abs.f32 %f1217, %f1216;
|
|
setp.gt.f32 %p105, %f1217, 0f42FC0000;
|
|
mov.b32 %r334, %f1216;
|
|
and.b32 %r335, %r334, -2147483648;
|
|
or.b32 %r336, %r335, 1123811328;
|
|
mov.b32 %f1218, %r336;
|
|
selp.f32 %f1219, %f1218, %f1216, %p105;
|
|
mov.f32 %f1220, 0fBF317218;
|
|
fma.rn.f32 %f1221, %f1219, %f1220, %f1213;
|
|
mov.f32 %f1222, 0f3102E308;
|
|
fma.rn.f32 %f1223, %f1219, %f1222, %f1221;
|
|
mul.f32 %f1224, %f1223, 0f3FB8AA3B;
|
|
add.f32 %f1225, %f1219, 0f4B40007F;
|
|
mov.b32 %r337, %f1225;
|
|
shl.b32 %r338, %r337, 23;
|
|
mov.b32 %f1226, %r338;
|
|
ex2.approx.ftz.f32 %f1227, %f1224;
|
|
mul.f32 %f313, %f1227, %f1226;
|
|
setp.eq.f32 %p106, %f313, 0f7F800000;
|
|
mov.f32 %f1868, 0f7F800000;
|
|
@%p106 bra $L__BB0_86;
|
|
|
|
fma.rn.f32 %f1868, %f313, %f312, %f313;
|
|
|
|
$L__BB0_86:
|
|
setp.lt.f32 %p107, %f1799, 0f00000000;
|
|
and.pred %p6, %p107, %p78;
|
|
setp.eq.f32 %p109, %f1799, 0f00000000;
|
|
@%p109 bra $L__BB0_90;
|
|
bra.uni $L__BB0_87;
|
|
|
|
$L__BB0_90:
|
|
add.f32 %f1232, %f1799, %f1799;
|
|
selp.f32 %f1870, %f1232, 0f00000000, %p78;
|
|
bra.uni $L__BB0_91;
|
|
|
|
$L__BB0_87:
|
|
mov.b32 %r339, %f1868;
|
|
xor.b32 %r340, %r339, -2147483648;
|
|
mov.b32 %f1228, %r340;
|
|
selp.f32 %f1870, %f1228, %f1868, %p6;
|
|
setp.geu.f32 %p110, %f1799, 0f00000000;
|
|
@%p110 bra $L__BB0_91;
|
|
|
|
mov.f32 %f1229, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f1230, %f1229;
|
|
setp.eq.f32 %p111, %f1230, 0f3EE66666;
|
|
@%p111 bra $L__BB0_91;
|
|
|
|
mov.f32 %f1870, 0f7FFFFFFF;
|
|
|
|
$L__BB0_91:
|
|
add.f32 %f1233, %f311, 0f3EE66666;
|
|
mov.b32 %r341, %f1233;
|
|
setp.lt.s32 %p113, %r341, 2139095040;
|
|
@%p113 bra $L__BB0_96;
|
|
|
|
setp.gtu.f32 %p114, %f311, 0f7F800000;
|
|
@%p114 bra $L__BB0_95;
|
|
bra.uni $L__BB0_93;
|
|
|
|
$L__BB0_95:
|
|
add.f32 %f1870, %f1799, 0f3EE66666;
|
|
bra.uni $L__BB0_96;
|
|
|
|
$L__BB0_93:
|
|
setp.neu.f32 %p115, %f311, 0f7F800000;
|
|
@%p115 bra $L__BB0_96;
|
|
|
|
selp.f32 %f1870, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_96:
|
|
setp.eq.f32 %p116, %f1799, 0f3F800000;
|
|
mov.f32 %f1235, 0f3F800000;
|
|
selp.f32 %f1236, 0f3F800000, %f1870, %p116;
|
|
ld.const.u64 %rd46, [params+144];
|
|
cvta.to.global.u64 %rd9, %rd46;
|
|
ld.const.u32 %r342, [params+136];
|
|
mad.lo.s32 %r343, %r342, %r4, %r3;
|
|
cvt.u64.u32 %rd10, %r343;
|
|
min.f32 %f1237, %f298, %f1235;
|
|
mov.f32 %f1238, 0f00000000;
|
|
max.f32 %f322, %f1238, %f1237;
|
|
min.f32 %f1239, %f310, %f1235;
|
|
max.f32 %f323, %f1238, %f1239;
|
|
min.f32 %f1240, %f1236, %f1235;
|
|
max.f32 %f324, %f1238, %f1240;
|
|
mov.f32 %f1241, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1242, %f1241;
|
|
add.f32 %f1243, %f1242, %f1242;
|
|
mov.f32 %f1244, 0f3ED55555;
|
|
sub.f32 %f1245, %f1244, %f1243;
|
|
abs.f32 %f325, %f1245;
|
|
abs.f32 %f326, %f322;
|
|
setp.lt.f32 %p117, %f326, 0f00800000;
|
|
mul.f32 %f1246, %f326, 0f4B800000;
|
|
selp.f32 %f1247, %f1246, %f326, %p117;
|
|
selp.f32 %f1248, 0fC3170000, 0fC2FE0000, %p117;
|
|
mov.b32 %r344, %f1247;
|
|
and.b32 %r345, %r344, 8388607;
|
|
or.b32 %r346, %r345, 1065353216;
|
|
mov.b32 %f1249, %r346;
|
|
shr.u32 %r347, %r344, 23;
|
|
cvt.rn.f32.u32 %f1250, %r347;
|
|
add.f32 %f1251, %f1248, %f1250;
|
|
setp.gt.f32 %p118, %f1249, 0f3FB504F3;
|
|
mul.f32 %f1252, %f1249, 0f3F000000;
|
|
add.f32 %f1253, %f1251, 0f3F800000;
|
|
selp.f32 %f1254, %f1253, %f1251, %p118;
|
|
selp.f32 %f1255, %f1252, %f1249, %p118;
|
|
add.f32 %f1256, %f1255, 0fBF800000;
|
|
add.f32 %f1257, %f1255, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1258, %f1257;
|
|
add.f32 %f1259, %f1256, %f1256;
|
|
mul.f32 %f1260, %f1259, %f1258;
|
|
mul.f32 %f1261, %f1260, %f1260;
|
|
mov.f32 %f1262, 0f3C4CAF63;
|
|
mov.f32 %f1263, 0f3B18F0FE;
|
|
fma.rn.f32 %f1264, %f1263, %f1261, %f1262;
|
|
mov.f32 %f1265, 0f3DAAAABD;
|
|
fma.rn.f32 %f1266, %f1264, %f1261, %f1265;
|
|
mul.rn.f32 %f1267, %f1266, %f1261;
|
|
mul.rn.f32 %f1268, %f1267, %f1260;
|
|
sub.f32 %f1269, %f1256, %f1260;
|
|
add.f32 %f1270, %f1269, %f1269;
|
|
neg.f32 %f1271, %f1260;
|
|
fma.rn.f32 %f1272, %f1271, %f1256, %f1270;
|
|
mul.rn.f32 %f1273, %f1258, %f1272;
|
|
add.f32 %f1274, %f1268, %f1260;
|
|
sub.f32 %f1275, %f1260, %f1274;
|
|
add.f32 %f1276, %f1268, %f1275;
|
|
add.f32 %f1277, %f1273, %f1276;
|
|
add.f32 %f1278, %f1274, %f1277;
|
|
sub.f32 %f1279, %f1274, %f1278;
|
|
add.f32 %f1280, %f1277, %f1279;
|
|
mov.f32 %f1281, 0f3F317200;
|
|
mul.rn.f32 %f1282, %f1254, %f1281;
|
|
mov.f32 %f1283, 0f35BFBE8E;
|
|
mul.rn.f32 %f1284, %f1254, %f1283;
|
|
add.f32 %f1285, %f1282, %f1278;
|
|
sub.f32 %f1286, %f1282, %f1285;
|
|
add.f32 %f1287, %f1278, %f1286;
|
|
add.f32 %f1288, %f1280, %f1287;
|
|
add.f32 %f1289, %f1284, %f1288;
|
|
add.f32 %f1290, %f1285, %f1289;
|
|
sub.f32 %f1291, %f1285, %f1290;
|
|
add.f32 %f1292, %f1289, %f1291;
|
|
mul.rn.f32 %f1293, %f1244, %f1290;
|
|
neg.f32 %f1294, %f1293;
|
|
fma.rn.f32 %f1295, %f1244, %f1290, %f1294;
|
|
fma.rn.f32 %f1296, %f1244, %f1292, %f1295;
|
|
fma.rn.f32 %f1297, %f1238, %f1290, %f1296;
|
|
add.rn.f32 %f1298, %f1293, %f1297;
|
|
neg.f32 %f1299, %f1298;
|
|
add.rn.f32 %f1300, %f1293, %f1299;
|
|
add.rn.f32 %f1301, %f1300, %f1297;
|
|
mov.b32 %r348, %f1298;
|
|
setp.eq.s32 %p119, %r348, 1118925336;
|
|
add.s32 %r349, %r348, -1;
|
|
mov.b32 %f1302, %r349;
|
|
add.f32 %f1303, %f1301, 0f37000000;
|
|
selp.f32 %f327, %f1303, %f1301, %p119;
|
|
selp.f32 %f1304, %f1302, %f1298, %p119;
|
|
mov.f32 %f1305, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1306, %f1304, %f1305;
|
|
cvt.rzi.f32.f32 %f1307, %f1306;
|
|
abs.f32 %f1308, %f1307;
|
|
setp.gt.f32 %p120, %f1308, 0f42FC0000;
|
|
mov.b32 %r350, %f1307;
|
|
and.b32 %r351, %r350, -2147483648;
|
|
or.b32 %r352, %r351, 1123811328;
|
|
mov.b32 %f1309, %r352;
|
|
selp.f32 %f1310, %f1309, %f1307, %p120;
|
|
mov.f32 %f1311, 0fBF317218;
|
|
fma.rn.f32 %f1312, %f1310, %f1311, %f1304;
|
|
mov.f32 %f1313, 0f3102E308;
|
|
fma.rn.f32 %f1314, %f1310, %f1313, %f1312;
|
|
mul.f32 %f1315, %f1314, 0f3FB8AA3B;
|
|
add.f32 %f1316, %f1310, 0f4B40007F;
|
|
mov.b32 %r353, %f1316;
|
|
shl.b32 %r354, %r353, 23;
|
|
mov.b32 %f1317, %r354;
|
|
ex2.approx.ftz.f32 %f1318, %f1315;
|
|
mul.f32 %f328, %f1318, %f1317;
|
|
setp.eq.f32 %p121, %f328, 0f7F800000;
|
|
mov.f32 %f1871, 0f7F800000;
|
|
@%p121 bra $L__BB0_98;
|
|
|
|
fma.rn.f32 %f1871, %f328, %f327, %f328;
|
|
|
|
$L__BB0_98:
|
|
setp.lt.f32 %p122, %f322, 0f00000000;
|
|
setp.eq.f32 %p123, %f325, 0f3F800000;
|
|
and.pred %p7, %p122, %p123;
|
|
setp.eq.f32 %p124, %f322, 0f00000000;
|
|
@%p124 bra $L__BB0_102;
|
|
bra.uni $L__BB0_99;
|
|
|
|
$L__BB0_102:
|
|
add.f32 %f1323, %f322, %f322;
|
|
selp.f32 %f1873, %f1323, 0f00000000, %p123;
|
|
bra.uni $L__BB0_103;
|
|
|
|
$L__BB0_99:
|
|
mov.b32 %r355, %f1871;
|
|
xor.b32 %r356, %r355, -2147483648;
|
|
mov.b32 %f1319, %r356;
|
|
selp.f32 %f1873, %f1319, %f1871, %p7;
|
|
setp.geu.f32 %p125, %f322, 0f00000000;
|
|
@%p125 bra $L__BB0_103;
|
|
|
|
mov.f32 %f1320, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1321, %f1320;
|
|
setp.eq.f32 %p126, %f1321, 0f3ED55555;
|
|
@%p126 bra $L__BB0_103;
|
|
|
|
mov.f32 %f1873, 0f7FFFFFFF;
|
|
|
|
$L__BB0_103:
|
|
add.f32 %f1324, %f326, 0f3ED55555;
|
|
mov.b32 %r357, %f1324;
|
|
setp.lt.s32 %p128, %r357, 2139095040;
|
|
@%p128 bra $L__BB0_108;
|
|
|
|
setp.gtu.f32 %p129, %f326, 0f7F800000;
|
|
@%p129 bra $L__BB0_107;
|
|
bra.uni $L__BB0_105;
|
|
|
|
$L__BB0_107:
|
|
add.f32 %f1873, %f322, 0f3ED55555;
|
|
bra.uni $L__BB0_108;
|
|
|
|
$L__BB0_105:
|
|
setp.neu.f32 %p130, %f326, 0f7F800000;
|
|
@%p130 bra $L__BB0_108;
|
|
|
|
selp.f32 %f1873, 0fFF800000, 0f7F800000, %p7;
|
|
|
|
$L__BB0_108:
|
|
abs.f32 %f337, %f323;
|
|
setp.lt.f32 %p131, %f337, 0f00800000;
|
|
mul.f32 %f1326, %f337, 0f4B800000;
|
|
selp.f32 %f1327, %f1326, %f337, %p131;
|
|
selp.f32 %f1328, 0fC3170000, 0fC2FE0000, %p131;
|
|
mov.b32 %r358, %f1327;
|
|
and.b32 %r359, %r358, 8388607;
|
|
or.b32 %r360, %r359, 1065353216;
|
|
mov.b32 %f1329, %r360;
|
|
shr.u32 %r361, %r358, 23;
|
|
cvt.rn.f32.u32 %f1330, %r361;
|
|
add.f32 %f1331, %f1328, %f1330;
|
|
setp.gt.f32 %p132, %f1329, 0f3FB504F3;
|
|
mul.f32 %f1332, %f1329, 0f3F000000;
|
|
add.f32 %f1333, %f1331, 0f3F800000;
|
|
selp.f32 %f1334, %f1333, %f1331, %p132;
|
|
selp.f32 %f1335, %f1332, %f1329, %p132;
|
|
add.f32 %f1336, %f1335, 0fBF800000;
|
|
add.f32 %f1337, %f1335, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1338, %f1337;
|
|
add.f32 %f1339, %f1336, %f1336;
|
|
mul.f32 %f1340, %f1339, %f1338;
|
|
mul.f32 %f1341, %f1340, %f1340;
|
|
mov.f32 %f1342, 0f3C4CAF63;
|
|
mov.f32 %f1343, 0f3B18F0FE;
|
|
fma.rn.f32 %f1344, %f1343, %f1341, %f1342;
|
|
mov.f32 %f1345, 0f3DAAAABD;
|
|
fma.rn.f32 %f1346, %f1344, %f1341, %f1345;
|
|
mul.rn.f32 %f1347, %f1346, %f1341;
|
|
mul.rn.f32 %f1348, %f1347, %f1340;
|
|
sub.f32 %f1349, %f1336, %f1340;
|
|
add.f32 %f1350, %f1349, %f1349;
|
|
neg.f32 %f1351, %f1340;
|
|
fma.rn.f32 %f1352, %f1351, %f1336, %f1350;
|
|
mul.rn.f32 %f1353, %f1338, %f1352;
|
|
add.f32 %f1354, %f1348, %f1340;
|
|
sub.f32 %f1355, %f1340, %f1354;
|
|
add.f32 %f1356, %f1348, %f1355;
|
|
add.f32 %f1357, %f1353, %f1356;
|
|
add.f32 %f1358, %f1354, %f1357;
|
|
sub.f32 %f1359, %f1354, %f1358;
|
|
add.f32 %f1360, %f1357, %f1359;
|
|
mov.f32 %f1361, 0f3F317200;
|
|
mul.rn.f32 %f1362, %f1334, %f1361;
|
|
mov.f32 %f1363, 0f35BFBE8E;
|
|
mul.rn.f32 %f1364, %f1334, %f1363;
|
|
add.f32 %f1365, %f1362, %f1358;
|
|
sub.f32 %f1366, %f1362, %f1365;
|
|
add.f32 %f1367, %f1358, %f1366;
|
|
add.f32 %f1368, %f1360, %f1367;
|
|
add.f32 %f1369, %f1364, %f1368;
|
|
add.f32 %f1370, %f1365, %f1369;
|
|
sub.f32 %f1371, %f1365, %f1370;
|
|
add.f32 %f1372, %f1369, %f1371;
|
|
mov.f32 %f1373, 0f3ED55555;
|
|
mul.rn.f32 %f1374, %f1373, %f1370;
|
|
neg.f32 %f1375, %f1374;
|
|
fma.rn.f32 %f1376, %f1373, %f1370, %f1375;
|
|
fma.rn.f32 %f1377, %f1373, %f1372, %f1376;
|
|
mov.f32 %f1378, 0f00000000;
|
|
fma.rn.f32 %f1379, %f1378, %f1370, %f1377;
|
|
add.rn.f32 %f1380, %f1374, %f1379;
|
|
neg.f32 %f1381, %f1380;
|
|
add.rn.f32 %f1382, %f1374, %f1381;
|
|
add.rn.f32 %f1383, %f1382, %f1379;
|
|
mov.b32 %r362, %f1380;
|
|
setp.eq.s32 %p133, %r362, 1118925336;
|
|
add.s32 %r363, %r362, -1;
|
|
mov.b32 %f1384, %r363;
|
|
add.f32 %f1385, %f1383, 0f37000000;
|
|
selp.f32 %f338, %f1385, %f1383, %p133;
|
|
selp.f32 %f1386, %f1384, %f1380, %p133;
|
|
mov.f32 %f1387, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1388, %f1386, %f1387;
|
|
cvt.rzi.f32.f32 %f1389, %f1388;
|
|
abs.f32 %f1390, %f1389;
|
|
setp.gt.f32 %p134, %f1390, 0f42FC0000;
|
|
mov.b32 %r364, %f1389;
|
|
and.b32 %r365, %r364, -2147483648;
|
|
or.b32 %r366, %r365, 1123811328;
|
|
mov.b32 %f1391, %r366;
|
|
selp.f32 %f1392, %f1391, %f1389, %p134;
|
|
mov.f32 %f1393, 0fBF317218;
|
|
fma.rn.f32 %f1394, %f1392, %f1393, %f1386;
|
|
mov.f32 %f1395, 0f3102E308;
|
|
fma.rn.f32 %f1396, %f1392, %f1395, %f1394;
|
|
mul.f32 %f1397, %f1396, 0f3FB8AA3B;
|
|
add.f32 %f1398, %f1392, 0f4B40007F;
|
|
mov.b32 %r367, %f1398;
|
|
shl.b32 %r368, %r367, 23;
|
|
mov.b32 %f1399, %r368;
|
|
ex2.approx.ftz.f32 %f1400, %f1397;
|
|
mul.f32 %f339, %f1400, %f1399;
|
|
setp.eq.f32 %p135, %f339, 0f7F800000;
|
|
mov.f32 %f1874, 0f7F800000;
|
|
@%p135 bra $L__BB0_110;
|
|
|
|
fma.rn.f32 %f1874, %f339, %f338, %f339;
|
|
|
|
$L__BB0_110:
|
|
setp.lt.f32 %p136, %f323, 0f00000000;
|
|
and.pred %p8, %p136, %p123;
|
|
setp.eq.f32 %p138, %f323, 0f00000000;
|
|
@%p138 bra $L__BB0_114;
|
|
bra.uni $L__BB0_111;
|
|
|
|
$L__BB0_114:
|
|
add.f32 %f1405, %f323, %f323;
|
|
selp.f32 %f1876, %f1405, 0f00000000, %p123;
|
|
bra.uni $L__BB0_115;
|
|
|
|
$L__BB0_111:
|
|
mov.b32 %r369, %f1874;
|
|
xor.b32 %r370, %r369, -2147483648;
|
|
mov.b32 %f1401, %r370;
|
|
selp.f32 %f1876, %f1401, %f1874, %p8;
|
|
setp.geu.f32 %p139, %f323, 0f00000000;
|
|
@%p139 bra $L__BB0_115;
|
|
|
|
mov.f32 %f1402, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1403, %f1402;
|
|
setp.eq.f32 %p140, %f1403, 0f3ED55555;
|
|
@%p140 bra $L__BB0_115;
|
|
|
|
mov.f32 %f1876, 0f7FFFFFFF;
|
|
|
|
$L__BB0_115:
|
|
add.f32 %f1406, %f337, 0f3ED55555;
|
|
mov.b32 %r371, %f1406;
|
|
setp.lt.s32 %p142, %r371, 2139095040;
|
|
@%p142 bra $L__BB0_120;
|
|
|
|
setp.gtu.f32 %p143, %f337, 0f7F800000;
|
|
@%p143 bra $L__BB0_119;
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_119:
|
|
add.f32 %f1876, %f323, 0f3ED55555;
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_117:
|
|
setp.neu.f32 %p144, %f337, 0f7F800000;
|
|
@%p144 bra $L__BB0_120;
|
|
|
|
selp.f32 %f1876, 0fFF800000, 0f7F800000, %p8;
|
|
|
|
$L__BB0_120:
|
|
abs.f32 %f348, %f324;
|
|
setp.lt.f32 %p145, %f348, 0f00800000;
|
|
mul.f32 %f1408, %f348, 0f4B800000;
|
|
selp.f32 %f1409, %f1408, %f348, %p145;
|
|
selp.f32 %f1410, 0fC3170000, 0fC2FE0000, %p145;
|
|
mov.b32 %r372, %f1409;
|
|
and.b32 %r373, %r372, 8388607;
|
|
or.b32 %r374, %r373, 1065353216;
|
|
mov.b32 %f1411, %r374;
|
|
shr.u32 %r375, %r372, 23;
|
|
cvt.rn.f32.u32 %f1412, %r375;
|
|
add.f32 %f1413, %f1410, %f1412;
|
|
setp.gt.f32 %p146, %f1411, 0f3FB504F3;
|
|
mul.f32 %f1414, %f1411, 0f3F000000;
|
|
add.f32 %f1415, %f1413, 0f3F800000;
|
|
selp.f32 %f1416, %f1415, %f1413, %p146;
|
|
selp.f32 %f1417, %f1414, %f1411, %p146;
|
|
add.f32 %f1418, %f1417, 0fBF800000;
|
|
add.f32 %f1419, %f1417, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f1420, %f1419;
|
|
add.f32 %f1421, %f1418, %f1418;
|
|
mul.f32 %f1422, %f1421, %f1420;
|
|
mul.f32 %f1423, %f1422, %f1422;
|
|
mov.f32 %f1424, 0f3C4CAF63;
|
|
mov.f32 %f1425, 0f3B18F0FE;
|
|
fma.rn.f32 %f1426, %f1425, %f1423, %f1424;
|
|
mov.f32 %f1427, 0f3DAAAABD;
|
|
fma.rn.f32 %f1428, %f1426, %f1423, %f1427;
|
|
mul.rn.f32 %f1429, %f1428, %f1423;
|
|
mul.rn.f32 %f1430, %f1429, %f1422;
|
|
sub.f32 %f1431, %f1418, %f1422;
|
|
add.f32 %f1432, %f1431, %f1431;
|
|
neg.f32 %f1433, %f1422;
|
|
fma.rn.f32 %f1434, %f1433, %f1418, %f1432;
|
|
mul.rn.f32 %f1435, %f1420, %f1434;
|
|
add.f32 %f1436, %f1430, %f1422;
|
|
sub.f32 %f1437, %f1422, %f1436;
|
|
add.f32 %f1438, %f1430, %f1437;
|
|
add.f32 %f1439, %f1435, %f1438;
|
|
add.f32 %f1440, %f1436, %f1439;
|
|
sub.f32 %f1441, %f1436, %f1440;
|
|
add.f32 %f1442, %f1439, %f1441;
|
|
mov.f32 %f1443, 0f3F317200;
|
|
mul.rn.f32 %f1444, %f1416, %f1443;
|
|
mov.f32 %f1445, 0f35BFBE8E;
|
|
mul.rn.f32 %f1446, %f1416, %f1445;
|
|
add.f32 %f1447, %f1444, %f1440;
|
|
sub.f32 %f1448, %f1444, %f1447;
|
|
add.f32 %f1449, %f1440, %f1448;
|
|
add.f32 %f1450, %f1442, %f1449;
|
|
add.f32 %f1451, %f1446, %f1450;
|
|
add.f32 %f1452, %f1447, %f1451;
|
|
sub.f32 %f1453, %f1447, %f1452;
|
|
add.f32 %f1454, %f1451, %f1453;
|
|
mov.f32 %f1455, 0f3ED55555;
|
|
mul.rn.f32 %f1456, %f1455, %f1452;
|
|
neg.f32 %f1457, %f1456;
|
|
fma.rn.f32 %f1458, %f1455, %f1452, %f1457;
|
|
fma.rn.f32 %f1459, %f1455, %f1454, %f1458;
|
|
mov.f32 %f1460, 0f00000000;
|
|
fma.rn.f32 %f1461, %f1460, %f1452, %f1459;
|
|
add.rn.f32 %f1462, %f1456, %f1461;
|
|
neg.f32 %f1463, %f1462;
|
|
add.rn.f32 %f1464, %f1456, %f1463;
|
|
add.rn.f32 %f1465, %f1464, %f1461;
|
|
mov.b32 %r376, %f1462;
|
|
setp.eq.s32 %p147, %r376, 1118925336;
|
|
add.s32 %r377, %r376, -1;
|
|
mov.b32 %f1466, %r377;
|
|
add.f32 %f1467, %f1465, 0f37000000;
|
|
selp.f32 %f349, %f1467, %f1465, %p147;
|
|
selp.f32 %f1468, %f1466, %f1462, %p147;
|
|
mov.f32 %f1469, 0f3FB8AA3B;
|
|
mul.rn.f32 %f1470, %f1468, %f1469;
|
|
cvt.rzi.f32.f32 %f1471, %f1470;
|
|
abs.f32 %f1472, %f1471;
|
|
setp.gt.f32 %p148, %f1472, 0f42FC0000;
|
|
mov.b32 %r378, %f1471;
|
|
and.b32 %r379, %r378, -2147483648;
|
|
or.b32 %r380, %r379, 1123811328;
|
|
mov.b32 %f1473, %r380;
|
|
selp.f32 %f1474, %f1473, %f1471, %p148;
|
|
mov.f32 %f1475, 0fBF317218;
|
|
fma.rn.f32 %f1476, %f1474, %f1475, %f1468;
|
|
mov.f32 %f1477, 0f3102E308;
|
|
fma.rn.f32 %f1478, %f1474, %f1477, %f1476;
|
|
mul.f32 %f1479, %f1478, 0f3FB8AA3B;
|
|
add.f32 %f1480, %f1474, 0f4B40007F;
|
|
mov.b32 %r381, %f1480;
|
|
shl.b32 %r382, %r381, 23;
|
|
mov.b32 %f1481, %r382;
|
|
ex2.approx.ftz.f32 %f1482, %f1479;
|
|
mul.f32 %f350, %f1482, %f1481;
|
|
setp.eq.f32 %p149, %f350, 0f7F800000;
|
|
mov.f32 %f1877, 0f7F800000;
|
|
@%p149 bra $L__BB0_122;
|
|
|
|
fma.rn.f32 %f1877, %f350, %f349, %f350;
|
|
|
|
$L__BB0_122:
|
|
setp.lt.f32 %p150, %f324, 0f00000000;
|
|
and.pred %p9, %p150, %p123;
|
|
setp.eq.f32 %p152, %f324, 0f00000000;
|
|
@%p152 bra $L__BB0_126;
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_126:
|
|
add.f32 %f1487, %f324, %f324;
|
|
selp.f32 %f1879, %f1487, 0f00000000, %p123;
|
|
bra.uni $L__BB0_127;
|
|
|
|
$L__BB0_123:
|
|
mov.b32 %r383, %f1877;
|
|
xor.b32 %r384, %r383, -2147483648;
|
|
mov.b32 %f1483, %r384;
|
|
selp.f32 %f1879, %f1483, %f1877, %p9;
|
|
setp.geu.f32 %p153, %f324, 0f00000000;
|
|
@%p153 bra $L__BB0_127;
|
|
|
|
mov.f32 %f1484, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f1485, %f1484;
|
|
setp.eq.f32 %p154, %f1485, 0f3ED55555;
|
|
@%p154 bra $L__BB0_127;
|
|
|
|
mov.f32 %f1879, 0f7FFFFFFF;
|
|
|
|
$L__BB0_127:
|
|
add.f32 %f1488, %f348, 0f3ED55555;
|
|
mov.b32 %r385, %f1488;
|
|
setp.lt.s32 %p156, %r385, 2139095040;
|
|
@%p156 bra $L__BB0_132;
|
|
|
|
setp.gtu.f32 %p157, %f348, 0f7F800000;
|
|
@%p157 bra $L__BB0_131;
|
|
bra.uni $L__BB0_129;
|
|
|
|
$L__BB0_131:
|
|
add.f32 %f1879, %f324, 0f3ED55555;
|
|
bra.uni $L__BB0_132;
|
|
|
|
$L__BB0_129:
|
|
setp.neu.f32 %p158, %f348, 0f7F800000;
|
|
@%p158 bra $L__BB0_132;
|
|
|
|
selp.f32 %f1879, 0fFF800000, 0f7F800000, %p9;
|
|
|
|
$L__BB0_132:
|
|
fma.rn.f32 %f1489, %f1873, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p159, %f322, 0f3F800000;
|
|
mov.f32 %f1490, 0f3F800000;
|
|
selp.f32 %f1491, 0f3F7FFFFF, %f1489, %p159;
|
|
mul.f32 %f1492, %f322, 0f414EB852;
|
|
setp.lt.f32 %p160, %f322, 0f3B4D2E1C;
|
|
selp.f32 %f1493, %f1492, %f1491, %p160;
|
|
fma.rn.f32 %f1494, %f1876, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p161, %f323, 0f3F800000;
|
|
selp.f32 %f1495, 0f3F7FFFFF, %f1494, %p161;
|
|
mul.f32 %f1496, %f323, 0f414EB852;
|
|
setp.lt.f32 %p162, %f323, 0f3B4D2E1C;
|
|
selp.f32 %f1497, %f1496, %f1495, %p162;
|
|
fma.rn.f32 %f1498, %f1879, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p163, %f324, 0f3F800000;
|
|
selp.f32 %f1499, 0f3F7FFFFF, %f1498, %p163;
|
|
mul.f32 %f1500, %f324, 0f414EB852;
|
|
setp.lt.f32 %p164, %f324, 0f3B4D2E1C;
|
|
selp.f32 %f1501, %f1500, %f1499, %p164;
|
|
min.f32 %f1502, %f1493, %f1490;
|
|
mov.f32 %f1503, 0f00000000;
|
|
max.f32 %f1504, %f1503, %f1502;
|
|
mul.f32 %f1505, %f1504, 0f43800000;
|
|
cvt.rzi.u32.f32 %r386, %f1505;
|
|
min.u32 %r387, %r386, 255;
|
|
min.f32 %f1506, %f1497, %f1490;
|
|
max.f32 %f1507, %f1503, %f1506;
|
|
mul.f32 %f1508, %f1507, 0f43800000;
|
|
cvt.rzi.u32.f32 %r388, %f1508;
|
|
min.u32 %r389, %r388, 255;
|
|
min.f32 %f1509, %f1501, %f1490;
|
|
max.f32 %f1510, %f1503, %f1509;
|
|
mul.f32 %f1511, %f1510, 0f43800000;
|
|
cvt.rzi.u32.f32 %r390, %f1511;
|
|
min.u32 %r391, %r390, 255;
|
|
shl.b64 %rd47, %rd10, 2;
|
|
add.s64 %rd48, %rd9, %rd47;
|
|
cvt.u16.u32 %rs20, %r391;
|
|
cvt.u16.u32 %rs21, %r389;
|
|
cvt.u16.u32 %rs22, %r387;
|
|
mov.u16 %rs23, 255;
|
|
st.global.v4.u8 [%rd48], {%rs22, %rs21, %rs20, %rs23};
|
|
|
|
$L__BB0_133:
|
|
and.b32 %r392, %r447, 4;
|
|
setp.eq.s32 %p165, %r392, 0;
|
|
ld.const.u32 %r448, [params+108];
|
|
@%p165 bra $L__BB0_137;
|
|
|
|
setp.eq.s32 %p166, %r448, 0;
|
|
ld.const.u64 %rd49, [params+224];
|
|
cvta.to.global.u64 %rd50, %rd49;
|
|
ld.const.u32 %r393, [params+216];
|
|
mad.lo.s32 %r394, %r393, %r4, %r3;
|
|
mul.wide.u32 %rd51, %r394, 8;
|
|
add.s64 %rd11, %rd50, %rd51;
|
|
@%p166 bra $L__BB0_136;
|
|
|
|
ld.global.v4.u16 {%rs31, %rs32, %rs33, %rs34}, [%rd11];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1512, %rs31;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1513, %rs32;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1514, %rs33;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1515, %f1797, %f1512;
|
|
add.f32 %f1516, %f1798, %f1513;
|
|
add.f32 %f1517, %f1799, %f1514;
|
|
mov.f32 %f1518, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs29, %f1517;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs28, %f1516;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs27, %f1515;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f1518;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd11], {%rs27, %rs28, %rs29, %rs30};
|
|
bra.uni $L__BB0_137;
|
|
|
|
$L__BB0_136:
|
|
mov.f32 %f1522, 0f3F800000;
|
|
mov.u32 %r448, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f1522;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f1799;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs36, %f1798;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs35, %f1797;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd11], {%rs35, %rs36, %rs37, %rs38};
|
|
|
|
$L__BB0_137:
|
|
mul.f32 %f359, %f1800, 0f3F558750;
|
|
mul.f32 %f360, %f1801, 0f3F558750;
|
|
mul.f32 %f361, %f1802, 0f3F558750;
|
|
ld.const.u64 %rd52, [params+256];
|
|
cvta.to.global.u64 %rd53, %rd52;
|
|
ld.const.u32 %r396, [params+248];
|
|
mad.lo.s32 %r397, %r396, %r4, %r3;
|
|
mul.wide.u32 %rd54, %r397, 8;
|
|
add.s64 %rd12, %rd53, %rd54;
|
|
setp.eq.s32 %p167, %r448, 0;
|
|
@%p167 bra $L__BB0_139;
|
|
|
|
ld.global.v4.u16 {%rs46, %rs47, %rs48, %rs49}, [%rd12];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1523, %rs46;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1524, %rs47;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1525, %rs48;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1526, %f359, %f1523;
|
|
add.f32 %f1527, %f360, %f1524;
|
|
add.f32 %f1528, %f361, %f1525;
|
|
mov.f32 %f1529, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs44, %f1528;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs43, %f1527;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs42, %f1526;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs45, %f1529;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd12], {%rs42, %rs43, %rs44, %rs45};
|
|
bra.uni $L__BB0_140;
|
|
|
|
$L__BB0_139:
|
|
mov.f32 %f1533, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f1533;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f361;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs51, %f360;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs50, %f359;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd12], {%rs50, %rs51, %rs52, %rs53};
|
|
|
|
$L__BB0_140:
|
|
mul.f32 %f362, %f1803, 0f3FB8EBD1;
|
|
mul.f32 %f363, %f1804, 0f3FB8EBD1;
|
|
mul.f32 %f364, %f1805, 0f3FB8EBD1;
|
|
ld.const.u64 %rd55, [params+272];
|
|
cvta.to.global.u64 %rd56, %rd55;
|
|
ld.const.u32 %r398, [params+264];
|
|
mad.lo.s32 %r399, %r398, %r4, %r3;
|
|
mul.wide.u32 %rd57, %r399, 8;
|
|
add.s64 %rd13, %rd56, %rd57;
|
|
@%p167 bra $L__BB0_142;
|
|
|
|
ld.global.v4.u16 {%rs61, %rs62, %rs63, %rs64}, [%rd13];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1534, %rs61;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1535, %rs62;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1536, %rs63;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1537, %f362, %f1534;
|
|
add.f32 %f1538, %f363, %f1535;
|
|
add.f32 %f1539, %f364, %f1536;
|
|
mov.f32 %f1540, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs59, %f1539;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs58, %f1538;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs57, %f1537;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f1540;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd13], {%rs57, %rs58, %rs59, %rs60};
|
|
bra.uni $L__BB0_143;
|
|
|
|
$L__BB0_142:
|
|
mov.f32 %f1544, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1544;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f364;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs66, %f363;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs65, %f362;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd13], {%rs65, %rs66, %rs67, %rs68};
|
|
|
|
$L__BB0_143:
|
|
mul.f32 %f365, %f1806, 0f3FB8EBD1;
|
|
mul.f32 %f366, %f1807, 0f3FB8EBD1;
|
|
mul.f32 %f367, %f1808, 0f3FB8EBD1;
|
|
ld.const.u64 %rd58, [params+288];
|
|
cvta.to.global.u64 %rd59, %rd58;
|
|
ld.const.u32 %r400, [params+280];
|
|
mad.lo.s32 %r401, %r400, %r4, %r3;
|
|
mul.wide.u32 %rd60, %r401, 8;
|
|
add.s64 %rd14, %rd59, %rd60;
|
|
@%p167 bra $L__BB0_145;
|
|
|
|
ld.global.v4.u16 {%rs76, %rs77, %rs78, %rs79}, [%rd14];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1545, %rs76;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1546, %rs77;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1547, %rs78;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1548, %f365, %f1545;
|
|
add.f32 %f1549, %f366, %f1546;
|
|
add.f32 %f1550, %f367, %f1547;
|
|
mov.f32 %f1551, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs74, %f1550;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs73, %f1549;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs72, %f1548;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f1551;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd14], {%rs72, %rs73, %rs74, %rs75};
|
|
bra.uni $L__BB0_146;
|
|
|
|
$L__BB0_145:
|
|
mov.f32 %f1555, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1555;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f367;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs81, %f366;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs80, %f365;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd14], {%rs80, %rs81, %rs82, %rs83};
|
|
|
|
$L__BB0_146:
|
|
mul.f32 %f368, %f1809, 0f3FB8EBD1;
|
|
mul.f32 %f369, %f1810, 0f3FB8EBD1;
|
|
mul.f32 %f370, %f1811, 0f3FB8EBD1;
|
|
ld.const.u64 %rd61, [params+304];
|
|
cvta.to.global.u64 %rd62, %rd61;
|
|
ld.const.u32 %r402, [params+296];
|
|
mad.lo.s32 %r403, %r402, %r4, %r3;
|
|
mul.wide.u32 %rd63, %r403, 8;
|
|
add.s64 %rd15, %rd62, %rd63;
|
|
@%p167 bra $L__BB0_148;
|
|
|
|
ld.global.v4.u16 {%rs91, %rs92, %rs93, %rs94}, [%rd15];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1556, %rs91;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1557, %rs92;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1558, %rs93;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1559, %f368, %f1556;
|
|
add.f32 %f1560, %f369, %f1557;
|
|
add.f32 %f1561, %f370, %f1558;
|
|
mov.f32 %f1562, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs89, %f1561;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs88, %f1560;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs87, %f1559;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f1562;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd15], {%rs87, %rs88, %rs89, %rs90};
|
|
bra.uni $L__BB0_149;
|
|
|
|
$L__BB0_148:
|
|
mov.f32 %f1566, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs98, %f1566;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs97, %f370;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs96, %f369;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs95, %f368;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd15], {%rs95, %rs96, %rs97, %rs98};
|
|
|
|
$L__BB0_149:
|
|
mul.f32 %f371, %f1812, 0f404EBF87;
|
|
mul.f32 %f372, %f1813, 0f404EBF87;
|
|
mul.f32 %f373, %f1814, 0f404EBF87;
|
|
ld.const.u64 %rd64, [params+320];
|
|
cvta.to.global.u64 %rd65, %rd64;
|
|
ld.const.u32 %r404, [params+312];
|
|
mad.lo.s32 %r405, %r404, %r4, %r3;
|
|
mul.wide.u32 %rd66, %r405, 8;
|
|
add.s64 %rd16, %rd65, %rd66;
|
|
@%p167 bra $L__BB0_151;
|
|
|
|
ld.global.v4.u16 {%rs106, %rs107, %rs108, %rs109}, [%rd16];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1567, %rs106;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1568, %rs107;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1569, %rs108;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1570, %f371, %f1567;
|
|
add.f32 %f1571, %f372, %f1568;
|
|
add.f32 %f1572, %f373, %f1569;
|
|
mov.f32 %f1573, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs104, %f1572;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs103, %f1571;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs102, %f1570;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs105, %f1573;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd16], {%rs102, %rs103, %rs104, %rs105};
|
|
bra.uni $L__BB0_152;
|
|
|
|
$L__BB0_151:
|
|
mov.f32 %f1577, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1577;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs112, %f373;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs111, %f372;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs110, %f371;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd16], {%rs110, %rs111, %rs112, %rs113};
|
|
|
|
$L__BB0_152:
|
|
mul.f32 %f374, %f1815, 0f404EBF87;
|
|
mul.f32 %f375, %f1816, 0f404EBF87;
|
|
mul.f32 %f376, %f1817, 0f404EBF87;
|
|
ld.const.u64 %rd67, [params+336];
|
|
cvta.to.global.u64 %rd68, %rd67;
|
|
ld.const.u32 %r406, [params+328];
|
|
mad.lo.s32 %r407, %r406, %r4, %r3;
|
|
mul.wide.u32 %rd69, %r407, 8;
|
|
add.s64 %rd17, %rd68, %rd69;
|
|
@%p167 bra $L__BB0_154;
|
|
|
|
ld.global.v4.u16 {%rs121, %rs122, %rs123, %rs124}, [%rd17];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1578, %rs121;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1579, %rs122;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1580, %rs123;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1581, %f374, %f1578;
|
|
add.f32 %f1582, %f375, %f1579;
|
|
add.f32 %f1583, %f376, %f1580;
|
|
mov.f32 %f1584, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs119, %f1583;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs118, %f1582;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs117, %f1581;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs120, %f1584;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd17], {%rs117, %rs118, %rs119, %rs120};
|
|
bra.uni $L__BB0_155;
|
|
|
|
$L__BB0_154:
|
|
mov.f32 %f1588, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1588;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs127, %f376;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs126, %f375;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs125, %f374;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd17], {%rs125, %rs126, %rs127, %rs128};
|
|
|
|
$L__BB0_155:
|
|
mul.f32 %f377, %f1818, 0f40330C94;
|
|
mul.f32 %f378, %f1819, 0f40330C94;
|
|
mul.f32 %f379, %f1820, 0f40330C94;
|
|
ld.const.u64 %rd70, [params+352];
|
|
cvta.to.global.u64 %rd71, %rd70;
|
|
ld.const.u32 %r408, [params+344];
|
|
mad.lo.s32 %r409, %r408, %r4, %r3;
|
|
mul.wide.u32 %rd72, %r409, 8;
|
|
add.s64 %rd18, %rd71, %rd72;
|
|
@%p167 bra $L__BB0_157;
|
|
|
|
ld.global.v4.u16 {%rs136, %rs137, %rs138, %rs139}, [%rd18];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1589, %rs136;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1590, %rs137;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1591, %rs138;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1592, %f377, %f1589;
|
|
add.f32 %f1593, %f378, %f1590;
|
|
add.f32 %f1594, %f379, %f1591;
|
|
mov.f32 %f1595, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs134, %f1594;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs133, %f1593;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs132, %f1592;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs135, %f1595;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs132, %rs133, %rs134, %rs135};
|
|
bra.uni $L__BB0_158;
|
|
|
|
$L__BB0_157:
|
|
mov.f32 %f1599, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1599;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs142, %f379;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs141, %f378;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs140, %f377;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd18], {%rs140, %rs141, %rs142, %rs143};
|
|
|
|
$L__BB0_158:
|
|
mul.f32 %f380, %f1821, 0f404EBF87;
|
|
mul.f32 %f381, %f1822, 0f404EBF87;
|
|
mul.f32 %f382, %f1823, 0f404EBF87;
|
|
ld.const.u64 %rd73, [params+368];
|
|
cvta.to.global.u64 %rd74, %rd73;
|
|
ld.const.u32 %r410, [params+360];
|
|
mad.lo.s32 %r411, %r410, %r4, %r3;
|
|
mul.wide.u32 %rd75, %r411, 8;
|
|
add.s64 %rd19, %rd74, %rd75;
|
|
@%p167 bra $L__BB0_160;
|
|
|
|
ld.global.v4.u16 {%rs151, %rs152, %rs153, %rs154}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1600, %rs151;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1601, %rs152;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1602, %rs153;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1603, %f380, %f1600;
|
|
add.f32 %f1604, %f381, %f1601;
|
|
add.f32 %f1605, %f382, %f1602;
|
|
mov.f32 %f1606, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs149, %f1605;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs148, %f1604;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs147, %f1603;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs150, %f1606;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs147, %rs148, %rs149, %rs150};
|
|
bra.uni $L__BB0_161;
|
|
|
|
$L__BB0_160:
|
|
mov.f32 %f1610, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1610;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs157, %f382;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs156, %f381;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs155, %f380;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs155, %rs156, %rs157, %rs158};
|
|
|
|
$L__BB0_161:
|
|
mul.f32 %f383, %f1824, 0f3FCEBF87;
|
|
mul.f32 %f384, %f1825, 0f3FCEBF87;
|
|
mul.f32 %f385, %f1826, 0f3FCEBF87;
|
|
ld.const.u64 %rd76, [params+384];
|
|
cvta.to.global.u64 %rd77, %rd76;
|
|
ld.const.u32 %r412, [params+376];
|
|
mad.lo.s32 %r413, %r412, %r4, %r3;
|
|
mul.wide.u32 %rd78, %r413, 8;
|
|
add.s64 %rd20, %rd77, %rd78;
|
|
@%p167 bra $L__BB0_163;
|
|
|
|
ld.global.v4.u16 {%rs166, %rs167, %rs168, %rs169}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1611, %rs166;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1612, %rs167;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1613, %rs168;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1614, %f383, %f1611;
|
|
add.f32 %f1615, %f384, %f1612;
|
|
add.f32 %f1616, %f385, %f1613;
|
|
mov.f32 %f1617, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs164, %f1616;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs163, %f1615;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs162, %f1614;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs165, %f1617;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs162, %rs163, %rs164, %rs165};
|
|
bra.uni $L__BB0_199;
|
|
|
|
$L__BB0_163:
|
|
mov.f32 %f1621, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs173, %f1621;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs172, %f385;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs171, %f384;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs170, %f383;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs170, %rs171, %rs172, %rs173};
|
|
|
|
$L__BB0_199:
|
|
ret;
|
|
|
|
}
|
|
|