2273 lines
61 KiB
Plaintext
2273 lines
61 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl __raygen__oxMain
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.const .align 16 .b8 params[1184];
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.global .align 4 .b8 __cudart_i2opi_f[24] = {65, 144, 67, 60, 153, 149, 98, 219, 192, 221, 52, 245, 209, 87, 39, 252, 41, 21, 68, 78, 110, 131, 249, 162};
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.visible .entry __raygen__oxMain()
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{
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.local .align 4 .b8 __local_depot0[28];
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.reg .b64 %SP;
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.reg .b64 %SPL;
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.reg .pred %p<155>;
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.reg .b16 %rs<172>;
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.reg .f32 %f<1208>;
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.reg .b32 %r<361>;
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.reg .f64 %fd<5>;
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.reg .b64 %rd<110>;
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mov.u64 %SPL, __local_depot0;
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add.u64 %rd1, %SPL, 0;
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// begin inline asm
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call (%r55), _optix_get_launch_index_x, ();
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// end inline asm
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// begin inline asm
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call (%r56), _optix_get_launch_index_y, ();
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// end inline asm
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ld.const.u32 %r3, [params+540];
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ld.const.u64 %rd30, [params+400];
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cvta.to.global.u64 %rd31, %rd30;
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ld.const.u32 %r61, [params+392];
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mad.lo.s32 %r62, %r61, %r56, %r55;
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mul.wide.u32 %rd32, %r62, 4;
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add.s64 %rd2, %rd31, %rd32;
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ld.global.v2.u8 {%rs7, %rs171}, [%rd2];
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or.b16 %rs9, %rs7, %rs171;
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and.b16 %rs10, %rs9, 255;
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setp.eq.s16 %p7, %rs10, 0;
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@%p7 bra $L__BB0_2;
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ld.global.u8 %rs170, [%rd2+2];
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bra.uni $L__BB0_3;
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$L__BB0_2:
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ld.global.u8 %rs170, [%rd2+2];
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setp.eq.s16 %p8, %rs170, 0;
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mov.f32 %f1121, 0f00000000;
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mov.u16 %rs171, 0;
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mov.f32 %f1122, %f1121;
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mov.f32 %f1123, %f1121;
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@%p8 bra $L__BB0_4;
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$L__BB0_3:
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cvt.rn.f32.u16 %f243, %rs7;
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div.rn.f32 %f244, %f243, 0f437F0000;
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fma.rn.f32 %f245, %f244, 0f40000000, 0fBF800000;
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and.b16 %rs13, %rs171, 255;
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cvt.rn.f32.u16 %f246, %rs13;
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div.rn.f32 %f247, %f246, 0f437F0000;
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fma.rn.f32 %f248, %f247, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f249, %rs170;
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div.rn.f32 %f250, %f249, 0f437F0000;
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fma.rn.f32 %f251, %f250, 0f40000000, 0fBF800000;
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mul.f32 %f252, %f248, %f248;
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fma.rn.f32 %f253, %f245, %f245, %f252;
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fma.rn.f32 %f254, %f251, %f251, %f253;
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sqrt.rn.f32 %f255, %f254;
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rcp.rn.f32 %f256, %f255;
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mul.f32 %f1123, %f256, %f251;
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mul.f32 %f1122, %f256, %f248;
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mul.f32 %f1121, %f245, %f256;
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$L__BB0_4:
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ld.const.v2.u32 {%r63, %r64}, [params];
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add.s32 %r4, %r63, %r55;
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add.s32 %r5, %r64, %r56;
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setp.eq.f32 %p9, %f1121, 0f00000000;
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setp.eq.f32 %p10, %f1122, 0f00000000;
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and.pred %p11, %p9, %p10;
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setp.eq.f32 %p12, %f1123, 0f00000000;
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and.pred %p13, %p12, %p11;
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@%p13 bra $L__BB0_126;
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bra.uni $L__BB0_5;
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$L__BB0_126:
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ld.const.u32 %r52, [params+104];
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and.b32 %r314, %r52, 1;
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setp.eq.b32 %p144, %r314, 1;
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mov.pred %p145, 0;
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xor.pred %p146, %p144, %p145;
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not.pred %p147, %p146;
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@%p147 bra $L__BB0_128;
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ld.const.u64 %rd83, [params+144];
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cvta.to.global.u64 %rd84, %rd83;
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ld.const.u32 %r315, [params+136];
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mad.lo.s32 %r316, %r315, %r5, %r4;
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mul.wide.u32 %rd85, %r316, 4;
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add.s64 %rd86, %rd84, %rd85;
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mov.u16 %rs94, 0;
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st.global.v4.u8 [%rd86], {%rs94, %rs94, %rs94, %rs94};
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$L__BB0_128:
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and.b32 %r317, %r52, 4;
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setp.eq.s32 %p148, %r317, 0;
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ld.const.u32 %r360, [params+108];
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@%p148 bra $L__BB0_132;
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setp.eq.s32 %p149, %r360, 0;
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ld.const.u64 %rd87, [params+224];
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cvta.to.global.u64 %rd88, %rd87;
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ld.const.u32 %r318, [params+216];
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mad.lo.s32 %r319, %r318, %r5, %r4;
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mul.wide.u32 %rd89, %r319, 8;
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add.s64 %rd24, %rd88, %rd89;
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@%p149 bra $L__BB0_131;
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ld.global.v4.u16 {%rs101, %rs102, %rs103, %rs104}, [%rd24];
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// begin inline asm
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{ cvt.f32.f16 %f1030, %rs101;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1031, %rs102;}
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// end inline asm
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// begin inline asm
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{ cvt.f32.f16 %f1032, %rs103;}
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// end inline asm
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add.f32 %f1033, %f1030, 0f00000000;
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add.f32 %f1034, %f1031, 0f00000000;
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add.f32 %f1035, %f1032, 0f00000000;
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// begin inline asm
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{ cvt.rn.f16.f32 %rs100, %f1035;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs99, %f1034;}
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// end inline asm
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// begin inline asm
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{ cvt.rn.f16.f32 %rs98, %f1033;}
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// end inline asm
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mov.u16 %rs105, 0;
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st.global.v4.u16 [%rd24], {%rs98, %rs99, %rs100, %rs105};
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bra.uni $L__BB0_132;
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$L__BB0_5:
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ld.const.u64 %rd33, [params+432];
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cvta.to.global.u64 %rd34, %rd33;
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ld.const.u32 %r67, [params+424];
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mad.lo.s32 %r68, %r67, %r56, %r55;
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mul.wide.u32 %rd35, %r68, 12;
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add.s64 %rd36, %rd34, %rd35;
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ld.global.f32 %f272, [%rd36];
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mul.f32 %f273, %f272, 0f3456BF95;
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ld.global.f32 %f274, [%rd36+4];
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mul.f32 %f275, %f274, 0f3456BF95;
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ld.global.f32 %f276, [%rd36+8];
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mul.f32 %f277, %f276, 0f3456BF95;
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abs.f32 %f278, %f1121;
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div.rn.f32 %f279, %f273, %f278;
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abs.f32 %f280, %f1122;
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div.rn.f32 %f281, %f275, %f280;
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abs.f32 %f282, %f1123;
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div.rn.f32 %f283, %f277, %f282;
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abs.f32 %f284, %f279;
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abs.f32 %f285, %f281;
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abs.f32 %f286, %f283;
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mov.f32 %f287, 0f38D1B717;
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max.f32 %f288, %f284, %f287;
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max.f32 %f289, %f285, %f287;
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max.f32 %f290, %f286, %f287;
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fma.rn.f32 %f10, %f1121, %f288, %f272;
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fma.rn.f32 %f11, %f1122, %f289, %f274;
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fma.rn.f32 %f12, %f1123, %f290, %f276;
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setp.gt.f32 %p14, %f278, %f282;
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neg.f32 %f291, %f1122;
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selp.f32 %f292, %f291, 0f00000000, %p14;
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mov.f32 %f1160, 0f00000000;
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neg.f32 %f293, %f1123;
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selp.f32 %f294, %f1121, %f293, %p14;
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selp.f32 %f295, 0f00000000, %f1122, %p14;
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mul.f32 %f296, %f294, %f294;
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fma.rn.f32 %f297, %f292, %f292, %f296;
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fma.rn.f32 %f298, %f295, %f295, %f297;
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sqrt.rn.f32 %f299, %f298;
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rcp.rn.f32 %f300, %f299;
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mul.f32 %f13, %f292, %f300;
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mul.f32 %f14, %f294, %f300;
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mul.f32 %f15, %f295, %f300;
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ld.const.u64 %rd37, [params+128];
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cvta.to.global.u64 %rd38, %rd37;
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ld.const.u32 %r69, [params+120];
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mad.lo.s32 %r70, %r69, %r56, %r55;
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mul.wide.u32 %rd39, %r70, 4;
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add.s64 %rd3, %rd38, %rd39;
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setp.lt.s32 %p15, %r3, 1;
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mov.f32 %f1161, %f1160;
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mov.f32 %f1162, %f1160;
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mov.f32 %f1163, %f1160;
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mov.f32 %f1164, %f1160;
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mov.f32 %f1165, %f1160;
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mov.f32 %f1166, %f1160;
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mov.f32 %f1167, %f1160;
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mov.f32 %f1168, %f1160;
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mov.f32 %f1169, %f1160;
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mov.f32 %f1170, %f1160;
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mov.f32 %f1171, %f1160;
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mov.f32 %f1172, %f1160;
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mov.f32 %f1173, %f1160;
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mov.f32 %f1174, %f1160;
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@%p15 bra $L__BB0_36;
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ld.const.u32 %r6, [params+588];
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cvt.rn.f32.s32 %f316, %r3;
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rcp.rn.f32 %f16, %f316;
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ld.global.u32 %r351, [%rd3];
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mul.f32 %f17, %f10, 0f3456BF95;
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mul.f32 %f18, %f11, 0f3456BF95;
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mul.f32 %f19, %f12, 0f3456BF95;
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ld.const.u64 %rd4, [params+592];
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ld.const.u64 %rd5, [params+96];
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mul.f32 %f317, %f1121, %f14;
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mul.f32 %f318, %f1122, %f13;
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sub.f32 %f20, %f318, %f317;
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mul.f32 %f319, %f1123, %f13;
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mul.f32 %f320, %f1121, %f15;
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sub.f32 %f21, %f320, %f319;
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mul.f32 %f321, %f1122, %f15;
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mul.f32 %f322, %f1123, %f14;
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sub.f32 %f22, %f322, %f321;
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mov.u32 %r71, 0;
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add.s64 %rd6, %rd1, 24;
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abs.f32 %f385, %f17;
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abs.f32 %f386, %f18;
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max.f32 %f387, %f385, %f386;
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abs.f32 %f388, %f19;
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max.f32 %f389, %f387, %f388;
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mov.u32 %r348, %r71;
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$L__BB0_7:
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mov.u32 %r350, %r71;
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$L__BB0_8:
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cvt.rn.f32.s32 %f1076, %r348;
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mad.lo.s32 %r73, %r351, 1664525, 1013904223;
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and.b32 %r74, %r73, 16777215;
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cvt.rn.f32.u32 %f323, %r74;
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fma.rn.f32 %f324, %f323, 0f33800000, %f1076;
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mul.f32 %f54, %f16, %f324;
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mad.lo.s32 %r351, %r73, 1664525, 1013904223;
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and.b32 %r75, %r351, 16777215;
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cvt.rn.f32.u32 %f325, %r75;
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cvt.rn.f32.s32 %f326, %r350;
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fma.rn.f32 %f327, %f325, 0f33800000, %f326;
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mul.f32 %f328, %f16, %f327;
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mul.f32 %f329, %f54, %f54;
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mov.f32 %f330, 0f3F800000;
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sub.f32 %f331, %f330, %f329;
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mov.f32 %f332, 0f00000000;
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max.f32 %f333, %f332, %f331;
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sqrt.rn.f32 %f55, %f333;
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mul.f32 %f56, %f328, 0f40C90FDB;
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mul.f32 %f334, %f56, 0f3F22F983;
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cvt.rni.s32.f32 %r355, %f334;
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cvt.rn.f32.s32 %f335, %r355;
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mov.f32 %f336, 0fBFC90FDA;
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fma.rn.f32 %f337, %f335, %f336, %f56;
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mov.f32 %f338, 0fB3A22168;
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fma.rn.f32 %f339, %f335, %f338, %f337;
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mov.f32 %f340, 0fA7C234C5;
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fma.rn.f32 %f1157, %f335, %f340, %f339;
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abs.f32 %f58, %f56;
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setp.ltu.f32 %p16, %f58, 0f47CE4780;
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mov.f32 %f1154, %f1157;
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@%p16 bra $L__BB0_16;
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setp.eq.f32 %p17, %f58, 0f7F800000;
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@%p17 bra $L__BB0_15;
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bra.uni $L__BB0_10;
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$L__BB0_15:
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mov.f32 %f343, 0f00000000;
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mul.rn.f32 %f1154, %f56, %f343;
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mov.u32 %r355, 0;
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bra.uni $L__BB0_16;
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$L__BB0_10:
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mov.b32 %r14, %f56;
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bfe.u32 %r77, %r14, 23, 8;
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mov.u64 %rd107, 0;
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mov.u32 %r352, 0;
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mov.u64 %rd106, __cudart_i2opi_f;
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mov.u64 %rd105, %rd1;
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$L__BB0_11:
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.pragma "nounroll";
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mov.b32 %r331, %f56;
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shl.b32 %r330, %r331, 8;
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or.b32 %r329, %r330, -2147483648;
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ld.global.nc.u32 %r79, [%rd106];
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mad.wide.u32 %rd42, %r79, %r329, %rd107;
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shr.u64 %rd107, %rd42, 32;
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st.local.u32 [%rd105], %rd42;
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add.s64 %rd106, %rd106, 4;
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add.s64 %rd105, %rd105, 4;
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add.s32 %r352, %r352, 1;
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setp.ne.s32 %p18, %r352, 6;
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@%p18 bra $L__BB0_11;
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add.s32 %r336, %r77, -128;
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mov.b32 %r335, %f56;
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bfe.u32 %r334, %r335, 23, 8;
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add.s32 %r333, %r334, -128;
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shr.u32 %r332, %r333, 5;
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st.local.u32 [%rd6], %rd107;
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mov.u32 %r81, 6;
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sub.s32 %r82, %r81, %r332;
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mul.wide.s32 %rd43, %r82, 4;
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add.s64 %rd44, %rd1, %rd43;
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ld.local.u32 %r353, [%rd44];
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ld.local.u32 %r354, [%rd44+-4];
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and.b32 %r23, %r333, 31;
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setp.eq.s32 %p19, %r23, 0;
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@%p19 bra $L__BB0_14;
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mov.b32 %r344, %f56;
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bfe.u32 %r343, %r344, 23, 8;
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add.s32 %r342, %r343, -128;
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shr.u32 %r341, %r342, 5;
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mov.u32 %r340, 4;
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sub.s32 %r339, %r340, %r341;
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mov.u32 %r83, 32;
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sub.s32 %r84, %r83, %r23;
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shr.u32 %r85, %r354, %r84;
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shl.b32 %r86, %r353, %r23;
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add.s32 %r353, %r85, %r86;
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mul.wide.s32 %rd45, %r339, 4;
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add.s64 %rd46, %rd1, %rd45;
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ld.local.u32 %r87, [%rd46];
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shr.u32 %r88, %r87, %r84;
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shl.b32 %r89, %r354, %r23;
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add.s32 %r354, %r88, %r89;
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$L__BB0_14:
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mov.b32 %r337, %f56;
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and.b32 %r90, %r337, -2147483648;
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shr.u32 %r91, %r354, 30;
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shl.b32 %r92, %r353, 2;
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or.b32 %r93, %r91, %r92;
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shr.u32 %r94, %r93, 31;
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shr.u32 %r95, %r353, 30;
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add.s32 %r96, %r94, %r95;
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neg.s32 %r97, %r96;
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setp.eq.s32 %p20, %r90, 0;
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selp.b32 %r355, %r96, %r97, %p20;
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setp.ne.s32 %p21, %r94, 0;
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xor.b32 %r98, %r90, -2147483648;
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selp.b32 %r99, %r98, %r90, %p21;
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selp.b32 %r100, -1, 0, %p21;
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xor.b32 %r101, %r93, %r100;
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shl.b32 %r102, %r354, 2;
|
|
xor.b32 %r103, %r102, %r100;
|
|
cvt.u64.u32 %rd47, %r101;
|
|
cvt.u64.u32 %rd48, %r103;
|
|
bfi.b64 %rd49, %rd47, %rd48, 32, 32;
|
|
cvt.rn.f64.s64 %fd1, %rd49;
|
|
mul.f64 %fd2, %fd1, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f341, %fd2;
|
|
setp.eq.s32 %p22, %r99, 0;
|
|
neg.f32 %f342, %f341;
|
|
selp.f32 %f1154, %f341, %f342, %p22;
|
|
|
|
$L__BB0_16:
|
|
add.s32 %r30, %r355, 1;
|
|
and.b32 %r31, %r30, 1;
|
|
setp.eq.s32 %p23, %r31, 0;
|
|
selp.f32 %f62, %f1154, 0f3F800000, %p23;
|
|
mul.rn.f32 %f63, %f1154, %f1154;
|
|
mov.f32 %f1155, 0fB94D4153;
|
|
@%p23 bra $L__BB0_18;
|
|
|
|
mov.f32 %f345, 0fBAB607ED;
|
|
mov.f32 %f346, 0f37CBAC00;
|
|
fma.rn.f32 %f1155, %f346, %f63, %f345;
|
|
|
|
$L__BB0_18:
|
|
selp.f32 %f347, 0f3C0885E4, 0f3D2AAABB, %p23;
|
|
fma.rn.f32 %f348, %f1155, %f63, %f347;
|
|
selp.f32 %f349, 0fBE2AAAA8, 0fBEFFFFFF, %p23;
|
|
fma.rn.f32 %f350, %f348, %f63, %f349;
|
|
mov.f32 %f351, 0f00000000;
|
|
fma.rn.f32 %f352, %f63, %f62, %f351;
|
|
fma.rn.f32 %f1156, %f350, %f352, %f62;
|
|
and.b32 %r105, %r30, 2;
|
|
setp.eq.s32 %p25, %r105, 0;
|
|
@%p25 bra $L__BB0_20;
|
|
|
|
mov.f32 %f354, 0fBF800000;
|
|
fma.rn.f32 %f1156, %f1156, %f354, %f351;
|
|
|
|
$L__BB0_20:
|
|
mul.f32 %f1075, %f56, 0f3F22F983;
|
|
cvt.rni.s32.f32 %r358, %f1075;
|
|
setp.ltu.f32 %p154, %f58, 0f47CE4780;
|
|
@%p154 bra $L__BB0_28;
|
|
|
|
setp.eq.f32 %p27, %f58, 0f7F800000;
|
|
@%p27 bra $L__BB0_27;
|
|
bra.uni $L__BB0_22;
|
|
|
|
$L__BB0_27:
|
|
mov.f32 %f357, 0f00000000;
|
|
mul.rn.f32 %f1157, %f56, %f357;
|
|
mov.u32 %r358, 0;
|
|
bra.uni $L__BB0_28;
|
|
|
|
$L__BB0_22:
|
|
mov.b32 %r32, %f56;
|
|
bfe.u32 %r106, %r32, 23, 8;
|
|
add.s32 %r33, %r106, -128;
|
|
shl.b32 %r107, %r32, 8;
|
|
or.b32 %r34, %r107, -2147483648;
|
|
shr.u32 %r35, %r33, 5;
|
|
mov.u64 %rd108, 0;
|
|
mov.u64 %rd109, %rd108;
|
|
|
|
$L__BB0_23:
|
|
.pragma "nounroll";
|
|
shl.b64 %rd52, %rd108, 2;
|
|
mov.u64 %rd53, __cudart_i2opi_f;
|
|
add.s64 %rd54, %rd53, %rd52;
|
|
ld.global.nc.u32 %r108, [%rd54];
|
|
mad.wide.u32 %rd55, %r108, %r34, %rd109;
|
|
shr.u64 %rd109, %rd55, 32;
|
|
add.s64 %rd56, %rd1, %rd52;
|
|
st.local.u32 [%rd56], %rd55;
|
|
cvt.u32.u64 %r109, %rd108;
|
|
add.s32 %r110, %r109, 1;
|
|
cvt.s64.s32 %rd108, %r110;
|
|
setp.ne.s32 %p28, %r110, 6;
|
|
@%p28 bra $L__BB0_23;
|
|
|
|
st.local.u32 [%rd6], %rd109;
|
|
mov.u32 %r111, 4;
|
|
sub.s32 %r36, %r111, %r35;
|
|
mov.u32 %r112, 6;
|
|
sub.s32 %r113, %r112, %r35;
|
|
mul.wide.s32 %rd57, %r113, 4;
|
|
add.s64 %rd58, %rd1, %rd57;
|
|
ld.local.u32 %r356, [%rd58];
|
|
ld.local.u32 %r357, [%rd58+-4];
|
|
and.b32 %r39, %r33, 31;
|
|
setp.eq.s32 %p29, %r39, 0;
|
|
@%p29 bra $L__BB0_26;
|
|
|
|
mov.u32 %r114, 32;
|
|
sub.s32 %r115, %r114, %r39;
|
|
shr.u32 %r116, %r357, %r115;
|
|
shl.b32 %r117, %r356, %r39;
|
|
add.s32 %r356, %r116, %r117;
|
|
mul.wide.s32 %rd59, %r36, 4;
|
|
add.s64 %rd60, %rd1, %rd59;
|
|
ld.local.u32 %r118, [%rd60];
|
|
shr.u32 %r119, %r118, %r115;
|
|
shl.b32 %r120, %r357, %r39;
|
|
add.s32 %r357, %r119, %r120;
|
|
|
|
$L__BB0_26:
|
|
and.b32 %r121, %r32, -2147483648;
|
|
shr.u32 %r122, %r357, 30;
|
|
shl.b32 %r123, %r356, 2;
|
|
or.b32 %r124, %r122, %r123;
|
|
shr.u32 %r125, %r124, 31;
|
|
shr.u32 %r126, %r356, 30;
|
|
add.s32 %r127, %r125, %r126;
|
|
neg.s32 %r128, %r127;
|
|
setp.eq.s32 %p30, %r121, 0;
|
|
selp.b32 %r358, %r127, %r128, %p30;
|
|
setp.ne.s32 %p31, %r125, 0;
|
|
xor.b32 %r129, %r121, -2147483648;
|
|
selp.b32 %r130, %r129, %r121, %p31;
|
|
selp.b32 %r131, -1, 0, %p31;
|
|
xor.b32 %r132, %r124, %r131;
|
|
shl.b32 %r133, %r357, 2;
|
|
xor.b32 %r134, %r133, %r131;
|
|
cvt.u64.u32 %rd61, %r132;
|
|
cvt.u64.u32 %rd62, %r134;
|
|
bfi.b64 %rd63, %rd61, %rd62, 32, 32;
|
|
cvt.rn.f64.s64 %fd3, %rd63;
|
|
mul.f64 %fd4, %fd3, 0d3BF921FB54442D19;
|
|
cvt.rn.f32.f64 %f355, %fd4;
|
|
setp.eq.s32 %p32, %r130, 0;
|
|
neg.f32 %f356, %f355;
|
|
selp.f32 %f1157, %f355, %f356, %p32;
|
|
|
|
$L__BB0_28:
|
|
mul.f32 %f72, %f55, %f1156;
|
|
and.b32 %r46, %r358, 1;
|
|
setp.eq.s32 %p33, %r46, 0;
|
|
mul.rn.f32 %f74, %f1157, %f1157;
|
|
mov.f32 %f1158, 0fB94D4153;
|
|
@%p33 bra $L__BB0_30;
|
|
|
|
mov.f32 %f359, 0fBAB607ED;
|
|
mov.f32 %f360, 0f37CBAC00;
|
|
fma.rn.f32 %f1158, %f360, %f74, %f359;
|
|
|
|
$L__BB0_30:
|
|
selp.f32 %f1077, %f1157, 0f3F800000, %p33;
|
|
selp.f32 %f361, 0f3C0885E4, 0f3D2AAABB, %p33;
|
|
fma.rn.f32 %f362, %f1158, %f74, %f361;
|
|
selp.f32 %f363, 0fBE2AAAA8, 0fBEFFFFFF, %p33;
|
|
fma.rn.f32 %f364, %f362, %f74, %f363;
|
|
mov.f32 %f365, 0f00000000;
|
|
fma.rn.f32 %f366, %f74, %f1077, %f365;
|
|
fma.rn.f32 %f1159, %f364, %f366, %f1077;
|
|
and.b32 %r136, %r358, 2;
|
|
setp.eq.s32 %p35, %r136, 0;
|
|
@%p35 bra $L__BB0_32;
|
|
|
|
mov.f32 %f368, 0fBF800000;
|
|
fma.rn.f32 %f1159, %f1159, %f368, %f365;
|
|
|
|
$L__BB0_32:
|
|
mul.f32 %f369, %f55, %f1159;
|
|
mul.f32 %f370, %f13, %f369;
|
|
mul.f32 %f371, %f14, %f369;
|
|
mul.f32 %f372, %f15, %f369;
|
|
fma.rn.f32 %f373, %f22, %f72, %f370;
|
|
fma.rn.f32 %f374, %f21, %f72, %f371;
|
|
fma.rn.f32 %f375, %f20, %f72, %f372;
|
|
fma.rn.f32 %f80, %f1121, %f54, %f373;
|
|
fma.rn.f32 %f81, %f1122, %f54, %f374;
|
|
fma.rn.f32 %f82, %f1123, %f54, %f375;
|
|
setp.leu.f32 %p36, %f81, 0f00000000;
|
|
setp.ne.s32 %p37, %r6, 0;
|
|
and.pred %p38, %p37, %p36;
|
|
@%p38 bra $L__BB0_34;
|
|
|
|
mov.f32 %f390, 0f38D1B717;
|
|
max.f32 %f382, %f389, %f390;
|
|
neg.f32 %f391, %f80;
|
|
neg.f32 %f392, %f81;
|
|
neg.f32 %f393, %f82;
|
|
tex.cube.v4.f32.f32 {%f394, %f395, %f396, %f397}, [%rd4, {%f393, %f392, %f391, %f391}];
|
|
mov.b32 %r176, %f394;
|
|
mov.b32 %r177, %f395;
|
|
mov.b32 %r178, %f396;
|
|
mov.f32 %f383, 0f6C4ECB8F;
|
|
mov.f32 %f384, 0f00000000;
|
|
mov.u32 %r173, 2;
|
|
mov.u32 %r174, 1;
|
|
mov.u32 %r175, 3;
|
|
mov.u32 %r207, 0;
|
|
// begin inline asm
|
|
call(%r137,%r138,%r139,%r140,%r141,%r142,%r143,%r144,%r145,%r146,%r147,%r148,%r149,%r150,%r151,%r152,%r153,%r154,%r155,%r156,%r157,%r158,%r159,%r160,%r161,%r162,%r163,%r164,%r165,%r166,%r167,%r168),_optix_trace_typed_32,(%r207,%rd5,%f10,%f11,%f12,%f80,%f81,%f82,%f382,%f383,%f384,%r174,%r207,%r174,%r173,%r174,%r175,%r176,%r177,%r178,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207,%r207);
|
|
// end inline asm
|
|
mov.b32 %f398, %r137;
|
|
mov.b32 %f399, %r138;
|
|
mov.b32 %f400, %r139;
|
|
mul.f32 %f401, %f1122, %f81;
|
|
fma.rn.f32 %f402, %f1121, %f80, %f401;
|
|
fma.rn.f32 %f403, %f1123, %f82, %f402;
|
|
mul.f32 %f404, %f403, 0f40800000;
|
|
cvt.sat.f32.f32 %f405, %f404;
|
|
mul.f32 %f406, %f405, %f398;
|
|
mul.f32 %f407, %f405, %f399;
|
|
mul.f32 %f408, %f405, %f400;
|
|
fma.rn.f32 %f1166, %f80, %f406, %f1166;
|
|
fma.rn.f32 %f1167, %f80, %f407, %f1167;
|
|
fma.rn.f32 %f1168, %f80, %f408, %f1168;
|
|
fma.rn.f32 %f1163, %f81, %f406, %f1163;
|
|
fma.rn.f32 %f1164, %f81, %f407, %f1164;
|
|
fma.rn.f32 %f1165, %f81, %f408, %f1165;
|
|
fma.rn.f32 %f1160, %f82, %f406, %f1160;
|
|
fma.rn.f32 %f1161, %f82, %f407, %f1161;
|
|
fma.rn.f32 %f1162, %f82, %f408, %f1162;
|
|
add.f32 %f1169, %f1169, %f406;
|
|
add.f32 %f1170, %f1170, %f407;
|
|
add.f32 %f1171, %f1171, %f408;
|
|
cvt.sat.f32.f32 %f409, %f403;
|
|
fma.rn.f32 %f1172, %f409, %f398, %f1172;
|
|
fma.rn.f32 %f1173, %f409, %f399, %f1173;
|
|
fma.rn.f32 %f1174, %f409, %f400, %f1174;
|
|
|
|
$L__BB0_34:
|
|
add.s32 %r350, %r350, 1;
|
|
setp.lt.s32 %p39, %r350, %r3;
|
|
@%p39 bra $L__BB0_8;
|
|
|
|
add.s32 %r348, %r348, 1;
|
|
setp.lt.s32 %p40, %r348, %r3;
|
|
@%p40 bra $L__BB0_7;
|
|
|
|
$L__BB0_36:
|
|
mul.lo.s32 %r208, %r3, %r3;
|
|
cvt.rn.f32.s32 %f410, %r208;
|
|
rcp.rn.f32 %f411, %f410;
|
|
mul.f32 %f412, %f411, %f1172;
|
|
mul.f32 %f413, %f411, %f1173;
|
|
mul.f32 %f414, %f411, %f1174;
|
|
mul.f32 %f128, %f411, %f1169;
|
|
mul.f32 %f129, %f411, %f1170;
|
|
mul.f32 %f130, %f411, %f1171;
|
|
mul.f32 %f131, %f411, %f1166;
|
|
mul.f32 %f132, %f411, %f1167;
|
|
mul.f32 %f133, %f411, %f1168;
|
|
mul.f32 %f134, %f411, %f1163;
|
|
mul.f32 %f135, %f411, %f1164;
|
|
mul.f32 %f136, %f411, %f1165;
|
|
mul.f32 %f137, %f411, %f1160;
|
|
mul.f32 %f138, %f411, %f1161;
|
|
mul.f32 %f139, %f411, %f1162;
|
|
fma.rn.f32 %f415, %f411, %f1172, %f412;
|
|
fma.rn.f32 %f416, %f411, %f1173, %f413;
|
|
fma.rn.f32 %f417, %f411, %f1174, %f414;
|
|
ld.const.v4.f32 {%f418, %f419, %f420, %f421}, [params+576];
|
|
mul.f32 %f143, %f415, %f418;
|
|
mul.f32 %f144, %f416, %f419;
|
|
mul.f32 %f145, %f417, %f420;
|
|
ld.const.u32 %r49, [params+104];
|
|
and.b32 %r209, %r49, 1;
|
|
setp.eq.b32 %p41, %r209, 1;
|
|
mov.pred %p42, 0;
|
|
xor.pred %p43, %p41, %p42;
|
|
not.pred %p44, %p43;
|
|
@%p44 bra $L__BB0_110;
|
|
|
|
mov.f32 %f423, 0f3E666666;
|
|
cvt.rzi.f32.f32 %f424, %f423;
|
|
add.f32 %f425, %f424, %f424;
|
|
mov.f32 %f426, 0f3EE66666;
|
|
sub.f32 %f427, %f426, %f425;
|
|
abs.f32 %f146, %f427;
|
|
abs.f32 %f147, %f143;
|
|
setp.lt.f32 %p45, %f147, 0f00800000;
|
|
mul.f32 %f428, %f147, 0f4B800000;
|
|
selp.f32 %f429, %f428, %f147, %p45;
|
|
selp.f32 %f430, 0fC3170000, 0fC2FE0000, %p45;
|
|
mov.b32 %r210, %f429;
|
|
and.b32 %r211, %r210, 8388607;
|
|
or.b32 %r212, %r211, 1065353216;
|
|
mov.b32 %f431, %r212;
|
|
shr.u32 %r213, %r210, 23;
|
|
cvt.rn.f32.u32 %f432, %r213;
|
|
add.f32 %f433, %f430, %f432;
|
|
setp.gt.f32 %p46, %f431, 0f3FB504F3;
|
|
mul.f32 %f434, %f431, 0f3F000000;
|
|
add.f32 %f435, %f433, 0f3F800000;
|
|
selp.f32 %f436, %f435, %f433, %p46;
|
|
selp.f32 %f437, %f434, %f431, %p46;
|
|
add.f32 %f438, %f437, 0fBF800000;
|
|
add.f32 %f439, %f437, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f440, %f439;
|
|
add.f32 %f441, %f438, %f438;
|
|
mul.f32 %f442, %f441, %f440;
|
|
mul.f32 %f443, %f442, %f442;
|
|
mov.f32 %f444, 0f3C4CAF63;
|
|
mov.f32 %f445, 0f3B18F0FE;
|
|
fma.rn.f32 %f446, %f445, %f443, %f444;
|
|
mov.f32 %f447, 0f3DAAAABD;
|
|
fma.rn.f32 %f448, %f446, %f443, %f447;
|
|
mul.rn.f32 %f449, %f448, %f443;
|
|
mul.rn.f32 %f450, %f449, %f442;
|
|
sub.f32 %f451, %f438, %f442;
|
|
add.f32 %f452, %f451, %f451;
|
|
neg.f32 %f453, %f442;
|
|
fma.rn.f32 %f454, %f453, %f438, %f452;
|
|
mul.rn.f32 %f455, %f440, %f454;
|
|
add.f32 %f456, %f450, %f442;
|
|
sub.f32 %f457, %f442, %f456;
|
|
add.f32 %f458, %f450, %f457;
|
|
add.f32 %f459, %f455, %f458;
|
|
add.f32 %f460, %f456, %f459;
|
|
sub.f32 %f461, %f456, %f460;
|
|
add.f32 %f462, %f459, %f461;
|
|
mov.f32 %f463, 0f3F317200;
|
|
mul.rn.f32 %f464, %f436, %f463;
|
|
mov.f32 %f465, 0f35BFBE8E;
|
|
mul.rn.f32 %f466, %f436, %f465;
|
|
add.f32 %f467, %f464, %f460;
|
|
sub.f32 %f468, %f464, %f467;
|
|
add.f32 %f469, %f460, %f468;
|
|
add.f32 %f470, %f462, %f469;
|
|
add.f32 %f471, %f466, %f470;
|
|
add.f32 %f472, %f467, %f471;
|
|
sub.f32 %f473, %f467, %f472;
|
|
add.f32 %f474, %f471, %f473;
|
|
mul.rn.f32 %f475, %f426, %f472;
|
|
neg.f32 %f476, %f475;
|
|
fma.rn.f32 %f477, %f426, %f472, %f476;
|
|
fma.rn.f32 %f478, %f426, %f474, %f477;
|
|
mov.f32 %f479, 0f00000000;
|
|
fma.rn.f32 %f480, %f479, %f472, %f478;
|
|
add.rn.f32 %f481, %f475, %f480;
|
|
neg.f32 %f482, %f481;
|
|
add.rn.f32 %f483, %f475, %f482;
|
|
add.rn.f32 %f484, %f483, %f480;
|
|
mov.b32 %r214, %f481;
|
|
setp.eq.s32 %p47, %r214, 1118925336;
|
|
add.s32 %r215, %r214, -1;
|
|
mov.b32 %f485, %r215;
|
|
add.f32 %f486, %f484, 0f37000000;
|
|
selp.f32 %f148, %f486, %f484, %p47;
|
|
selp.f32 %f487, %f485, %f481, %p47;
|
|
mov.f32 %f488, 0f3FB8AA3B;
|
|
mul.rn.f32 %f489, %f487, %f488;
|
|
cvt.rzi.f32.f32 %f490, %f489;
|
|
abs.f32 %f491, %f490;
|
|
setp.gt.f32 %p48, %f491, 0f42FC0000;
|
|
mov.b32 %r216, %f490;
|
|
and.b32 %r217, %r216, -2147483648;
|
|
or.b32 %r218, %r217, 1123811328;
|
|
mov.b32 %f492, %r218;
|
|
selp.f32 %f493, %f492, %f490, %p48;
|
|
mov.f32 %f494, 0fBF317218;
|
|
fma.rn.f32 %f495, %f493, %f494, %f487;
|
|
mov.f32 %f496, 0f3102E308;
|
|
fma.rn.f32 %f497, %f493, %f496, %f495;
|
|
mul.f32 %f498, %f497, 0f3FB8AA3B;
|
|
add.f32 %f499, %f493, 0f4B40007F;
|
|
mov.b32 %r219, %f499;
|
|
shl.b32 %r220, %r219, 23;
|
|
mov.b32 %f500, %r220;
|
|
ex2.approx.ftz.f32 %f501, %f498;
|
|
mul.f32 %f149, %f501, %f500;
|
|
setp.eq.f32 %p49, %f149, 0f7F800000;
|
|
mov.f32 %f1190, 0f7F800000;
|
|
@%p49 bra $L__BB0_39;
|
|
|
|
fma.rn.f32 %f1190, %f149, %f148, %f149;
|
|
|
|
$L__BB0_39:
|
|
setp.lt.f32 %p50, %f143, 0f00000000;
|
|
setp.eq.f32 %p51, %f146, 0f3F800000;
|
|
and.pred %p1, %p50, %p51;
|
|
setp.eq.f32 %p52, %f143, 0f00000000;
|
|
@%p52 bra $L__BB0_43;
|
|
bra.uni $L__BB0_40;
|
|
|
|
$L__BB0_43:
|
|
add.f32 %f506, %f143, %f143;
|
|
selp.f32 %f1192, %f506, 0f00000000, %p51;
|
|
bra.uni $L__BB0_44;
|
|
|
|
$L__BB0_131:
|
|
mov.f32 %f1038, 0f00000000;
|
|
mov.u32 %r360, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs108, %f1038;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs107, %f1038;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs106, %f1038;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs109, 0;
|
|
st.global.v4.u16 [%rd24], {%rs106, %rs107, %rs108, %rs109};
|
|
|
|
$L__BB0_132:
|
|
ld.const.u64 %rd90, [params+256];
|
|
cvta.to.global.u64 %rd91, %rd90;
|
|
ld.const.u32 %r321, [params+248];
|
|
mad.lo.s32 %r322, %r321, %r5, %r4;
|
|
mul.wide.u32 %rd92, %r322, 8;
|
|
add.s64 %rd25, %rd91, %rd92;
|
|
setp.eq.s32 %p150, %r360, 0;
|
|
@%p150 bra $L__BB0_134;
|
|
|
|
ld.global.v4.u16 {%rs116, %rs117, %rs118, %rs119}, [%rd25];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1039, %rs116;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1040, %rs117;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1041, %rs118;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1042, %f1039, 0f00000000;
|
|
add.f32 %f1043, %f1040, 0f00000000;
|
|
add.f32 %f1044, %f1041, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs115, %f1044;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs114, %f1043;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs113, %f1042;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs120, 0;
|
|
st.global.v4.u16 [%rd25], {%rs113, %rs114, %rs115, %rs120};
|
|
bra.uni $L__BB0_135;
|
|
|
|
$L__BB0_134:
|
|
mov.f32 %f1047, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs123, %f1047;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs122, %f1047;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs121, %f1047;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs124, 0;
|
|
st.global.v4.u16 [%rd25], {%rs121, %rs122, %rs123, %rs124};
|
|
|
|
$L__BB0_135:
|
|
ld.const.u64 %rd93, [params+272];
|
|
cvta.to.global.u64 %rd94, %rd93;
|
|
ld.const.u32 %r323, [params+264];
|
|
mad.lo.s32 %r324, %r323, %r5, %r4;
|
|
mul.wide.u32 %rd95, %r324, 8;
|
|
add.s64 %rd26, %rd94, %rd95;
|
|
@%p150 bra $L__BB0_137;
|
|
|
|
ld.global.v4.u16 {%rs131, %rs132, %rs133, %rs134}, [%rd26];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1048, %rs131;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1049, %rs132;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1050, %rs133;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1051, %f1048, 0f00000000;
|
|
add.f32 %f1052, %f1049, 0f00000000;
|
|
add.f32 %f1053, %f1050, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs130, %f1053;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs129, %f1052;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs128, %f1051;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs135, 0;
|
|
st.global.v4.u16 [%rd26], {%rs128, %rs129, %rs130, %rs135};
|
|
bra.uni $L__BB0_138;
|
|
|
|
$L__BB0_137:
|
|
mov.f32 %f1056, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs138, %f1056;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs137, %f1056;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs136, %f1056;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs139, 0;
|
|
st.global.v4.u16 [%rd26], {%rs136, %rs137, %rs138, %rs139};
|
|
|
|
$L__BB0_138:
|
|
ld.const.u64 %rd96, [params+288];
|
|
cvta.to.global.u64 %rd97, %rd96;
|
|
ld.const.u32 %r325, [params+280];
|
|
mad.lo.s32 %r326, %r325, %r5, %r4;
|
|
mul.wide.u32 %rd98, %r326, 8;
|
|
add.s64 %rd27, %rd97, %rd98;
|
|
@%p150 bra $L__BB0_140;
|
|
|
|
ld.global.v4.u16 {%rs146, %rs147, %rs148, %rs149}, [%rd27];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1057, %rs146;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1058, %rs147;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1059, %rs148;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1060, %f1057, 0f00000000;
|
|
add.f32 %f1061, %f1058, 0f00000000;
|
|
add.f32 %f1062, %f1059, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs145, %f1062;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs144, %f1061;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs143, %f1060;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs150, 0;
|
|
st.global.v4.u16 [%rd27], {%rs143, %rs144, %rs145, %rs150};
|
|
bra.uni $L__BB0_141;
|
|
|
|
$L__BB0_140:
|
|
mov.f32 %f1065, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs153, %f1065;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs152, %f1065;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs151, %f1065;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs154, 0;
|
|
st.global.v4.u16 [%rd27], {%rs151, %rs152, %rs153, %rs154};
|
|
|
|
$L__BB0_141:
|
|
ld.const.u64 %rd99, [params+304];
|
|
cvta.to.global.u64 %rd100, %rd99;
|
|
ld.const.u32 %r327, [params+296];
|
|
mad.lo.s32 %r328, %r327, %r5, %r4;
|
|
mul.wide.u32 %rd101, %r328, 8;
|
|
add.s64 %rd28, %rd100, %rd101;
|
|
@%p150 bra $L__BB0_143;
|
|
|
|
ld.global.v4.u16 {%rs161, %rs162, %rs163, %rs164}, [%rd28];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1066, %rs161;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1067, %rs162;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1068, %rs163;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1069, %f1066, 0f00000000;
|
|
add.f32 %f1070, %f1067, 0f00000000;
|
|
add.f32 %f1071, %f1068, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs160, %f1071;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs159, %f1070;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs158, %f1069;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs165, 0;
|
|
st.global.v4.u16 [%rd28], {%rs158, %rs159, %rs160, %rs165};
|
|
bra.uni $L__BB0_144;
|
|
|
|
$L__BB0_143:
|
|
mov.f32 %f1074, 0f00000000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs168, %f1074;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs167, %f1074;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs166, %f1074;}
|
|
|
|
// end inline asm
|
|
mov.u16 %rs169, 0;
|
|
st.global.v4.u16 [%rd28], {%rs166, %rs167, %rs168, %rs169};
|
|
bra.uni $L__BB0_144;
|
|
|
|
$L__BB0_40:
|
|
mov.b32 %r221, %f1190;
|
|
xor.b32 %r222, %r221, -2147483648;
|
|
mov.b32 %f502, %r222;
|
|
selp.f32 %f1192, %f502, %f1190, %p1;
|
|
setp.geu.f32 %p53, %f143, 0f00000000;
|
|
@%p53 bra $L__BB0_44;
|
|
|
|
mov.f32 %f503, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f504, %f503;
|
|
setp.eq.f32 %p54, %f504, 0f3EE66666;
|
|
@%p54 bra $L__BB0_44;
|
|
|
|
mov.f32 %f1192, 0f7FFFFFFF;
|
|
|
|
$L__BB0_44:
|
|
add.f32 %f507, %f147, 0f3EE66666;
|
|
mov.b32 %r223, %f507;
|
|
setp.lt.s32 %p56, %r223, 2139095040;
|
|
@%p56 bra $L__BB0_49;
|
|
|
|
setp.gtu.f32 %p57, %f147, 0f7F800000;
|
|
@%p57 bra $L__BB0_48;
|
|
bra.uni $L__BB0_46;
|
|
|
|
$L__BB0_48:
|
|
add.f32 %f1192, %f143, 0f3EE66666;
|
|
bra.uni $L__BB0_49;
|
|
|
|
$L__BB0_46:
|
|
setp.neu.f32 %p58, %f147, 0f7F800000;
|
|
@%p58 bra $L__BB0_49;
|
|
|
|
selp.f32 %f1192, 0fFF800000, 0f7F800000, %p1;
|
|
|
|
$L__BB0_49:
|
|
setp.eq.f32 %p59, %f143, 0f3F800000;
|
|
selp.f32 %f158, 0f3F800000, %f1192, %p59;
|
|
abs.f32 %f159, %f144;
|
|
setp.lt.f32 %p60, %f159, 0f00800000;
|
|
mul.f32 %f509, %f159, 0f4B800000;
|
|
selp.f32 %f510, %f509, %f159, %p60;
|
|
selp.f32 %f511, 0fC3170000, 0fC2FE0000, %p60;
|
|
mov.b32 %r224, %f510;
|
|
and.b32 %r225, %r224, 8388607;
|
|
or.b32 %r226, %r225, 1065353216;
|
|
mov.b32 %f512, %r226;
|
|
shr.u32 %r227, %r224, 23;
|
|
cvt.rn.f32.u32 %f513, %r227;
|
|
add.f32 %f514, %f511, %f513;
|
|
setp.gt.f32 %p61, %f512, 0f3FB504F3;
|
|
mul.f32 %f515, %f512, 0f3F000000;
|
|
add.f32 %f516, %f514, 0f3F800000;
|
|
selp.f32 %f517, %f516, %f514, %p61;
|
|
selp.f32 %f518, %f515, %f512, %p61;
|
|
add.f32 %f519, %f518, 0fBF800000;
|
|
add.f32 %f520, %f518, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f521, %f520;
|
|
add.f32 %f522, %f519, %f519;
|
|
mul.f32 %f523, %f522, %f521;
|
|
mul.f32 %f524, %f523, %f523;
|
|
mov.f32 %f525, 0f3C4CAF63;
|
|
mov.f32 %f526, 0f3B18F0FE;
|
|
fma.rn.f32 %f527, %f526, %f524, %f525;
|
|
mov.f32 %f528, 0f3DAAAABD;
|
|
fma.rn.f32 %f529, %f527, %f524, %f528;
|
|
mul.rn.f32 %f530, %f529, %f524;
|
|
mul.rn.f32 %f531, %f530, %f523;
|
|
sub.f32 %f532, %f519, %f523;
|
|
add.f32 %f533, %f532, %f532;
|
|
neg.f32 %f534, %f523;
|
|
fma.rn.f32 %f535, %f534, %f519, %f533;
|
|
mul.rn.f32 %f536, %f521, %f535;
|
|
add.f32 %f537, %f531, %f523;
|
|
sub.f32 %f538, %f523, %f537;
|
|
add.f32 %f539, %f531, %f538;
|
|
add.f32 %f540, %f536, %f539;
|
|
add.f32 %f541, %f537, %f540;
|
|
sub.f32 %f542, %f537, %f541;
|
|
add.f32 %f543, %f540, %f542;
|
|
mov.f32 %f544, 0f3F317200;
|
|
mul.rn.f32 %f545, %f517, %f544;
|
|
mov.f32 %f546, 0f35BFBE8E;
|
|
mul.rn.f32 %f547, %f517, %f546;
|
|
add.f32 %f548, %f545, %f541;
|
|
sub.f32 %f549, %f545, %f548;
|
|
add.f32 %f550, %f541, %f549;
|
|
add.f32 %f551, %f543, %f550;
|
|
add.f32 %f552, %f547, %f551;
|
|
add.f32 %f553, %f548, %f552;
|
|
sub.f32 %f554, %f548, %f553;
|
|
add.f32 %f555, %f552, %f554;
|
|
mov.f32 %f556, 0f3EE66666;
|
|
mul.rn.f32 %f557, %f556, %f553;
|
|
neg.f32 %f558, %f557;
|
|
fma.rn.f32 %f559, %f556, %f553, %f558;
|
|
fma.rn.f32 %f560, %f556, %f555, %f559;
|
|
mov.f32 %f561, 0f00000000;
|
|
fma.rn.f32 %f562, %f561, %f553, %f560;
|
|
add.rn.f32 %f563, %f557, %f562;
|
|
neg.f32 %f564, %f563;
|
|
add.rn.f32 %f565, %f557, %f564;
|
|
add.rn.f32 %f566, %f565, %f562;
|
|
mov.b32 %r228, %f563;
|
|
setp.eq.s32 %p62, %r228, 1118925336;
|
|
add.s32 %r229, %r228, -1;
|
|
mov.b32 %f567, %r229;
|
|
add.f32 %f568, %f566, 0f37000000;
|
|
selp.f32 %f160, %f568, %f566, %p62;
|
|
selp.f32 %f569, %f567, %f563, %p62;
|
|
mov.f32 %f570, 0f3FB8AA3B;
|
|
mul.rn.f32 %f571, %f569, %f570;
|
|
cvt.rzi.f32.f32 %f572, %f571;
|
|
abs.f32 %f573, %f572;
|
|
setp.gt.f32 %p63, %f573, 0f42FC0000;
|
|
mov.b32 %r230, %f572;
|
|
and.b32 %r231, %r230, -2147483648;
|
|
or.b32 %r232, %r231, 1123811328;
|
|
mov.b32 %f574, %r232;
|
|
selp.f32 %f575, %f574, %f572, %p63;
|
|
mov.f32 %f576, 0fBF317218;
|
|
fma.rn.f32 %f577, %f575, %f576, %f569;
|
|
mov.f32 %f578, 0f3102E308;
|
|
fma.rn.f32 %f579, %f575, %f578, %f577;
|
|
mul.f32 %f580, %f579, 0f3FB8AA3B;
|
|
add.f32 %f581, %f575, 0f4B40007F;
|
|
mov.b32 %r233, %f581;
|
|
shl.b32 %r234, %r233, 23;
|
|
mov.b32 %f582, %r234;
|
|
ex2.approx.ftz.f32 %f583, %f580;
|
|
mul.f32 %f161, %f583, %f582;
|
|
setp.eq.f32 %p64, %f161, 0f7F800000;
|
|
mov.f32 %f1193, 0f7F800000;
|
|
@%p64 bra $L__BB0_51;
|
|
|
|
fma.rn.f32 %f1193, %f161, %f160, %f161;
|
|
|
|
$L__BB0_51:
|
|
setp.lt.f32 %p65, %f144, 0f00000000;
|
|
and.pred %p2, %p65, %p51;
|
|
setp.eq.f32 %p67, %f144, 0f00000000;
|
|
@%p67 bra $L__BB0_55;
|
|
bra.uni $L__BB0_52;
|
|
|
|
$L__BB0_55:
|
|
add.f32 %f588, %f144, %f144;
|
|
selp.f32 %f1195, %f588, 0f00000000, %p51;
|
|
bra.uni $L__BB0_56;
|
|
|
|
$L__BB0_52:
|
|
mov.b32 %r235, %f1193;
|
|
xor.b32 %r236, %r235, -2147483648;
|
|
mov.b32 %f584, %r236;
|
|
selp.f32 %f1195, %f584, %f1193, %p2;
|
|
setp.geu.f32 %p68, %f144, 0f00000000;
|
|
@%p68 bra $L__BB0_56;
|
|
|
|
mov.f32 %f585, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f586, %f585;
|
|
setp.eq.f32 %p69, %f586, 0f3EE66666;
|
|
@%p69 bra $L__BB0_56;
|
|
|
|
mov.f32 %f1195, 0f7FFFFFFF;
|
|
|
|
$L__BB0_56:
|
|
add.f32 %f589, %f159, 0f3EE66666;
|
|
mov.b32 %r237, %f589;
|
|
setp.lt.s32 %p71, %r237, 2139095040;
|
|
@%p71 bra $L__BB0_61;
|
|
|
|
setp.gtu.f32 %p72, %f159, 0f7F800000;
|
|
@%p72 bra $L__BB0_60;
|
|
bra.uni $L__BB0_58;
|
|
|
|
$L__BB0_60:
|
|
add.f32 %f1195, %f144, 0f3EE66666;
|
|
bra.uni $L__BB0_61;
|
|
|
|
$L__BB0_58:
|
|
setp.neu.f32 %p73, %f159, 0f7F800000;
|
|
@%p73 bra $L__BB0_61;
|
|
|
|
selp.f32 %f1195, 0fFF800000, 0f7F800000, %p2;
|
|
|
|
$L__BB0_61:
|
|
setp.eq.f32 %p74, %f144, 0f3F800000;
|
|
selp.f32 %f170, 0f3F800000, %f1195, %p74;
|
|
abs.f32 %f171, %f145;
|
|
setp.lt.f32 %p75, %f171, 0f00800000;
|
|
mul.f32 %f591, %f171, 0f4B800000;
|
|
selp.f32 %f592, %f591, %f171, %p75;
|
|
selp.f32 %f593, 0fC3170000, 0fC2FE0000, %p75;
|
|
mov.b32 %r238, %f592;
|
|
and.b32 %r239, %r238, 8388607;
|
|
or.b32 %r240, %r239, 1065353216;
|
|
mov.b32 %f594, %r240;
|
|
shr.u32 %r241, %r238, 23;
|
|
cvt.rn.f32.u32 %f595, %r241;
|
|
add.f32 %f596, %f593, %f595;
|
|
setp.gt.f32 %p76, %f594, 0f3FB504F3;
|
|
mul.f32 %f597, %f594, 0f3F000000;
|
|
add.f32 %f598, %f596, 0f3F800000;
|
|
selp.f32 %f599, %f598, %f596, %p76;
|
|
selp.f32 %f600, %f597, %f594, %p76;
|
|
add.f32 %f601, %f600, 0fBF800000;
|
|
add.f32 %f602, %f600, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f603, %f602;
|
|
add.f32 %f604, %f601, %f601;
|
|
mul.f32 %f605, %f604, %f603;
|
|
mul.f32 %f606, %f605, %f605;
|
|
mov.f32 %f607, 0f3C4CAF63;
|
|
mov.f32 %f608, 0f3B18F0FE;
|
|
fma.rn.f32 %f609, %f608, %f606, %f607;
|
|
mov.f32 %f610, 0f3DAAAABD;
|
|
fma.rn.f32 %f611, %f609, %f606, %f610;
|
|
mul.rn.f32 %f612, %f611, %f606;
|
|
mul.rn.f32 %f613, %f612, %f605;
|
|
sub.f32 %f614, %f601, %f605;
|
|
add.f32 %f615, %f614, %f614;
|
|
neg.f32 %f616, %f605;
|
|
fma.rn.f32 %f617, %f616, %f601, %f615;
|
|
mul.rn.f32 %f618, %f603, %f617;
|
|
add.f32 %f619, %f613, %f605;
|
|
sub.f32 %f620, %f605, %f619;
|
|
add.f32 %f621, %f613, %f620;
|
|
add.f32 %f622, %f618, %f621;
|
|
add.f32 %f623, %f619, %f622;
|
|
sub.f32 %f624, %f619, %f623;
|
|
add.f32 %f625, %f622, %f624;
|
|
mov.f32 %f626, 0f3F317200;
|
|
mul.rn.f32 %f627, %f599, %f626;
|
|
mov.f32 %f628, 0f35BFBE8E;
|
|
mul.rn.f32 %f629, %f599, %f628;
|
|
add.f32 %f630, %f627, %f623;
|
|
sub.f32 %f631, %f627, %f630;
|
|
add.f32 %f632, %f623, %f631;
|
|
add.f32 %f633, %f625, %f632;
|
|
add.f32 %f634, %f629, %f633;
|
|
add.f32 %f635, %f630, %f634;
|
|
sub.f32 %f636, %f630, %f635;
|
|
add.f32 %f637, %f634, %f636;
|
|
mov.f32 %f638, 0f3EE66666;
|
|
mul.rn.f32 %f639, %f638, %f635;
|
|
neg.f32 %f640, %f639;
|
|
fma.rn.f32 %f641, %f638, %f635, %f640;
|
|
fma.rn.f32 %f642, %f638, %f637, %f641;
|
|
mov.f32 %f643, 0f00000000;
|
|
fma.rn.f32 %f644, %f643, %f635, %f642;
|
|
add.rn.f32 %f645, %f639, %f644;
|
|
neg.f32 %f646, %f645;
|
|
add.rn.f32 %f647, %f639, %f646;
|
|
add.rn.f32 %f648, %f647, %f644;
|
|
mov.b32 %r242, %f645;
|
|
setp.eq.s32 %p77, %r242, 1118925336;
|
|
add.s32 %r243, %r242, -1;
|
|
mov.b32 %f649, %r243;
|
|
add.f32 %f650, %f648, 0f37000000;
|
|
selp.f32 %f172, %f650, %f648, %p77;
|
|
selp.f32 %f651, %f649, %f645, %p77;
|
|
mov.f32 %f652, 0f3FB8AA3B;
|
|
mul.rn.f32 %f653, %f651, %f652;
|
|
cvt.rzi.f32.f32 %f654, %f653;
|
|
abs.f32 %f655, %f654;
|
|
setp.gt.f32 %p78, %f655, 0f42FC0000;
|
|
mov.b32 %r244, %f654;
|
|
and.b32 %r245, %r244, -2147483648;
|
|
or.b32 %r246, %r245, 1123811328;
|
|
mov.b32 %f656, %r246;
|
|
selp.f32 %f657, %f656, %f654, %p78;
|
|
mov.f32 %f658, 0fBF317218;
|
|
fma.rn.f32 %f659, %f657, %f658, %f651;
|
|
mov.f32 %f660, 0f3102E308;
|
|
fma.rn.f32 %f661, %f657, %f660, %f659;
|
|
mul.f32 %f662, %f661, 0f3FB8AA3B;
|
|
add.f32 %f663, %f657, 0f4B40007F;
|
|
mov.b32 %r247, %f663;
|
|
shl.b32 %r248, %r247, 23;
|
|
mov.b32 %f664, %r248;
|
|
ex2.approx.ftz.f32 %f665, %f662;
|
|
mul.f32 %f173, %f665, %f664;
|
|
setp.eq.f32 %p79, %f173, 0f7F800000;
|
|
mov.f32 %f1196, 0f7F800000;
|
|
@%p79 bra $L__BB0_63;
|
|
|
|
fma.rn.f32 %f1196, %f173, %f172, %f173;
|
|
|
|
$L__BB0_63:
|
|
setp.lt.f32 %p80, %f145, 0f00000000;
|
|
and.pred %p3, %p80, %p51;
|
|
setp.eq.f32 %p82, %f145, 0f00000000;
|
|
@%p82 bra $L__BB0_67;
|
|
bra.uni $L__BB0_64;
|
|
|
|
$L__BB0_67:
|
|
add.f32 %f670, %f145, %f145;
|
|
selp.f32 %f1198, %f670, 0f00000000, %p51;
|
|
bra.uni $L__BB0_68;
|
|
|
|
$L__BB0_64:
|
|
mov.b32 %r249, %f1196;
|
|
xor.b32 %r250, %r249, -2147483648;
|
|
mov.b32 %f666, %r250;
|
|
selp.f32 %f1198, %f666, %f1196, %p3;
|
|
setp.geu.f32 %p83, %f145, 0f00000000;
|
|
@%p83 bra $L__BB0_68;
|
|
|
|
mov.f32 %f667, 0f3EE66666;
|
|
cvt.rzi.f32.f32 %f668, %f667;
|
|
setp.eq.f32 %p84, %f668, 0f3EE66666;
|
|
@%p84 bra $L__BB0_68;
|
|
|
|
mov.f32 %f1198, 0f7FFFFFFF;
|
|
|
|
$L__BB0_68:
|
|
add.f32 %f671, %f171, 0f3EE66666;
|
|
mov.b32 %r251, %f671;
|
|
setp.lt.s32 %p86, %r251, 2139095040;
|
|
@%p86 bra $L__BB0_73;
|
|
|
|
setp.gtu.f32 %p87, %f171, 0f7F800000;
|
|
@%p87 bra $L__BB0_72;
|
|
bra.uni $L__BB0_70;
|
|
|
|
$L__BB0_72:
|
|
add.f32 %f1198, %f145, 0f3EE66666;
|
|
bra.uni $L__BB0_73;
|
|
|
|
$L__BB0_70:
|
|
setp.neu.f32 %p88, %f171, 0f7F800000;
|
|
@%p88 bra $L__BB0_73;
|
|
|
|
selp.f32 %f1198, 0fFF800000, 0f7F800000, %p3;
|
|
|
|
$L__BB0_73:
|
|
setp.eq.f32 %p89, %f145, 0f3F800000;
|
|
mov.f32 %f673, 0f3F800000;
|
|
selp.f32 %f674, 0f3F800000, %f1198, %p89;
|
|
min.f32 %f675, %f158, %f673;
|
|
mov.f32 %f676, 0f00000000;
|
|
max.f32 %f182, %f676, %f675;
|
|
min.f32 %f677, %f170, %f673;
|
|
max.f32 %f183, %f676, %f677;
|
|
min.f32 %f678, %f674, %f673;
|
|
max.f32 %f184, %f676, %f678;
|
|
mov.f32 %f682, 0f3ED55555;
|
|
abs.f32 %f186, %f182;
|
|
setp.lt.f32 %p90, %f186, 0f00800000;
|
|
mul.f32 %f684, %f186, 0f4B800000;
|
|
selp.f32 %f685, %f684, %f186, %p90;
|
|
selp.f32 %f686, 0fC3170000, 0fC2FE0000, %p90;
|
|
mov.b32 %r254, %f685;
|
|
and.b32 %r255, %r254, 8388607;
|
|
or.b32 %r256, %r255, 1065353216;
|
|
mov.b32 %f687, %r256;
|
|
shr.u32 %r257, %r254, 23;
|
|
cvt.rn.f32.u32 %f688, %r257;
|
|
add.f32 %f689, %f686, %f688;
|
|
setp.gt.f32 %p91, %f687, 0f3FB504F3;
|
|
mul.f32 %f690, %f687, 0f3F000000;
|
|
add.f32 %f691, %f689, 0f3F800000;
|
|
selp.f32 %f692, %f691, %f689, %p91;
|
|
selp.f32 %f693, %f690, %f687, %p91;
|
|
add.f32 %f694, %f693, 0fBF800000;
|
|
add.f32 %f695, %f693, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f696, %f695;
|
|
add.f32 %f697, %f694, %f694;
|
|
mul.f32 %f698, %f697, %f696;
|
|
mul.f32 %f699, %f698, %f698;
|
|
mov.f32 %f700, 0f3C4CAF63;
|
|
mov.f32 %f701, 0f3B18F0FE;
|
|
fma.rn.f32 %f702, %f701, %f699, %f700;
|
|
mov.f32 %f703, 0f3DAAAABD;
|
|
fma.rn.f32 %f704, %f702, %f699, %f703;
|
|
mul.rn.f32 %f705, %f704, %f699;
|
|
mul.rn.f32 %f706, %f705, %f698;
|
|
sub.f32 %f707, %f694, %f698;
|
|
add.f32 %f708, %f707, %f707;
|
|
neg.f32 %f709, %f698;
|
|
fma.rn.f32 %f710, %f709, %f694, %f708;
|
|
mul.rn.f32 %f711, %f696, %f710;
|
|
add.f32 %f712, %f706, %f698;
|
|
sub.f32 %f713, %f698, %f712;
|
|
add.f32 %f714, %f706, %f713;
|
|
add.f32 %f715, %f711, %f714;
|
|
add.f32 %f716, %f712, %f715;
|
|
sub.f32 %f717, %f712, %f716;
|
|
add.f32 %f718, %f715, %f717;
|
|
mov.f32 %f719, 0f3F317200;
|
|
mul.rn.f32 %f720, %f692, %f719;
|
|
mov.f32 %f721, 0f35BFBE8E;
|
|
mul.rn.f32 %f722, %f692, %f721;
|
|
add.f32 %f723, %f720, %f716;
|
|
sub.f32 %f724, %f720, %f723;
|
|
add.f32 %f725, %f716, %f724;
|
|
add.f32 %f726, %f718, %f725;
|
|
add.f32 %f727, %f722, %f726;
|
|
add.f32 %f728, %f723, %f727;
|
|
sub.f32 %f729, %f723, %f728;
|
|
add.f32 %f730, %f727, %f729;
|
|
mul.rn.f32 %f731, %f682, %f728;
|
|
neg.f32 %f732, %f731;
|
|
fma.rn.f32 %f733, %f682, %f728, %f732;
|
|
fma.rn.f32 %f734, %f682, %f730, %f733;
|
|
fma.rn.f32 %f735, %f676, %f728, %f734;
|
|
add.rn.f32 %f736, %f731, %f735;
|
|
neg.f32 %f737, %f736;
|
|
add.rn.f32 %f738, %f731, %f737;
|
|
add.rn.f32 %f739, %f738, %f735;
|
|
mov.b32 %r258, %f736;
|
|
setp.eq.s32 %p92, %r258, 1118925336;
|
|
add.s32 %r259, %r258, -1;
|
|
mov.b32 %f740, %r259;
|
|
add.f32 %f741, %f739, 0f37000000;
|
|
selp.f32 %f187, %f741, %f739, %p92;
|
|
selp.f32 %f742, %f740, %f736, %p92;
|
|
mov.f32 %f743, 0f3FB8AA3B;
|
|
mul.rn.f32 %f744, %f742, %f743;
|
|
cvt.rzi.f32.f32 %f745, %f744;
|
|
abs.f32 %f746, %f745;
|
|
setp.gt.f32 %p93, %f746, 0f42FC0000;
|
|
mov.b32 %r260, %f745;
|
|
and.b32 %r261, %r260, -2147483648;
|
|
or.b32 %r262, %r261, 1123811328;
|
|
mov.b32 %f747, %r262;
|
|
selp.f32 %f748, %f747, %f745, %p93;
|
|
mov.f32 %f749, 0fBF317218;
|
|
fma.rn.f32 %f750, %f748, %f749, %f742;
|
|
mov.f32 %f751, 0f3102E308;
|
|
fma.rn.f32 %f752, %f748, %f751, %f750;
|
|
mul.f32 %f753, %f752, 0f3FB8AA3B;
|
|
add.f32 %f754, %f748, 0f4B40007F;
|
|
mov.b32 %r263, %f754;
|
|
shl.b32 %r264, %r263, 23;
|
|
mov.b32 %f755, %r264;
|
|
ex2.approx.ftz.f32 %f756, %f753;
|
|
mul.f32 %f188, %f756, %f755;
|
|
setp.eq.f32 %p94, %f188, 0f7F800000;
|
|
mov.f32 %f1199, 0f7F800000;
|
|
@%p94 bra $L__BB0_75;
|
|
|
|
fma.rn.f32 %f1199, %f188, %f187, %f188;
|
|
|
|
$L__BB0_75:
|
|
mov.f32 %f1103, 0f00000000;
|
|
max.f32 %f1102, %f1103, %f675;
|
|
mov.f32 %f1083, 0f3E555555;
|
|
cvt.rzi.f32.f32 %f1082, %f1083;
|
|
add.f32 %f1081, %f1082, %f1082;
|
|
mov.f32 %f1080, 0f3ED55555;
|
|
sub.f32 %f1079, %f1080, %f1081;
|
|
abs.f32 %f1078, %f1079;
|
|
setp.lt.f32 %p95, %f1102, 0f00000000;
|
|
setp.eq.f32 %p96, %f1078, 0f3F800000;
|
|
and.pred %p4, %p95, %p96;
|
|
setp.eq.f32 %p97, %f1102, 0f00000000;
|
|
@%p97 bra $L__BB0_79;
|
|
bra.uni $L__BB0_76;
|
|
|
|
$L__BB0_79:
|
|
mov.f32 %f1120, 0f00000000;
|
|
max.f32 %f1119, %f1120, %f675;
|
|
add.f32 %f761, %f1119, %f1119;
|
|
selp.f32 %f1201, %f761, 0f00000000, %p96;
|
|
bra.uni $L__BB0_80;
|
|
|
|
$L__BB0_76:
|
|
mov.f32 %f1105, 0f00000000;
|
|
max.f32 %f1104, %f1105, %f675;
|
|
mov.b32 %r265, %f1199;
|
|
xor.b32 %r266, %r265, -2147483648;
|
|
mov.b32 %f757, %r266;
|
|
selp.f32 %f1201, %f757, %f1199, %p4;
|
|
setp.geu.f32 %p98, %f1104, 0f00000000;
|
|
@%p98 bra $L__BB0_80;
|
|
|
|
mov.f32 %f758, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f759, %f758;
|
|
setp.eq.f32 %p99, %f759, 0f3ED55555;
|
|
@%p99 bra $L__BB0_80;
|
|
|
|
mov.f32 %f1201, 0f7FFFFFFF;
|
|
|
|
$L__BB0_80:
|
|
mov.f32 %f1108, 0f00000000;
|
|
max.f32 %f1107, %f1108, %f675;
|
|
abs.f32 %f1106, %f1107;
|
|
add.f32 %f762, %f1106, 0f3ED55555;
|
|
mov.b32 %r267, %f762;
|
|
setp.lt.s32 %p101, %r267, 2139095040;
|
|
@%p101 bra $L__BB0_85;
|
|
|
|
mov.f32 %f1113, 0f00000000;
|
|
max.f32 %f1112, %f1113, %f675;
|
|
abs.f32 %f1111, %f1112;
|
|
setp.gtu.f32 %p102, %f1111, 0f7F800000;
|
|
@%p102 bra $L__BB0_84;
|
|
bra.uni $L__BB0_82;
|
|
|
|
$L__BB0_84:
|
|
mov.f32 %f1118, 0f00000000;
|
|
max.f32 %f1117, %f1118, %f675;
|
|
add.f32 %f1201, %f1117, 0f3ED55555;
|
|
bra.uni $L__BB0_85;
|
|
|
|
$L__BB0_82:
|
|
mov.f32 %f1116, 0f00000000;
|
|
max.f32 %f1115, %f1116, %f675;
|
|
abs.f32 %f1114, %f1115;
|
|
setp.neu.f32 %p103, %f1114, 0f7F800000;
|
|
@%p103 bra $L__BB0_85;
|
|
|
|
selp.f32 %f1201, 0fFF800000, 0f7F800000, %p4;
|
|
|
|
$L__BB0_85:
|
|
abs.f32 %f197, %f183;
|
|
setp.lt.f32 %p104, %f197, 0f00800000;
|
|
mul.f32 %f764, %f197, 0f4B800000;
|
|
selp.f32 %f765, %f764, %f197, %p104;
|
|
selp.f32 %f766, 0fC3170000, 0fC2FE0000, %p104;
|
|
mov.b32 %r268, %f765;
|
|
and.b32 %r269, %r268, 8388607;
|
|
or.b32 %r270, %r269, 1065353216;
|
|
mov.b32 %f767, %r270;
|
|
shr.u32 %r271, %r268, 23;
|
|
cvt.rn.f32.u32 %f768, %r271;
|
|
add.f32 %f769, %f766, %f768;
|
|
setp.gt.f32 %p105, %f767, 0f3FB504F3;
|
|
mul.f32 %f770, %f767, 0f3F000000;
|
|
add.f32 %f771, %f769, 0f3F800000;
|
|
selp.f32 %f772, %f771, %f769, %p105;
|
|
selp.f32 %f773, %f770, %f767, %p105;
|
|
add.f32 %f774, %f773, 0fBF800000;
|
|
add.f32 %f775, %f773, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f776, %f775;
|
|
add.f32 %f777, %f774, %f774;
|
|
mul.f32 %f778, %f777, %f776;
|
|
mul.f32 %f779, %f778, %f778;
|
|
mov.f32 %f780, 0f3C4CAF63;
|
|
mov.f32 %f781, 0f3B18F0FE;
|
|
fma.rn.f32 %f782, %f781, %f779, %f780;
|
|
mov.f32 %f783, 0f3DAAAABD;
|
|
fma.rn.f32 %f784, %f782, %f779, %f783;
|
|
mul.rn.f32 %f785, %f784, %f779;
|
|
mul.rn.f32 %f786, %f785, %f778;
|
|
sub.f32 %f787, %f774, %f778;
|
|
add.f32 %f788, %f787, %f787;
|
|
neg.f32 %f789, %f778;
|
|
fma.rn.f32 %f790, %f789, %f774, %f788;
|
|
mul.rn.f32 %f791, %f776, %f790;
|
|
add.f32 %f792, %f786, %f778;
|
|
sub.f32 %f793, %f778, %f792;
|
|
add.f32 %f794, %f786, %f793;
|
|
add.f32 %f795, %f791, %f794;
|
|
add.f32 %f796, %f792, %f795;
|
|
sub.f32 %f797, %f792, %f796;
|
|
add.f32 %f798, %f795, %f797;
|
|
mov.f32 %f799, 0f3F317200;
|
|
mul.rn.f32 %f800, %f772, %f799;
|
|
mov.f32 %f801, 0f35BFBE8E;
|
|
mul.rn.f32 %f802, %f772, %f801;
|
|
add.f32 %f803, %f800, %f796;
|
|
sub.f32 %f804, %f800, %f803;
|
|
add.f32 %f805, %f796, %f804;
|
|
add.f32 %f806, %f798, %f805;
|
|
add.f32 %f807, %f802, %f806;
|
|
add.f32 %f808, %f803, %f807;
|
|
sub.f32 %f809, %f803, %f808;
|
|
add.f32 %f810, %f807, %f809;
|
|
mov.f32 %f811, 0f3ED55555;
|
|
mul.rn.f32 %f812, %f811, %f808;
|
|
neg.f32 %f813, %f812;
|
|
fma.rn.f32 %f814, %f811, %f808, %f813;
|
|
fma.rn.f32 %f815, %f811, %f810, %f814;
|
|
mov.f32 %f816, 0f00000000;
|
|
fma.rn.f32 %f817, %f816, %f808, %f815;
|
|
add.rn.f32 %f818, %f812, %f817;
|
|
neg.f32 %f819, %f818;
|
|
add.rn.f32 %f820, %f812, %f819;
|
|
add.rn.f32 %f821, %f820, %f817;
|
|
mov.b32 %r272, %f818;
|
|
setp.eq.s32 %p106, %r272, 1118925336;
|
|
add.s32 %r273, %r272, -1;
|
|
mov.b32 %f822, %r273;
|
|
add.f32 %f823, %f821, 0f37000000;
|
|
selp.f32 %f198, %f823, %f821, %p106;
|
|
selp.f32 %f824, %f822, %f818, %p106;
|
|
mov.f32 %f825, 0f3FB8AA3B;
|
|
mul.rn.f32 %f826, %f824, %f825;
|
|
cvt.rzi.f32.f32 %f827, %f826;
|
|
abs.f32 %f828, %f827;
|
|
setp.gt.f32 %p107, %f828, 0f42FC0000;
|
|
mov.b32 %r274, %f827;
|
|
and.b32 %r275, %r274, -2147483648;
|
|
or.b32 %r276, %r275, 1123811328;
|
|
mov.b32 %f829, %r276;
|
|
selp.f32 %f830, %f829, %f827, %p107;
|
|
mov.f32 %f831, 0fBF317218;
|
|
fma.rn.f32 %f832, %f830, %f831, %f824;
|
|
mov.f32 %f833, 0f3102E308;
|
|
fma.rn.f32 %f834, %f830, %f833, %f832;
|
|
mul.f32 %f835, %f834, 0f3FB8AA3B;
|
|
add.f32 %f836, %f830, 0f4B40007F;
|
|
mov.b32 %r277, %f836;
|
|
shl.b32 %r278, %r277, 23;
|
|
mov.b32 %f837, %r278;
|
|
ex2.approx.ftz.f32 %f838, %f835;
|
|
mul.f32 %f199, %f838, %f837;
|
|
setp.eq.f32 %p108, %f199, 0f7F800000;
|
|
mov.f32 %f1202, 0f7F800000;
|
|
@%p108 bra $L__BB0_87;
|
|
|
|
fma.rn.f32 %f1202, %f199, %f198, %f199;
|
|
|
|
$L__BB0_87:
|
|
setp.lt.f32 %p109, %f183, 0f00000000;
|
|
and.pred %p5, %p109, %p96;
|
|
setp.eq.f32 %p111, %f183, 0f00000000;
|
|
@%p111 bra $L__BB0_91;
|
|
bra.uni $L__BB0_88;
|
|
|
|
$L__BB0_91:
|
|
add.f32 %f843, %f183, %f183;
|
|
selp.f32 %f1204, %f843, 0f00000000, %p96;
|
|
bra.uni $L__BB0_92;
|
|
|
|
$L__BB0_88:
|
|
mov.b32 %r279, %f1202;
|
|
xor.b32 %r280, %r279, -2147483648;
|
|
mov.b32 %f839, %r280;
|
|
selp.f32 %f1204, %f839, %f1202, %p5;
|
|
setp.geu.f32 %p112, %f183, 0f00000000;
|
|
@%p112 bra $L__BB0_92;
|
|
|
|
mov.f32 %f840, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f841, %f840;
|
|
setp.eq.f32 %p113, %f841, 0f3ED55555;
|
|
@%p113 bra $L__BB0_92;
|
|
|
|
mov.f32 %f1204, 0f7FFFFFFF;
|
|
|
|
$L__BB0_92:
|
|
mov.f32 %f1086, 0f00000000;
|
|
max.f32 %f1085, %f1086, %f677;
|
|
abs.f32 %f1084, %f1085;
|
|
add.f32 %f844, %f1084, 0f3ED55555;
|
|
mov.b32 %r281, %f844;
|
|
setp.lt.s32 %p115, %r281, 2139095040;
|
|
@%p115 bra $L__BB0_97;
|
|
|
|
mov.f32 %f1089, 0f00000000;
|
|
max.f32 %f1088, %f1089, %f677;
|
|
abs.f32 %f1087, %f1088;
|
|
setp.gtu.f32 %p116, %f1087, 0f7F800000;
|
|
@%p116 bra $L__BB0_96;
|
|
bra.uni $L__BB0_94;
|
|
|
|
$L__BB0_96:
|
|
add.f32 %f1204, %f183, 0f3ED55555;
|
|
bra.uni $L__BB0_97;
|
|
|
|
$L__BB0_94:
|
|
mov.f32 %f1092, 0f00000000;
|
|
max.f32 %f1091, %f1092, %f677;
|
|
abs.f32 %f1090, %f1091;
|
|
setp.neu.f32 %p117, %f1090, 0f7F800000;
|
|
@%p117 bra $L__BB0_97;
|
|
|
|
selp.f32 %f1204, 0fFF800000, 0f7F800000, %p5;
|
|
|
|
$L__BB0_97:
|
|
abs.f32 %f208, %f184;
|
|
setp.lt.f32 %p118, %f208, 0f00800000;
|
|
mul.f32 %f846, %f208, 0f4B800000;
|
|
selp.f32 %f847, %f846, %f208, %p118;
|
|
selp.f32 %f848, 0fC3170000, 0fC2FE0000, %p118;
|
|
mov.b32 %r282, %f847;
|
|
and.b32 %r283, %r282, 8388607;
|
|
or.b32 %r284, %r283, 1065353216;
|
|
mov.b32 %f849, %r284;
|
|
shr.u32 %r285, %r282, 23;
|
|
cvt.rn.f32.u32 %f850, %r285;
|
|
add.f32 %f851, %f848, %f850;
|
|
setp.gt.f32 %p119, %f849, 0f3FB504F3;
|
|
mul.f32 %f852, %f849, 0f3F000000;
|
|
add.f32 %f853, %f851, 0f3F800000;
|
|
selp.f32 %f854, %f853, %f851, %p119;
|
|
selp.f32 %f855, %f852, %f849, %p119;
|
|
add.f32 %f856, %f855, 0fBF800000;
|
|
add.f32 %f857, %f855, 0f3F800000;
|
|
rcp.approx.ftz.f32 %f858, %f857;
|
|
add.f32 %f859, %f856, %f856;
|
|
mul.f32 %f860, %f859, %f858;
|
|
mul.f32 %f861, %f860, %f860;
|
|
mov.f32 %f862, 0f3C4CAF63;
|
|
mov.f32 %f863, 0f3B18F0FE;
|
|
fma.rn.f32 %f864, %f863, %f861, %f862;
|
|
mov.f32 %f865, 0f3DAAAABD;
|
|
fma.rn.f32 %f866, %f864, %f861, %f865;
|
|
mul.rn.f32 %f867, %f866, %f861;
|
|
mul.rn.f32 %f868, %f867, %f860;
|
|
sub.f32 %f869, %f856, %f860;
|
|
add.f32 %f870, %f869, %f869;
|
|
neg.f32 %f871, %f860;
|
|
fma.rn.f32 %f872, %f871, %f856, %f870;
|
|
mul.rn.f32 %f873, %f858, %f872;
|
|
add.f32 %f874, %f868, %f860;
|
|
sub.f32 %f875, %f860, %f874;
|
|
add.f32 %f876, %f868, %f875;
|
|
add.f32 %f877, %f873, %f876;
|
|
add.f32 %f878, %f874, %f877;
|
|
sub.f32 %f879, %f874, %f878;
|
|
add.f32 %f880, %f877, %f879;
|
|
mov.f32 %f881, 0f3F317200;
|
|
mul.rn.f32 %f882, %f854, %f881;
|
|
mov.f32 %f883, 0f35BFBE8E;
|
|
mul.rn.f32 %f884, %f854, %f883;
|
|
add.f32 %f885, %f882, %f878;
|
|
sub.f32 %f886, %f882, %f885;
|
|
add.f32 %f887, %f878, %f886;
|
|
add.f32 %f888, %f880, %f887;
|
|
add.f32 %f889, %f884, %f888;
|
|
add.f32 %f890, %f885, %f889;
|
|
sub.f32 %f891, %f885, %f890;
|
|
add.f32 %f892, %f889, %f891;
|
|
mov.f32 %f893, 0f3ED55555;
|
|
mul.rn.f32 %f894, %f893, %f890;
|
|
neg.f32 %f895, %f894;
|
|
fma.rn.f32 %f896, %f893, %f890, %f895;
|
|
fma.rn.f32 %f897, %f893, %f892, %f896;
|
|
mov.f32 %f898, 0f00000000;
|
|
fma.rn.f32 %f899, %f898, %f890, %f897;
|
|
add.rn.f32 %f900, %f894, %f899;
|
|
neg.f32 %f901, %f900;
|
|
add.rn.f32 %f902, %f894, %f901;
|
|
add.rn.f32 %f903, %f902, %f899;
|
|
mov.b32 %r286, %f900;
|
|
setp.eq.s32 %p120, %r286, 1118925336;
|
|
add.s32 %r287, %r286, -1;
|
|
mov.b32 %f904, %r287;
|
|
add.f32 %f905, %f903, 0f37000000;
|
|
selp.f32 %f209, %f905, %f903, %p120;
|
|
selp.f32 %f906, %f904, %f900, %p120;
|
|
mov.f32 %f907, 0f3FB8AA3B;
|
|
mul.rn.f32 %f908, %f906, %f907;
|
|
cvt.rzi.f32.f32 %f909, %f908;
|
|
abs.f32 %f910, %f909;
|
|
setp.gt.f32 %p121, %f910, 0f42FC0000;
|
|
mov.b32 %r288, %f909;
|
|
and.b32 %r289, %r288, -2147483648;
|
|
or.b32 %r290, %r289, 1123811328;
|
|
mov.b32 %f911, %r290;
|
|
selp.f32 %f912, %f911, %f909, %p121;
|
|
mov.f32 %f913, 0fBF317218;
|
|
fma.rn.f32 %f914, %f912, %f913, %f906;
|
|
mov.f32 %f915, 0f3102E308;
|
|
fma.rn.f32 %f916, %f912, %f915, %f914;
|
|
mul.f32 %f917, %f916, 0f3FB8AA3B;
|
|
add.f32 %f918, %f912, 0f4B40007F;
|
|
mov.b32 %r291, %f918;
|
|
shl.b32 %r292, %r291, 23;
|
|
mov.b32 %f919, %r292;
|
|
ex2.approx.ftz.f32 %f920, %f917;
|
|
mul.f32 %f210, %f920, %f919;
|
|
setp.eq.f32 %p122, %f210, 0f7F800000;
|
|
mov.f32 %f1205, 0f7F800000;
|
|
@%p122 bra $L__BB0_99;
|
|
|
|
fma.rn.f32 %f1205, %f210, %f209, %f210;
|
|
|
|
$L__BB0_99:
|
|
setp.lt.f32 %p123, %f184, 0f00000000;
|
|
and.pred %p6, %p123, %p96;
|
|
setp.eq.f32 %p125, %f184, 0f00000000;
|
|
@%p125 bra $L__BB0_103;
|
|
bra.uni $L__BB0_100;
|
|
|
|
$L__BB0_103:
|
|
add.f32 %f925, %f184, %f184;
|
|
selp.f32 %f1207, %f925, 0f00000000, %p96;
|
|
bra.uni $L__BB0_104;
|
|
|
|
$L__BB0_100:
|
|
mov.b32 %r293, %f1205;
|
|
xor.b32 %r294, %r293, -2147483648;
|
|
mov.b32 %f921, %r294;
|
|
selp.f32 %f1207, %f921, %f1205, %p6;
|
|
setp.geu.f32 %p126, %f184, 0f00000000;
|
|
@%p126 bra $L__BB0_104;
|
|
|
|
mov.f32 %f922, 0f3ED55555;
|
|
cvt.rzi.f32.f32 %f923, %f922;
|
|
setp.eq.f32 %p127, %f923, 0f3ED55555;
|
|
@%p127 bra $L__BB0_104;
|
|
|
|
mov.f32 %f1207, 0f7FFFFFFF;
|
|
|
|
$L__BB0_104:
|
|
mov.f32 %f1095, 0f00000000;
|
|
max.f32 %f1094, %f1095, %f678;
|
|
abs.f32 %f1093, %f1094;
|
|
add.f32 %f926, %f1093, 0f3ED55555;
|
|
mov.b32 %r295, %f926;
|
|
setp.lt.s32 %p129, %r295, 2139095040;
|
|
@%p129 bra $L__BB0_109;
|
|
|
|
mov.f32 %f1098, 0f00000000;
|
|
max.f32 %f1097, %f1098, %f678;
|
|
abs.f32 %f1096, %f1097;
|
|
setp.gtu.f32 %p130, %f1096, 0f7F800000;
|
|
@%p130 bra $L__BB0_108;
|
|
bra.uni $L__BB0_106;
|
|
|
|
$L__BB0_108:
|
|
add.f32 %f1207, %f184, 0f3ED55555;
|
|
bra.uni $L__BB0_109;
|
|
|
|
$L__BB0_106:
|
|
mov.f32 %f1101, 0f00000000;
|
|
max.f32 %f1100, %f1101, %f678;
|
|
abs.f32 %f1099, %f1100;
|
|
setp.neu.f32 %p131, %f1099, 0f7F800000;
|
|
@%p131 bra $L__BB0_109;
|
|
|
|
selp.f32 %f1207, 0fFF800000, 0f7F800000, %p6;
|
|
|
|
$L__BB0_109:
|
|
mov.f32 %f1110, 0f00000000;
|
|
max.f32 %f1109, %f1110, %f675;
|
|
ld.const.u64 %rd104, [params+144];
|
|
cvta.to.global.u64 %rd103, %rd104;
|
|
ld.const.u32 %r346, [params+136];
|
|
mad.lo.s32 %r345, %r346, %r5, %r4;
|
|
cvt.u64.u32 %rd102, %r345;
|
|
fma.rn.f32 %f927, %f1201, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p132, %f1109, 0f3F800000;
|
|
mov.f32 %f928, 0f3F800000;
|
|
selp.f32 %f929, 0f3F7FFFFF, %f927, %p132;
|
|
mul.f32 %f930, %f1109, 0f414EB852;
|
|
setp.lt.f32 %p133, %f1109, 0f3B4D2E1C;
|
|
selp.f32 %f931, %f930, %f929, %p133;
|
|
fma.rn.f32 %f932, %f1204, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p134, %f183, 0f3F800000;
|
|
selp.f32 %f933, 0f3F7FFFFF, %f932, %p134;
|
|
mul.f32 %f934, %f183, 0f414EB852;
|
|
setp.lt.f32 %p135, %f183, 0f3B4D2E1C;
|
|
selp.f32 %f935, %f934, %f933, %p135;
|
|
fma.rn.f32 %f936, %f1207, 0f3F870A3D, 0fBD6147AE;
|
|
setp.eq.f32 %p136, %f184, 0f3F800000;
|
|
selp.f32 %f937, 0f3F7FFFFF, %f936, %p136;
|
|
mul.f32 %f938, %f184, 0f414EB852;
|
|
setp.lt.f32 %p137, %f184, 0f3B4D2E1C;
|
|
selp.f32 %f939, %f938, %f937, %p137;
|
|
min.f32 %f940, %f931, %f928;
|
|
mov.f32 %f941, 0f00000000;
|
|
max.f32 %f942, %f941, %f940;
|
|
mul.f32 %f943, %f942, 0f43800000;
|
|
cvt.rzi.u32.f32 %r296, %f943;
|
|
min.u32 %r297, %r296, 255;
|
|
min.f32 %f944, %f935, %f928;
|
|
max.f32 %f945, %f941, %f944;
|
|
mul.f32 %f946, %f945, 0f43800000;
|
|
cvt.rzi.u32.f32 %r298, %f946;
|
|
min.u32 %r299, %r298, 255;
|
|
min.f32 %f947, %f939, %f928;
|
|
max.f32 %f948, %f941, %f947;
|
|
mul.f32 %f949, %f948, 0f43800000;
|
|
cvt.rzi.u32.f32 %r300, %f949;
|
|
min.u32 %r301, %r300, 255;
|
|
shl.b64 %rd66, %rd102, 2;
|
|
add.s64 %rd67, %rd103, %rd66;
|
|
cvt.u16.u32 %rs15, %r301;
|
|
cvt.u16.u32 %rs16, %r299;
|
|
cvt.u16.u32 %rs17, %r297;
|
|
mov.u16 %rs18, 255;
|
|
st.global.v4.u8 [%rd67], {%rs17, %rs16, %rs15, %rs18};
|
|
|
|
$L__BB0_110:
|
|
ld.const.u32 %r347, [params+104];
|
|
and.b32 %r302, %r347, 4;
|
|
setp.eq.s32 %p138, %r302, 0;
|
|
ld.const.u32 %r359, [params+108];
|
|
@%p138 bra $L__BB0_114;
|
|
|
|
setp.eq.s32 %p139, %r359, 0;
|
|
ld.const.u64 %rd68, [params+224];
|
|
cvta.to.global.u64 %rd69, %rd68;
|
|
ld.const.u32 %r303, [params+216];
|
|
mad.lo.s32 %r304, %r303, %r5, %r4;
|
|
mul.wide.u32 %rd70, %r304, 8;
|
|
add.s64 %rd19, %rd69, %rd70;
|
|
@%p139 bra $L__BB0_113;
|
|
|
|
ld.global.v4.u16 {%rs26, %rs27, %rs28, %rs29}, [%rd19];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f950, %rs26;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f951, %rs27;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f952, %rs28;}
|
|
|
|
// end inline asm
|
|
add.f32 %f953, %f143, %f950;
|
|
add.f32 %f954, %f144, %f951;
|
|
add.f32 %f955, %f145, %f952;
|
|
mov.f32 %f956, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs24, %f955;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs23, %f954;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs22, %f953;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs25, %f956;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs22, %rs23, %rs24, %rs25};
|
|
bra.uni $L__BB0_114;
|
|
|
|
$L__BB0_113:
|
|
mov.f32 %f960, 0f3F800000;
|
|
mov.u32 %r359, 0;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs33, %f960;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs32, %f145;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs31, %f144;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs30, %f143;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd19], {%rs30, %rs31, %rs32, %rs33};
|
|
|
|
$L__BB0_114:
|
|
mul.f32 %f961, %f128, %f418;
|
|
mul.f32 %f219, %f961, 0f3F000000;
|
|
mul.f32 %f962, %f129, %f419;
|
|
mul.f32 %f220, %f962, 0f3F000000;
|
|
mul.f32 %f963, %f130, %f420;
|
|
mul.f32 %f221, %f963, 0f3F000000;
|
|
mul.f32 %f222, %f131, %f418;
|
|
mul.f32 %f223, %f132, %f419;
|
|
mul.f32 %f224, %f133, %f420;
|
|
mul.f32 %f225, %f134, %f418;
|
|
mul.f32 %f226, %f135, %f419;
|
|
mul.f32 %f227, %f136, %f420;
|
|
mul.f32 %f228, %f137, %f418;
|
|
mul.f32 %f229, %f138, %f419;
|
|
mul.f32 %f230, %f139, %f420;
|
|
ld.const.u64 %rd71, [params+256];
|
|
cvta.to.global.u64 %rd72, %rd71;
|
|
ld.const.u32 %r306, [params+248];
|
|
mad.lo.s32 %r307, %r306, %r5, %r4;
|
|
mul.wide.u32 %rd73, %r307, 8;
|
|
add.s64 %rd20, %rd72, %rd73;
|
|
setp.eq.s32 %p140, %r359, 0;
|
|
@%p140 bra $L__BB0_116;
|
|
|
|
ld.global.v4.u16 {%rs41, %rs42, %rs43, %rs44}, [%rd20];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f964, %rs41;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f965, %rs42;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f966, %rs43;}
|
|
|
|
// end inline asm
|
|
add.f32 %f967, %f219, %f964;
|
|
add.f32 %f968, %f220, %f965;
|
|
add.f32 %f969, %f221, %f966;
|
|
mov.f32 %f970, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs39, %f969;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs38, %f968;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs37, %f967;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs40, %f970;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs37, %rs38, %rs39, %rs40};
|
|
bra.uni $L__BB0_117;
|
|
|
|
$L__BB0_116:
|
|
mov.f32 %f974, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs48, %f974;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs47, %f221;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs46, %f220;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs45, %f219;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd20], {%rs45, %rs46, %rs47, %rs48};
|
|
|
|
$L__BB0_117:
|
|
mov.f32 %f975, 0f34000000;
|
|
max.f32 %f976, %f219, %f975;
|
|
mul.f32 %f977, %f222, 0f3F000000;
|
|
div.rn.f32 %f978, %f977, %f976;
|
|
max.f32 %f979, %f220, %f975;
|
|
mul.f32 %f980, %f223, 0f3F000000;
|
|
div.rn.f32 %f981, %f980, %f979;
|
|
max.f32 %f982, %f221, %f975;
|
|
mul.f32 %f983, %f224, 0f3F000000;
|
|
div.rn.f32 %f984, %f983, %f982;
|
|
fma.rn.f32 %f231, %f978, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f232, %f981, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f233, %f984, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f985, %f225, 0f3F000000;
|
|
div.rn.f32 %f986, %f985, %f976;
|
|
mul.f32 %f987, %f226, 0f3F000000;
|
|
div.rn.f32 %f988, %f987, %f979;
|
|
mul.f32 %f989, %f227, 0f3F000000;
|
|
div.rn.f32 %f990, %f989, %f982;
|
|
fma.rn.f32 %f234, %f986, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f235, %f988, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f236, %f990, 0f3F000000, 0f3F000000;
|
|
mul.f32 %f991, %f228, 0f3F000000;
|
|
div.rn.f32 %f992, %f991, %f976;
|
|
mul.f32 %f993, %f229, 0f3F000000;
|
|
div.rn.f32 %f994, %f993, %f979;
|
|
mul.f32 %f995, %f230, 0f3F000000;
|
|
div.rn.f32 %f996, %f995, %f982;
|
|
fma.rn.f32 %f237, %f992, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f238, %f994, 0f3F000000, 0f3F000000;
|
|
fma.rn.f32 %f239, %f996, 0f3F000000, 0f3F000000;
|
|
ld.const.u64 %rd74, [params+272];
|
|
cvta.to.global.u64 %rd75, %rd74;
|
|
ld.const.u32 %r308, [params+264];
|
|
mad.lo.s32 %r309, %r308, %r5, %r4;
|
|
mul.wide.u32 %rd76, %r309, 8;
|
|
add.s64 %rd21, %rd75, %rd76;
|
|
@%p140 bra $L__BB0_119;
|
|
|
|
ld.global.v4.u16 {%rs56, %rs57, %rs58, %rs59}, [%rd21];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f997, %rs56;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f998, %rs57;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f999, %rs58;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1000, %f231, %f997;
|
|
add.f32 %f1001, %f232, %f998;
|
|
add.f32 %f1002, %f233, %f999;
|
|
mov.f32 %f1003, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs54, %f1002;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs53, %f1001;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs52, %f1000;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs55, %f1003;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs52, %rs53, %rs54, %rs55};
|
|
bra.uni $L__BB0_120;
|
|
|
|
$L__BB0_119:
|
|
mov.f32 %f1007, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs63, %f1007;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs62, %f233;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs61, %f232;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs60, %f231;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd21], {%rs60, %rs61, %rs62, %rs63};
|
|
|
|
$L__BB0_120:
|
|
ld.const.u64 %rd77, [params+288];
|
|
cvta.to.global.u64 %rd78, %rd77;
|
|
ld.const.u32 %r310, [params+280];
|
|
mad.lo.s32 %r311, %r310, %r5, %r4;
|
|
mul.wide.u32 %rd79, %r311, 8;
|
|
add.s64 %rd22, %rd78, %rd79;
|
|
@%p140 bra $L__BB0_122;
|
|
|
|
ld.global.v4.u16 {%rs71, %rs72, %rs73, %rs74}, [%rd22];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1008, %rs71;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1009, %rs72;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1010, %rs73;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1011, %f234, %f1008;
|
|
add.f32 %f1012, %f235, %f1009;
|
|
add.f32 %f1013, %f236, %f1010;
|
|
mov.f32 %f1014, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs69, %f1013;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs68, %f1012;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs67, %f1011;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs70, %f1014;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs67, %rs68, %rs69, %rs70};
|
|
bra.uni $L__BB0_123;
|
|
|
|
$L__BB0_122:
|
|
mov.f32 %f1018, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs78, %f1018;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs77, %f236;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs76, %f235;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs75, %f234;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd22], {%rs75, %rs76, %rs77, %rs78};
|
|
|
|
$L__BB0_123:
|
|
ld.const.u64 %rd80, [params+304];
|
|
cvta.to.global.u64 %rd81, %rd80;
|
|
ld.const.u32 %r312, [params+296];
|
|
mad.lo.s32 %r313, %r312, %r5, %r4;
|
|
mul.wide.u32 %rd82, %r313, 8;
|
|
add.s64 %rd23, %rd81, %rd82;
|
|
@%p140 bra $L__BB0_125;
|
|
|
|
ld.global.v4.u16 {%rs86, %rs87, %rs88, %rs89}, [%rd23];
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1019, %rs86;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1020, %rs87;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.f32.f16 %f1021, %rs88;}
|
|
|
|
// end inline asm
|
|
add.f32 %f1022, %f237, %f1019;
|
|
add.f32 %f1023, %f238, %f1020;
|
|
add.f32 %f1024, %f239, %f1021;
|
|
mov.f32 %f1025, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs84, %f1024;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs83, %f1023;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs82, %f1022;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs85, %f1025;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs82, %rs83, %rs84, %rs85};
|
|
bra.uni $L__BB0_144;
|
|
|
|
$L__BB0_125:
|
|
mov.f32 %f1029, 0f3F800000;
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs93, %f1029;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs92, %f239;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs91, %f238;}
|
|
|
|
// end inline asm
|
|
// begin inline asm
|
|
{ cvt.rn.f16.f32 %rs90, %f237;}
|
|
|
|
// end inline asm
|
|
st.global.v4.u16 [%rd23], {%rs90, %rs91, %rs92, %rs93};
|
|
|
|
$L__BB0_144:
|
|
ret;
|
|
|
|
}
|
|
|