200 lines
5.2 KiB
Plaintext
200 lines
5.2 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-31968024
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// Cuda compilation tools, release 12.0, V12.0.76
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// Based on NVVM 7.0.1
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//
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.version 8.0
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.target sm_52
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.address_size 64
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// .globl oxMain
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.const .align 16 .b8 params[1184];
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.visible .entry oxMain()
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{
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.reg .pred %p<5>;
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.reg .b16 %rs<29>;
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.reg .f32 %f<91>;
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.reg .b32 %r<31>;
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.reg .b64 %rd<21>;
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mov.u32 %r3, %ctaid.x;
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mov.u32 %r4, %ntid.x;
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mov.u32 %r5, %tid.x;
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mad.lo.s32 %r1, %r3, %r4, %r5;
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mov.u32 %r6, %ntid.y;
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mov.u32 %r7, %ctaid.y;
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mov.u32 %r8, %tid.y;
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mad.lo.s32 %r2, %r7, %r6, %r8;
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ld.const.u64 %rd3, [params+1144];
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cvta.to.global.u64 %rd4, %rd3;
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ld.const.u32 %r9, [params+1136];
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mad.lo.s32 %r10, %r9, %r2, %r1;
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mul.wide.u32 %rd5, %r10, 8;
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add.s64 %rd6, %rd4, %rd5;
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ld.global.u16 %rs8, [%rd6];
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// begin inline asm
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{ cvt.f32.f16 %f17, %rs8;}
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// end inline asm
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ld.global.u16 %rs9, [%rd6+2];
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// begin inline asm
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{ cvt.f32.f16 %f18, %rs9;}
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// end inline asm
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ld.global.u16 %rs10, [%rd6+4];
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// begin inline asm
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{ cvt.f32.f16 %f19, %rs10;}
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// end inline asm
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mul.f32 %f20, %f18, 0f3F372474;
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fma.rn.f32 %f21, %f17, 0f3E59999A, %f20;
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fma.rn.f32 %f22, %f19, 0f3D93A92A, %f21;
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ld.const.u64 %rd7, [params+160];
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cvta.to.global.u64 %rd8, %rd7;
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ld.const.u32 %r11, [params+152];
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mad.lo.s32 %r12, %r11, %r2, %r1;
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mul.wide.u32 %rd9, %r12, 16;
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add.s64 %rd1, %rd8, %rd9;
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ld.global.v4.f32 {%f23, %f24, %f25, %f26}, [%rd1];
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ld.const.u64 %rd10, [params+144];
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cvta.to.global.u64 %rd11, %rd10;
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ld.const.u32 %r13, [params+136];
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mad.lo.s32 %r14, %r13, %r2, %r1;
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mul.wide.u32 %rd12, %r14, 4;
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add.s64 %rd13, %rd11, %rd12;
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ld.global.v4.u8 {%rs11, %rs12, %rs13, %rs14}, [%rd13];
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cvt.rn.f32.u16 %f30, %rs11;
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div.rn.f32 %f31, %f30, 0f437F0000;
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fma.rn.f32 %f32, %f31, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f33, %rs12;
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div.rn.f32 %f34, %f33, 0f437F0000;
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fma.rn.f32 %f35, %f34, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f36, %rs13;
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div.rn.f32 %f37, %f36, 0f437F0000;
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fma.rn.f32 %f38, %f37, 0f40000000, 0fBF800000;
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mul.f32 %f39, %f35, %f35;
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fma.rn.f32 %f40, %f32, %f32, %f39;
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fma.rn.f32 %f41, %f38, %f38, %f40;
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sqrt.rn.f32 %f42, %f41;
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rcp.rn.f32 %f43, %f42;
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mul.f32 %f44, %f32, %f43;
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mul.f32 %f45, %f35, %f43;
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mul.f32 %f46, %f43, %f38;
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fma.rn.f32 %f47, %f22, %f44, %f23;
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fma.rn.f32 %f48, %f22, %f45, %f24;
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fma.rn.f32 %f49, %f22, %f46, %f25;
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cvt.rn.f32.u16 %f50, %rs14;
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div.rn.f32 %f51, %f50, 0f437F0000;
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ld.global.f32 %f52, [%rd1+12];
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min.f32 %f90, %f51, %f52;
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mul.f32 %f2, %f47, %f90;
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mul.f32 %f3, %f48, %f90;
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mul.f32 %f4, %f49, %f90;
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ld.const.f32 %f53, [params+1168];
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setp.gt.f32 %p1, %f53, 0f3F000000;
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@%p1 bra $L__BB0_2;
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bra.uni $L__BB0_1;
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$L__BB0_2:
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mul.f32 %f54, %f3, %f3;
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fma.rn.f32 %f55, %f2, %f2, %f54;
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fma.rn.f32 %f56, %f4, %f4, %f55;
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sqrt.rn.f32 %f57, %f56;
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rcp.rn.f32 %f58, %f57;
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mul.f32 %f5, %f2, %f58;
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mul.f32 %f6, %f3, %f58;
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mul.f32 %f7, %f4, %f58;
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ld.const.u64 %rd14, [params+400];
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cvta.to.global.u64 %rd15, %rd14;
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ld.const.u32 %r15, [params+392];
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mad.lo.s32 %r16, %r15, %r2, %r1;
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mul.wide.u32 %rd16, %r16, 4;
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add.s64 %rd2, %rd15, %rd16;
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ld.global.v2.u8 {%rs15, %rs28}, [%rd2];
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or.b16 %rs17, %rs15, %rs28;
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and.b16 %rs18, %rs17, 255;
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setp.eq.s16 %p2, %rs18, 0;
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@%p2 bra $L__BB0_4;
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ld.global.u8 %rs27, [%rd2+2];
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bra.uni $L__BB0_5;
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$L__BB0_1:
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st.global.v4.f32 [%rd1], {%f2, %f3, %f4, %f90};
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bra.uni $L__BB0_9;
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$L__BB0_4:
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ld.global.u8 %rs27, [%rd2+2];
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setp.eq.s16 %p3, %rs27, 0;
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mov.f32 %f87, 0f00000000;
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mov.u16 %rs28, 0;
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mov.f32 %f88, %f87;
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mov.f32 %f89, %f87;
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@%p3 bra $L__BB0_6;
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$L__BB0_5:
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cvt.rn.f32.u16 %f62, %rs15;
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div.rn.f32 %f63, %f62, 0f437F0000;
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fma.rn.f32 %f64, %f63, 0f40000000, 0fBF800000;
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and.b16 %rs21, %rs28, 255;
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cvt.rn.f32.u16 %f65, %rs21;
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div.rn.f32 %f66, %f65, 0f437F0000;
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fma.rn.f32 %f67, %f66, 0f40000000, 0fBF800000;
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cvt.rn.f32.u16 %f68, %rs27;
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div.rn.f32 %f69, %f68, 0f437F0000;
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fma.rn.f32 %f70, %f69, 0f40000000, 0fBF800000;
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mul.f32 %f71, %f67, %f67;
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fma.rn.f32 %f72, %f64, %f64, %f71;
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fma.rn.f32 %f73, %f70, %f70, %f72;
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sqrt.rn.f32 %f74, %f73;
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rcp.rn.f32 %f75, %f74;
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mul.f32 %f89, %f75, %f70;
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mul.f32 %f88, %f75, %f67;
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mul.f32 %f87, %f64, %f75;
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$L__BB0_6:
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mul.f32 %f76, %f6, %f88;
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fma.rn.f32 %f77, %f5, %f87, %f76;
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fma.rn.f32 %f14, %f7, %f89, %f77;
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setp.leu.f32 %p4, %f90, 0f00000000;
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@%p4 bra $L__BB0_8;
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fma.rn.f32 %f78, %f14, 0f3F000000, 0f3F000000;
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mov.f32 %f79, 0f3B808081;
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max.f32 %f90, %f78, %f79;
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$L__BB0_8:
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ld.const.u64 %rd17, [params+1160];
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cvta.to.global.u64 %rd18, %rd17;
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ld.const.u32 %r21, [params+1152];
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mad.lo.s32 %r26, %r21, %r2, %r1;
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fma.rn.f32 %f80, %f5, 0f3F000000, 0f3F000000;
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mul.f32 %f81, %f80, 0f437F0000;
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cvt.rzi.u32.f32 %r27, %f81;
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fma.rn.f32 %f82, %f6, 0f3F000000, 0f3F000000;
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mul.f32 %f83, %f82, 0f437F0000;
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cvt.rzi.u32.f32 %r28, %f83;
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fma.rn.f32 %f84, %f7, 0f3F000000, 0f3F000000;
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mul.f32 %f85, %f84, 0f437F0000;
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cvt.rzi.u32.f32 %r29, %f85;
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mul.f32 %f86, %f90, 0f437F0000;
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cvt.rzi.u32.f32 %r30, %f86;
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mul.wide.u32 %rd19, %r26, 4;
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add.s64 %rd20, %rd18, %rd19;
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cvt.u16.u32 %rs23, %r30;
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cvt.u16.u32 %rs24, %r29;
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cvt.u16.u32 %rs25, %r28;
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cvt.u16.u32 %rs26, %r27;
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st.global.v4.u8 [%rd20], {%rs26, %rs25, %rs24, %rs23};
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$L__BB0_9:
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ret;
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}
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